Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
f70bb92deabc608a5d5fa414ef81c6e0facd7fa8
commit
f70bb92deabc608a5d5fa414ef81c6e0facd7fa8
[
log
]
[
tgz
]
author
AmoghLonkar <alonkar@ucsc.edu>
Thu Jun 17 14:02:56 2021 -0700
committer
AmoghLonkar <alonkar@ucsc.edu>
Thu Jun 17 14:02:56 2021 -0700
tree
809d3f76eccdc01f59d52de688fda4eb77dfcca3
parent
d617e93156c0e08af3f4da9ee3b3925994ceb63d
[
diff
]
Added global csr pin
verilog/dv/gpio_test/gpio_test.c
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diff
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verilog/dv/gpio_test/gpio_test_tb.v
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diff
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verilog/rtl/openram_testchip.v
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diff
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verilog/rtl/user_project_wrapper.v
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diff
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4 files changed
tree: 809d3f76eccdc01f59d52de688fda4eb77dfcca3
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
single_port/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.