Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main
diff --git a/openlane/openram_testchip/config.tcl b/openlane/openram_testchip/config.tcl
index de26d8b..8195c4f 100644
--- a/openlane/openram_testchip/config.tcl
+++ b/openlane/openram_testchip/config.tcl
@@ -8,27 +8,27 @@
set ::env(VERILOG_FILES) "$script_dir/../../verilog/rtl/openram_defines.v \
$script_dir/../../verilog/rtl/openram_testchip.v"
-set ::env(BASE_SDC_FILE) "$script_dir/openram_testchip.sdc"
+#set ::env(BASE_SDC_FILE) "$script_dir/openram_testchip.sdc"
-set ::env(CLOCK_PORT) "clk"
-set ::env(CLOCK_NET) "clk sram_clk"
+set ::env(CLOCK_PORT) "la_clk"
+set ::env(CLOCK_NET) "clk"
#set ::env(CLOCK_NET) ""
set ::env(CLOCK_PERIOD) "20"
set ::env(IO_PCT) 0.1
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 400 2600"
+set ::env(DIE_AREA) "0 0 400 2200"
set ::env(DESIGN_IS_CORE) 0
-set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
-set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+set ::env(VDD_NETS) [list {vccd1}]
+set ::env(GND_NETS) [list {vssd1}]
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
#set ::env(SYNTH_NO_FLAT) 1
set ::env(GLB_RT_ADJUSTMENT) 0.20
set ::env(RUN_KLAYOUT_DRC) 0
-set ::env(PL_TARGET_DENSITY) 0.40
+set ::env(PL_TARGET_DENSITY) 0.25
# This doesn't check for supply connectivity:
set ::env(FP_PDN_CHECK_NODES) 0
diff --git a/openlane/openram_testchip/openram_testchip.sdc b/openlane/openram_testchip/openram_testchip.sdc
index 644e49a..5f91463 100644
--- a/openlane/openram_testchip/openram_testchip.sdc
+++ b/openlane/openram_testchip/openram_testchip.sdc
@@ -15,6 +15,9 @@
# correct resetn
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
+#set clk_indx [lsearch [all_outputs] [get_port sram*_clk]]
+#set all_outputs_wo_clk [lreplace [all_outputs] $clk_indx $clk_indx]
+#set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_outputs_wo_clk
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
diff --git a/openlane/openram_testchip/pin_order.cfg b/openlane/openram_testchip/pin_order.cfg
index 2031dcb..9402f88 100644
--- a/openlane/openram_testchip/pin_order.cfg
+++ b/openlane/openram_testchip/pin_order.cfg
@@ -8,39 +8,23 @@
la_.*
#E
-sram0_clk
sram0_data[0-1]
-sram1_clk
sram1_data[0-1]
-sram2_clk
sram2_data[0-1]
-sram3_clk
sram3_data[0-1]
right_data[0-1]
-sram4_clk
sram4_data[0-1]
-sram5_clk
sram5_data[0-1]
-sram6_clk
sram6_data[0-1]
-sram7_clk
sram7_data[0-1]
#WR
-sram8_clk
sram8_data[0-1]
-sram9_clk
sram9_data[0-1]
-sram10_clk
sram10_data[0-1]
-sram11_clk
sram11_data[0-1]
left_data[0-1]
-sram12_clk
sram12_data[0-1]
-sram13_clk
sram13_data[0-1]
-sram14_clk
sram14_data[0-1]
-sram15_clk
sram15_data[0-1]
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index f40c1d4..6748289 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -30,10 +30,10 @@
$script_dir/../../verilog/rtl/user_project_wrapper.v "
## Clock configurations
-set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "wb_clk_i"
+set ::env(CLOCK_PORT) "la_sram_clk"
+set ::env(CLOCK_NET) "sram_clk"
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD) "20"
## Internal Macros
### Macro Placement
@@ -86,11 +86,11 @@
# Placement config
set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
-
+set ::env(PL_DIAMOND_SEARCH_HEIGHT) 500
set ::env(PL_RANDOM_GLB_PLACEMENT) 1
-set ::env(GLB_RT_ADJUSTMENT) 0.15
-set ::env(PL_TARGET_DENSITY) 0.35
+set ::env(GLB_RT_ADJUSTMENT) 0.10
+set ::env(PL_TARGET_DENSITY) 0.7
#set ::env(MAGIC_DRC_USE_GDS) 0
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 9a9ef9c..ed4bc40 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -48,4 +48,4 @@
# 823 x 335
SRAM8 2000 2600 N
-CONTROL_LOGIC 1475 100 N
+CONTROL_LOGIC 1300 100 N
diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
index c9125b5..58c8bf2 100644
--- a/verilog/rtl/openram_testchip.v
+++ b/verilog/rtl/openram_testchip.v
@@ -16,50 +16,48 @@
input in_select,
input la_clk,
- input la_sram_clk,
input la_in_load,
input la_sram_load,
input [`TOTAL_SIZE-1:0] la_data_in,
// GPIO bit to clock control register
input gpio_clk,
input gpio_in,
- input gpio_sram_clk,
input gpio_scan,
input gpio_sram_load,
// SRAM data outputs to be captured
- input [`DATA_SIZE-1:0] sram0_dout0,
- input [`DATA_SIZE-1:0] sram0_dout1,
- input [`DATA_SIZE-1:0] sram1_dout0,
- input [`DATA_SIZE-1:0] sram1_dout1,
- input [`DATA_SIZE-1:0] sram2_dout0,
- input [`DATA_SIZE-1:0] sram2_dout1,
- input [`DATA_SIZE-1:0] sram3_dout0,
- input [`DATA_SIZE-1:0] sram3_dout1,
- input [`DATA_SIZE-1:0] sram4_dout0,
- input [`DATA_SIZE-1:0] sram4_dout1,
- input [`DATA_SIZE-1:0] sram5_dout0,
- input [`DATA_SIZE-1:0] sram5_dout1,
- input [`DATA_SIZE-1:0] sram6_dout0,
- input [`DATA_SIZE-1:0] sram6_dout1,
- input [`DATA_SIZE-1:0] sram7_dout0,
- input [`DATA_SIZE-1:0] sram7_dout1,
- input [`DATA_SIZE-1:0] sram8_dout0,
- input [`DATA_SIZE-1:0] sram8_dout1,
- input [`DATA_SIZE-1:0] sram9_dout0,
- input [`DATA_SIZE-1:0] sram9_dout1,
- input [`DATA_SIZE-1:0] sram10_dout0,
- input [`DATA_SIZE-1:0] sram10_dout1,
- input [`DATA_SIZE-1:0] sram11_dout0,
- input [`DATA_SIZE-1:0] sram11_dout1,
- input [`DATA_SIZE-1:0] sram12_dout0,
- input [`DATA_SIZE-1:0] sram12_dout1,
- input [`DATA_SIZE-1:0] sram13_dout0,
- input [`DATA_SIZE-1:0] sram13_dout1,
- input [`DATA_SIZE-1:0] sram14_dout0,
- input [`DATA_SIZE-1:0] sram14_dout1,
- input [`DATA_SIZE-1:0] sram15_dout0,
- input [`DATA_SIZE-1:0] sram15_dout1,
+ input [`DATA_SIZE-1:0] sram0_data0,
+ input [`DATA_SIZE-1:0] sram0_data1,
+ input [`DATA_SIZE-1:0] sram1_data0,
+ input [`DATA_SIZE-1:0] sram1_data1,
+ input [`DATA_SIZE-1:0] sram2_data0,
+ input [`DATA_SIZE-1:0] sram2_data1,
+ input [`DATA_SIZE-1:0] sram3_data0,
+ input [`DATA_SIZE-1:0] sram3_data1,
+ input [`DATA_SIZE-1:0] sram4_data0,
+ input [`DATA_SIZE-1:0] sram4_data1,
+ input [`DATA_SIZE-1:0] sram5_data0,
+ input [`DATA_SIZE-1:0] sram5_data1,
+ input [`DATA_SIZE-1:0] sram6_data0,
+ input [`DATA_SIZE-1:0] sram6_data1,
+ input [`DATA_SIZE-1:0] sram7_data0,
+ input [`DATA_SIZE-1:0] sram7_data1,
+ input [`DATA_SIZE-1:0] sram8_data0,
+ input [`DATA_SIZE-1:0] sram8_data1,
+ input [`DATA_SIZE-1:0] sram9_data0,
+ input [`DATA_SIZE-1:0] sram9_data1,
+ input [`DATA_SIZE-1:0] sram10_data0,
+ input [`DATA_SIZE-1:0] sram10_data1,
+ input [`DATA_SIZE-1:0] sram11_data0,
+ input [`DATA_SIZE-1:0] sram11_data1,
+ input [`DATA_SIZE-1:0] sram12_data0,
+ input [`DATA_SIZE-1:0] sram12_data1,
+ input [`DATA_SIZE-1:0] sram13_data0,
+ input [`DATA_SIZE-1:0] sram13_data1,
+ input [`DATA_SIZE-1:0] sram14_data0,
+ input [`DATA_SIZE-1:0] sram14_data1,
+ input [`DATA_SIZE-1:0] sram15_data0,
+ input [`DATA_SIZE-1:0] sram15_data1,
// Shared control/data to the SRAMs
output reg [`ADDR_SIZE-1:0] left_addr0,
@@ -83,70 +81,17 @@
// One CSB for each SRAM
output [`MAX_CHIPS-1:0] right_csb0,
- // Clocks for each SRAM
- output reg sram0_clk,
- output reg sram1_clk,
- output reg sram2_clk,
- output reg sram3_clk,
- output reg sram4_clk,
- output reg sram5_clk,
- output reg sram6_clk,
- output reg sram7_clk,
- output reg sram8_clk,
- output reg sram9_clk,
- output reg sram10_clk,
- output reg sram11_clk,
- output reg sram12_clk,
- output reg sram13_clk,
- output reg sram14_clk,
- output reg sram15_clk,
output reg [`TOTAL_SIZE-1:0] la_data_out,
output reg gpio_out
);
reg clk;
- reg sram_clk;
// Store input instruction
reg [`TOTAL_SIZE-1:0] sram_register;
reg csb0_temp;
reg csb1_temp;
-// Hold dout from SRAM
-// clocked by SRAM clk
- reg [`DATA_SIZE-1:0] sram0_data0;
- reg [`DATA_SIZE-1:0] sram0_data1;
- reg [`DATA_SIZE-1:0] sram1_data0;
- reg [`DATA_SIZE-1:0] sram1_data1;
- reg [`DATA_SIZE-1:0] sram2_data0;
- reg [`DATA_SIZE-1:0] sram2_data1;
- reg [`DATA_SIZE-1:0] sram3_data0;
- reg [`DATA_SIZE-1:0] sram3_data1;
- reg [`DATA_SIZE-1:0] sram4_data0;
- reg [`DATA_SIZE-1:0] sram4_data1;
- reg [`DATA_SIZE-1:0] sram5_data0;
- reg [`DATA_SIZE-1:0] sram5_data1;
- reg [`DATA_SIZE-1:0] sram6_data0;
- reg [`DATA_SIZE-1:0] sram6_data1;
- reg [`DATA_SIZE-1:0] sram7_data0;
- reg [`DATA_SIZE-1:0] sram7_data1;
- reg [`DATA_SIZE-1:0] sram8_data0;
- reg [`DATA_SIZE-1:0] sram8_data1;
- reg [`DATA_SIZE-1:0] sram9_data0;
- reg [`DATA_SIZE-1:0] sram9_data1;
- reg [`DATA_SIZE-1:0] sram10_data0;
- reg [`DATA_SIZE-1:0] sram10_data1;
- reg [`DATA_SIZE-1:0] sram11_data0;
- reg [`DATA_SIZE-1:0] sram11_data1;
- reg [`DATA_SIZE-1:0] sram12_data0;
- reg [`DATA_SIZE-1:0] sram12_data1;
- reg [`DATA_SIZE-1:0] sram13_data0;
- reg [`DATA_SIZE-1:0] sram13_data1;
- reg [`DATA_SIZE-1:0] sram14_data0;
- reg [`DATA_SIZE-1:0] sram14_data1;
- reg [`DATA_SIZE-1:0] sram15_data0;
- reg [`DATA_SIZE-1:0] sram15_data1;
-
// Mux output to connect final output data
// into sram_register
reg [`DATA_SIZE-1:0] read_data0;
@@ -167,23 +112,6 @@
//Selecting clock pin
always @(*) begin
clk = in_select ? gpio_clk : la_clk;
- sram_clk = in_select ? gpio_sram_clk : la_sram_clk;
- sram0_clk = sram_clk;
- sram1_clk = sram_clk;
- sram2_clk = sram_clk;
- sram3_clk = sram_clk;
- sram4_clk = sram_clk;
- sram5_clk = sram_clk;
- sram6_clk = sram_clk;
- sram7_clk = sram_clk;
- sram8_clk = sram_clk;
- sram9_clk = sram_clk;
- sram10_clk = sram_clk;
- sram11_clk = sram_clk;
- sram12_clk = sram_clk;
- sram13_clk = sram_clk;
- sram14_clk = sram_clk;
- sram15_clk = sram_clk;
end
always @ (posedge clk) begin
@@ -232,80 +160,7 @@
left_csb0 = csb0_temp << chip_select;
left_csb1 = csb1_temp << chip_select;
end
-
-
-// Store dout of each SRAM
-always @(posedge sram_clk) begin
- if(reset) begin
- sram0_data0 <= 0;
- sram0_data1 <= 0;
- sram1_data0 <= 0;
- sram1_data1 <= 0;
- sram2_data0 <= 0;
- sram2_data1 <= 0;
- sram3_data0 <= 0;
- sram3_data1 <= 0;
- sram4_data0 <= 0;
- sram4_data1 <= 0;
- sram5_data0 <= 0;
- sram5_data1 <= 0;
- sram6_data0 <= 0;
- sram6_data1 <= 0;
- sram7_data0 <= 0;
- sram7_data1 <= 0;
- sram8_data0 <= 0;
- sram8_data1 <= 0;
- sram9_data0 <= 0;
- sram9_data1 <= 0;
- sram10_data0 <= 0;
- sram10_data1 <= 0;
- sram11_data0 <= 0;
- sram11_data1 <= 0;
- sram12_data0 <= 0;
- sram12_data1 <= 0;
- sram13_data0 <= 0;
- sram13_data1 <= 0;
- sram14_data0 <= 0;
- sram14_data1 <= 0;
- sram15_data0 <= 0;
- sram15_data1 <= 0;
- end
- else begin
- sram0_data0 <= sram0_dout0;
- sram0_data1 <= sram0_dout1;
- sram1_data0 <= sram1_dout0;
- sram1_data1 <= sram1_dout1;
- sram2_data0 <= sram2_dout0;
- sram2_data1 <= sram2_dout1;
- sram3_data0 <= sram3_dout0;
- sram3_data1 <= sram3_dout1;
- sram4_data0 <= sram4_dout0;
- sram4_data1 <= sram4_dout1;
- sram5_data0 <= sram5_dout0;
- sram5_data1 <= sram5_dout1;
- sram6_data0 <= sram6_dout0;
- sram6_data1 <= sram6_dout1;
- sram7_data0 <= sram7_dout0;
- sram7_data1 <= sram7_dout1;
- sram8_data0 <= sram8_dout0;
- sram8_data1 <= sram8_dout1;
- sram9_data0 <= sram9_dout0;
- sram9_data1 <= sram9_dout1;
- sram10_data0 <= sram10_dout0;
- sram10_data1 <= sram10_dout1;
- sram11_data0 <= sram11_dout0;
- sram11_data1 <= sram11_dout1;
- sram12_data0 <= sram12_dout0;
- sram12_data1 <= sram12_dout1;
- sram13_data0 <= sram13_dout0;
- sram13_data1 <= sram13_dout1;
- sram14_data0 <= sram14_dout0;
- sram14_data1 <= sram14_dout1;
- sram15_data0 <= sram15_dout0;
- sram15_data1 <= sram15_dout1;
- end
-end
-
+
// Mux value of correct SRAM dout FF to feed into
// DFF clocked by la/gpio clk
always @ (*) begin
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index d74db1e..4d91ad8 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -125,96 +125,97 @@
wire [31:0] sram14_dout0;
wire [31:0] sram14_dout1;
-
+
+ wire in_select = io_in[16];
+ wire in_reset = io_in[15];
+ wire gpio_clk = io_in[17];
+ wire gpio_sram_clk = io_in[18];
+ wire gpio_scan = io_in[19];
+ wire gpio_sram_load = io_in[20];
+
+ // Only io_out[21] is output
+ assign io_oeb = ~(1'b1 << 21);
+ // Assign other outputs to 0
+ assign io_out[`MPRJ_IO_PADS:22] = 0;
+ wire gpio_out;
+ assign io_out[21] = gpio_out;
+ assign io_out[20:0] = 0;
+
+ wire la_sram_clk = la_data_in[126];
+
+ reg sram_clk;
+
+always @(*) begin
+ sram_clk = in_select ? gpio_sram_clk : la_sram_clk;
+end
openram_testchip CONTROL_LOGIC(
- .reset(io_in[15]|~wb_rst_i),
- .in_select(io_in[16]),
- .gpio_clk(io_in[17]),
- .gpio_sram_clk(io_in[18]),
- .gpio_scan(io_in[19]),
- .gpio_sram_load(io_in[20]),
+ .reset(in_reset|~wb_rst_i),
+ .in_select(in_select),
+ .gpio_clk(gpio_clk),
+ .gpio_scan(gpio_scan),
+ .gpio_sram_load(gpio_sram_load),
.la_clk(la_data_in[127]),
- .la_sram_clk(la_data_in[126]),
.la_in_load(la_data_in[125]),
.la_sram_load(la_data_in[124]),
.la_data_in(la_data_in[111:0]),
.la_data_out(la_data_out[111:0]),
- .gpio_out(io_out[21]),
+ .gpio_out(gpio_out),
// Shared control/data to the SRAMs
- .left_addr0(addr0),
- .left_din0(din0),
- .left_web0(web0),
- .left_wmask0(wmask0),
- .left_addr1(addr1),
- .left_web1(web1),
- .left_wmask1(wmask1),
+ .left_addr0(left_addr0),
+ .left_din0(left_din0),
+ .left_web0(left_web0),
+ .left_wmask0(left_wmask0),
+ .left_addr1(left_addr1),
+ .left_web1(left_web1),
+ .left_wmask1(left_wmask1),
// One CSB for each SRAM
- .left_csb0(csb0),
- .left_csb1(csb1),
+ .left_csb0(left_csb0),
+ .left_csb1(left_csb1),
// Shared control/data to the SRAMs
- .right_addr0(addr0),
- .right_din0(din0),
- .right_web0(web0),
- .right_wmask0(wmask0),
+ .right_addr0(right_addr0),
+ .right_din0(right_din0),
+ .right_web0(right_web0),
+ .right_wmask0(right_wmask0),
// One CSB for each SRAM
- .right_csb0(csb0),
+ .right_csb0(right_csb0),
- // Clocks for each SRAM
- .sram0_clk(sram0_clk),
- .sram1_clk(sram1_clk),
- .sram2_clk(sram2_clk),
- .sram3_clk(sram3_clk),
- .sram4_clk(sram4_clk),
- .sram5_clk(sram5_clk),
- .sram6_clk(sram6_clk),
- .sram7_clk(sram7_clk),
- .sram8_clk(sram8_clk),
- .sram9_clk(sram9_clk),
- .sram10_clk(sram10_clk),
- .sram11_clk(sram11_clk),
- .sram12_clk(sram12_clk),
- .sram13_clk(sram13_clk),
- .sram14_clk(sram14_clk),
- .sram15_clk(sram15_clk),
-
// SRAM data outputs to be captured
- .sram0_dout0(sram0_dout0),
- .sram0_dout1(sram0_dout1),
- .sram1_dout0(sram1_dout0),
- .sram1_dout1(sram1_dout1),
- .sram2_dout0(sram2_dout0),
- .sram2_dout1(sram2_dout1),
- .sram3_dout0(sram3_dout0),
- .sram3_dout1(sram3_dout1),
- .sram4_dout0(sram4_dout0),
- .sram4_dout1(sram4_dout1),
- .sram5_dout0(sram5_dout0),
- .sram5_dout1(sram5_dout1),
- .sram6_dout0(sram6_dout0),
- .sram6_dout1(sram6_dout1),
- .sram7_dout0(sram7_dout0),
- .sram7_dout1(sram7_dout1),
- .sram8_dout0(sram8_dout0),
- .sram8_dout1(sram8_dout1),
- .sram9_dout0(sram9_dout0),
- .sram9_dout1(sram9_dout1),
- .sram10_dout0(sram10_dout0),
- .sram10_dout1(sram10_dout1),
- .sram11_dout0(sram11_dout0),
- .sram11_dout1(sram11_dout1),
- .sram12_dout0(sram12_dout0),
- .sram12_dout1(sram12_dout1),
- .sram13_dout0(sram13_dout0),
- .sram13_dout1(sram13_dout1),
- .sram14_dout0(sram14_dout0),
- .sram14_dout1(sram14_dout1),
- .sram15_dout0(sram15_dout0),
- .sram15_dout1(sram15_dout1),
-
+ .sram0_data0(sram0_data0),
+ .sram0_data1(sram0_data1),
+ .sram1_data0(sram1_data0),
+ .sram1_data1(sram1_data1),
+ .sram2_data0(sram2_data0),
+ .sram2_data1(sram2_data1),
+ .sram3_data0(sram3_data0),
+ .sram3_data1(sram3_data1),
+ .sram4_data0(sram4_data0),
+ .sram4_data1(sram4_data1),
+ .sram5_data0(sram5_data0),
+ .sram5_data1(sram5_data1),
+ .sram6_data0(sram6_data0),
+ .sram6_data1(sram6_data1),
+ .sram7_data0(sram7_data0),
+ .sram7_data1(sram7_data1),
+ .sram8_data0(sram8_data0),
+ .sram8_data1(sram8_data1),
+ .sram9_data0(sram9_data0),
+ .sram9_data1(sram9_data1),
+ .sram10_data0(sram10_data0),
+ .sram10_data1(sram10_data1),
+ .sram11_data0(sram11_data0),
+ .sram11_data1(sram11_data1),
+ .sram12_data0(sram12_data0),
+ .sram12_data1(sram12_data1),
+ .sram13_data0(sram13_data0),
+ .sram13_data1(sram13_data1),
+ .sram14_data0(sram14_data0),
+ .sram14_data1(sram14_data1),
+ .sram15_data0(sram15_data0),
+ .sram15_data1(sram15_data1)
);
@@ -268,23 +269,20 @@
wire [`DATA_SIZE-1:0] sram15_dout0;
wire [`DATA_SIZE-1:0] sram15_dout1;
- // Only io_out[27] is output
- assign io_oeb = 1'b1 << 21;
-
sky130_sram_1kbyte_1rw1r_8x1024_8 SRAM0
(
`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
- .clk0 (sram0_clk),
+ .clk0 (sram_clk),
.csb0 (left_csb0[0]),
.web0 (left_web0),
.wmask0 (left_wmask0),
.addr0 (left_addr0),
.din0 (left_din0),
.dout0 (sram0_dout0[7:0]),
- .clk1 (sram0_clk),
+ .clk1 (sram_clk),
.csb1 (left_csb1[0]),
.addr1 (left_addr0),
.dout1 (sram0_dout1[7:0])
@@ -298,14 +296,14 @@
.vccd1(vccd1),
.vssd1(vssd1),
`endif
- .clk0 (sram1_clk),
+ .clk0 (sram_clk),
.csb0 (left_csb0[1]),
.web0 (left_web0),
.wmask0 (left_wmask0),
.addr0 (left_addr0),
.din0 (left_din0),
.dout0 (sram1_dout0),
- .clk1 (sram1_clk),
+ .clk1 (sram_clk),
.csb1 (left_csb1[1]),
.addr1 (left_addr1),
.dout1 (sram1_dout1)
@@ -317,14 +315,14 @@
.vccd1(vccd1),
.vssd1(vssd1),
`endif
- .clk0 (sram2_clk),
+ .clk0 (sram_clk),
.csb0 (left_csb0[2]),
.web0 (left_web0),
.wmask0 (left_wmask0),
.addr0 (left_addr0),
.din0 (left_din0),
.dout0 (sram2_dout0),
- .clk1 (sram2_clk),
+ .clk1 (sram_clk),
.csb1 (left_csb1[2]),
.addr1 (left_addr1),
.dout1 (sram2_dout1)
@@ -336,14 +334,14 @@
.vccd1(vccd1),
.vssd1(vssd1),
`endif
- .clk0 (sram3_clk),
+ .clk0 (sram_clk),
.csb0 (left_csb0[3]),
.web0 (left_web0),
.wmask0 (left_wmask0),
.addr0 (left_addr0),
.din0 (left_din0),
.dout0 (sram3_dout0),
- .clk1 (sram3_clk),
+ .clk1 (sram_clk),
.csb1 (left_csb1[3]),
.addr1 (left_addr1),
.dout1 (sram3_dout1)
@@ -355,14 +353,14 @@
.vccd1(vccd1),
.vssd1(vssd1),
`endif
- .clk0 (sram4_clk),
+ .clk0 (sram_clk),
.csb0 (left_csb0[4]),
.web0 (left_web0),
.wmask0 (left_wmask0),
.addr0 (left_addr0),
.din0 (left_din0),
.dout0 (sram4_dout0),
- .clk1 (sram4_clk),
+ .clk1 (sram_clk),
.csb1 (left_csb1[4]),
.addr1 (left_addr1),
.dout1 (sram4_dout1)
@@ -375,14 +373,14 @@
// .vccd1(vccd1),
// .vssd1(vssd1),
// `endif
-// .clk0 (sram6_clk),
+// .clk0 (sram_clk),
// .csb0 (csb0[6]),
// .web0 (web0),
// .wmask0 (wmask0),
// .addr0 (addr0),
// .din0 (din0),
// .dout0 (sram6_dout0),
-// .clk1 (sram6_clk),
+// .clk1 (sram_clk),
// .csb1 (csb1[6]),
// .addr1 (addr1),
// .dout1 (sram6_dout1)
@@ -397,7 +395,7 @@
.vccd1(vccd1),
.vssd1(vssd1),
`endif
- .clk0 (sram8_clk),
+ .clk0 (sram_clk),
.csb0 (right_csb0[8]),
.web0 (right_web0),
.wmask0 (right_wmask0),
@@ -413,7 +411,7 @@
.vccd1(vccd1),
.vssd1(vssd1),
`endif
- .clk0 (sram9_clk),
+ .clk0 (sram_clk),
.csb0 (right_csb0[9]),
.web0 (right_web0),
.wmask0 (right_wmask0),
@@ -429,7 +427,7 @@
.vccd1(vccd1),
.vssd1(vssd1),
`endif
- .clk0 (sram10_clk),
+ .clk0 (sram_clk),
.csb0 (right_csb0[10]),
.web0 (right_web0),
.wmask0 (right_wmask0),
@@ -439,13 +437,14 @@
);
assign sram10_dout1 = 0;
+ wire [63:0] temp_sram11_dout0;
sram_1rw0r0w_64_512_sky130 SRAM11
(
`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
- .clk0 (sram11_clk),
+ .clk0 (sram_clk),
.csb0 (right_csb0[11]),
.web0 (right_web0),
.wmask0 (right_wmask0),
@@ -453,11 +452,132 @@
.din0 ({right_din0[31:16], 32'd0, right_din0[15:0]}),
.dout0 (temp_sram11_dout0)
);
-
- wire [63:0] temp_sram11_dout0;
assign sram11_dout1 = 0;
assign sram11_dout0 = {temp_sram11_dout0[64:33], temp_sram11_dout[15:0]};
+
+
+
+// Hold dout from SRAM
+// clocked by SRAM clk
+ reg [`DATA_SIZE-1:0] sram0_data0;
+ reg [`DATA_SIZE-1:0] sram0_data1;
+ reg [`DATA_SIZE-1:0] sram1_data0;
+ reg [`DATA_SIZE-1:0] sram1_data1;
+ reg [`DATA_SIZE-1:0] sram2_data0;
+ reg [`DATA_SIZE-1:0] sram2_data1;
+ reg [`DATA_SIZE-1:0] sram3_data0;
+ reg [`DATA_SIZE-1:0] sram3_data1;
+ reg [`DATA_SIZE-1:0] sram4_data0;
+ reg [`DATA_SIZE-1:0] sram4_data1;
+ reg [`DATA_SIZE-1:0] sram5_data0;
+ reg [`DATA_SIZE-1:0] sram5_data1;
+ reg [`DATA_SIZE-1:0] sram6_data0;
+ reg [`DATA_SIZE-1:0] sram6_data1;
+ reg [`DATA_SIZE-1:0] sram7_data0;
+ reg [`DATA_SIZE-1:0] sram7_data1;
+ reg [`DATA_SIZE-1:0] sram8_data0;
+ reg [`DATA_SIZE-1:0] sram8_data1;
+ reg [`DATA_SIZE-1:0] sram9_data0;
+ reg [`DATA_SIZE-1:0] sram9_data1;
+ reg [`DATA_SIZE-1:0] sram10_data0;
+ reg [`DATA_SIZE-1:0] sram10_data1;
+ reg [`DATA_SIZE-1:0] sram11_data0;
+ reg [`DATA_SIZE-1:0] sram11_data1;
+ reg [`DATA_SIZE-1:0] sram12_data0;
+ reg [`DATA_SIZE-1:0] sram12_data1;
+ reg [`DATA_SIZE-1:0] sram13_data0;
+ reg [`DATA_SIZE-1:0] sram13_data1;
+ reg [`DATA_SIZE-1:0] sram14_data0;
+ reg [`DATA_SIZE-1:0] sram14_data1;
+ reg [`DATA_SIZE-1:0] sram15_data0;
+ reg [`DATA_SIZE-1:0] sram15_data1;
+
+always @(posedge sram_clk) begin
+ if (in_reset) begin
+ sram0_data0 <= 0;
+ sram0_data1 <= 0;
+ sram1_data0 <= 0;
+ sram1_data1 <= 0;
+ sram2_data0 <= 0;
+ sram2_data1 <= 0;
+ sram3_data0 <= 0;
+ sram3_data1 <= 0;
+ sram4_data0 <= 0;
+ sram4_data1 <= 0;
+ // sram5_data0 <= 0;
+ // sram5_data1 <= 0;
+ // sram6_data0 <= 0;
+ // sram6_data1 <= 0;
+ // sram7_data0 <= 0;
+ // sram7_data1 <= 0;
+ sram8_data0 <= 0;
+ sram8_data1 <= 0;
+ sram9_data0 <= 0;
+ sram9_data1 <= 0;
+ sram10_data0 <= 0;
+ sram10_data1 <= 0;
+ sram11_data0 <= 0;
+ sram11_data1 <= 0;
+ sram12_data0 <= 0;
+ sram12_data1 <= 0;
+ sram13_data0 <= 0;
+ sram13_data1 <= 0;
+ sram14_data0 <= 0;
+ sram14_data1 <= 0;
+ sram15_data0 <= 0;
+ sram15_data1 <= 0;
+ end
+ else begin
+ sram0_data0 <= sram0_dout0;
+ sram0_data1 <= sram0_dout1;
+ sram1_data0 <= sram1_dout0;
+ sram1_data1 <= sram1_dout1;
+ sram2_data0 <= sram2_dout0;
+ sram2_data1 <= sram2_dout1;
+ sram3_data0 <= sram3_dout0;
+ sram3_data1 <= sram3_dout1;
+ sram4_data0 <= sram4_dout0;
+ sram4_data1 <= sram4_dout1;
+ // sram5_data0 <= sram5_dout0;
+ // sram5_data1 <= sram5_dout1;
+ // sram6_data0 <= sram6_dout0;
+ // sram6_data1 <= sram6_dout1;
+ // sram7_data0 <= sram7_dout0;
+ // sram7_data1 <= sram7_dout1;
+ sram8_data0 <= sram8_dout0;
+ sram8_data1 <= sram8_dout1;
+ sram9_data0 <= sram9_dout0;
+ sram9_data1 <= sram9_dout1;
+ sram10_data0 <= sram10_dout0;
+ sram10_data1 <= sram10_dout1;
+ sram11_data0 <= sram11_dout0;
+ sram11_data1 <= sram11_dout1;
+ // sram12_data0 <= sram12_dout0;
+ // sram12_data1 <= sram12_dout1;
+ // sram13_data0 <= sram13_dout0;
+ // sram13_data1 <= sram13_dout1;
+ // sram14_data0 <= sram14_dout0;
+ // sram14_data1 <= sram14_dout1;
+ // sram15_data0 <= sram15_dout0;
+ // sram15_data1 <= sram15_dout1;
+ end // else: !if(in_reset)
+end
+
+ assign sram5_data0 = 0;
+ assign sram5_data1 = 0;
+ assign sram6_data0 = 0;
+ assign sram6_data1 = 0;
+ assign sram7_data0 = 0;
+ assign sram7_data1 = 0;
+ assign sram12_data0 = 0;
+ assign sram12_data1 = 0;
+ assign sram13_data0 = 0;
+ assign sram13_data1 = 0;
+ assign sram14_data0 = 0;
+ assign sram14_data1 = 0;
+ assign sram15_data0 = 0;
+ assign sram15_data1 = 0;
endmodule // user_project_wrapper
