Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main
diff --git a/openlane/openram_testchip/config.tcl b/openlane/openram_testchip/config.tcl deleted file mode 100644 index 4533576..0000000 --- a/openlane/openram_testchip/config.tcl +++ /dev/null
@@ -1,40 +0,0 @@ -set script_dir [file dirname [file normalize [info script]]] - -set ::env(DESIGN_NAME) openram_testchip - -set ::env(DESIGN_IS_CORE) 0 -set ::env(FP_PDN_CORE_RING) 0 -set ::env(GLB_RT_MAXLAYER) 5 - -set ::env(VERILOG_FILES) "$script_dir/../../verilog/rtl/openram_defines.v \ - $script_dir/../../verilog/rtl/clock_mux.v \ - $script_dir/../../verilog/rtl/openram_testchip.v" -set ::env(BASE_SDC_FILE) "$script_dir/openram_testchip.sdc" - -set ::env(CLOCK_PORT) "clkmux.clk" -set ::env(CLOCK_NET) "clkmux.clk" -set ::env(RESET_PORT) "resetn" - -#set ::env(CLOCK_NET) "" -set ::env(CLOCK_PERIOD) "20" -set ::env(IO_PCT) 0.1 - -set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 400 2200" -set ::env(DESIGN_IS_CORE) 0 - -set ::env(VDD_NETS) [list {vccd1}] -set ::env(GND_NETS) [list {vssd1}] - -set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg - -#set ::env(SYNTH_NO_FLAT) 1 -set ::env(GLB_RT_ADJUSTMENT) 0.20 -set ::env(RUN_KLAYOUT_DRC) 0 -set ::env(PL_TARGET_DENSITY) 0.25 - -# This doesn't check for supply connectivity: -set ::env(FP_PDN_CHECK_NODES) 0 - -# If you're going to use multiple power domains, then keep this disabled. -set ::env(RUN_CVC) 0
diff --git a/openlane/openram_testchip/openram_testchip.sdc b/openlane/openram_testchip/openram_testchip.sdc deleted file mode 100644 index c96b83b..0000000 --- a/openlane/openram_testchip/openram_testchip.sdc +++ /dev/null
@@ -1,25 +0,0 @@ -create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD) -set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)] -set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)] -puts "\[INFO\]: Setting output delay to: $output_delay_value" -puts "\[INFO\]: Setting input delay to: $input_delay_value" - -set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design] - -set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]] -set rst_indx [lsearch [all_inputs] [get_port $::env(RESET_PORT)]] -set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx] -set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx] -#set all_inputs_wo_clk_rst $all_inputs_wo_clk - - -# correct resetn -set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst -set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] [get_port $::env(RESET_PORT)] -set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs] - -# TODO set this as parameter -set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] -set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] -puts "\[INFO\]: Setting load to: $cap_load" -set_load $cap_load [all_outputs]
diff --git a/openlane/openram_testchip/pin_order.cfg b/openlane/openram_testchip/pin_order.cfg deleted file mode 100644 index 9402f88..0000000 --- a/openlane/openram_testchip/pin_order.cfg +++ /dev/null
@@ -1,30 +0,0 @@ -#BUS_SORT -#NR -in_select -gpio.* - -#S -reset.* -la_.* - -#E -sram0_data[0-1] -sram1_data[0-1] -sram2_data[0-1] -sram3_data[0-1] -right_data[0-1] -sram4_data[0-1] -sram5_data[0-1] -sram6_data[0-1] -sram7_data[0-1] - -#WR -sram8_data[0-1] -sram9_data[0-1] -sram10_data[0-1] -sram11_data[0-1] -left_data[0-1] -sram12_data[0-1] -sram13_data[0-1] -sram14_data[0-1] -sram15_data[0-1] \ No newline at end of file
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index e326646..4e78d51 100755 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -75,7 +75,7 @@ $script_dir/../../gds/sky130_sram_4kbyte_1rw1r_32x1024_8.gds \ $script_dir/../../gds/sky130_sram_8kbyte_1rw1r_32x2048_8.gds \ $script_dir/../../gds/sram_1rw0r0w_32_1024_sky130.gds \ -p $script_dir/../../gds/sram_1rw0r0w_32_256_sky130.gds \ + $script_dir/../../gds/sram_1rw0r0w_32_256_sky130.gds \ $script_dir/../../gds/sram_1rw0r0w_32_512_sky130.gds \ $script_dir/../../gds/sram_1rw0r0w_64_512_sky130.gds" # $script_dir/../../gds/openram_testchip.gds