Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
8bde8f85b6c4b247c9657a1599751366bef362f3
commit
8bde8f85b6c4b247c9657a1599751366bef362f3
[
log
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author
mrg <mrg@ucsc.edu>
Thu Jun 17 11:52:32 2021 -0700
committer
mrg <mrg@ucsc.edu>
Thu Jun 17 11:52:32 2021 -0700
tree
e9e2049531ddc7dc3d3faf0b0978c0dc999a0d08
parent
2603fb948e7c06fa91e16ef6d93c7435fbf65546
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Remove extra character
openlane/openram_testchip/config.tcl
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openlane/openram_testchip/openram_testchip.sdc
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openlane/openram_testchip/pin_order.cfg
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openlane/user_project_wrapper/config.tcl
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4 files changed
tree: e9e2049531ddc7dc3d3faf0b0978c0dc999a0d08
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
single_port/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
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