Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 9885f23..2d92416 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -105,7 +105,7 @@
// Only io_out[21] is output
assign io_oeb = ~(1'b1 << 21);
// Assign other outputs to 0
- assign io_out[`MPRJ_IO_PADS:22] = 0;
+ assign io_out[`MPRJ_IO_PADS-1:22] = 0;
wire gpio_out;
assign io_out[21] = gpio_out;
assign io_out[20:0] = 0;