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foss-eda-tools/third_party/shuttle/sky130/mpw-002/slot-009/eb10e3571d76cde587057a40e1b4971db248f668
commit
eb10e3571d76cde587057a40e1b4971db248f668
[log] [tgz]
author
AmoghLonkar <alonkar@ucsc.edu>
Fri Jun 11 14:10:43 2021 -0700
committer
AmoghLonkar <alonkar@ucsc.edu>
Fri Jun 11 14:10:43 2021 -0700
tree
b3fe1520ee7161f78fc3132e2c50e7a5d95b8ecc
parent
8269657964df354c83fef908b973d0347b8e70dc [diff]
parent
617c9f5f4bd3124e3faf465414475f83da615306 [diff]
Merge branch 'control_verilog' of https://github.com/AmoghLonkar/openram_testchip into control_verilog
tree: b3fe1520ee7161f78fc3132e2c50e7a5d95b8ecc
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. single_port/
  11. spi/
  12. verilog/
  13. caravel
  14. .gitignore
  15. .gitmodules
  16. info.yaml
  17. LICENSE
  18. Makefile
  19. README.md
README.md

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