commit: 617c9f5f4bd3124e3faf465414475f83da615306
[log]
author: Amogh Lonkar <35778429+AmoghLonkar@users.noreply.github.com>
Fri Jun 11 14:05:47 2021 -0700
committer: GitHub <noreply@github.com>
Fri Jun 11 14:05:47 2021 -0700
tree: aa0036d7c5db0a9c6f72a855a3391f944801986a
parent: 1b30acd1bf2ecbd308bc4284dc85a9478dca2737 [diff]

Delete chisel directory

chisel/control_logic-main.zip:Zone.Identifier[Deleted - diff]
chisel/control_logic-main/control_logic-main/.github/workflows/test.yml[Deleted - diff]
chisel/control_logic-main/control_logic-main/.gitignore[Deleted - diff]
chisel/control_logic-main/control_logic-main/README.md[Deleted - diff]
chisel/control_logic-main/control_logic-main/build.sbt[Deleted - diff]
chisel/control_logic-main/control_logic-main/openram_testchip.v[Deleted - diff]
chisel/control_logic-main/control_logic-main/project/build.properties[Deleted - diff]
chisel/control_logic-main/control_logic-main/project/plugins.sbt[Deleted - diff]
chisel/control_logic-main/control_logic-main/src/main/scala/control_logic/openram_testchip.scala[Deleted - diff]
chisel/control_logic-main/control_logic-main/src/test/scala/control_logic/openramTestSuite.scala[Deleted - diff]

10 files changed

tree: aa0036d7c5db0a9c6f72a855a3391f944801986a

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.