commit: e8af1ae7e97c8effb684c65c0781df3bd711c283
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Tue Jun 15 08:54:56 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Tue Jun 15 08:54:56 2021 -0700
tree: 6c11218571133a86fe109c03734527e482b81017
parent: 2b607c0d6c7e28be9c657283276f90cff10acaf7 [diff]

Proper bits and variable name for temp_sram11_dout0

verilog/rtl/user_project_wrapper.v[diff]

1 file changed

tree: 6c11218571133a86fe109c03734527e482b81017

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.