)]}'
{
  "commit": "e8af1ae7e97c8effb684c65c0781df3bd711c283",
  "tree": "6c11218571133a86fe109c03734527e482b81017",
  "parents": [
    "2b607c0d6c7e28be9c657283276f90cff10acaf7"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Tue Jun 15 08:54:56 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Tue Jun 15 08:54:56 2021 -0700"
  },
  "message": "Proper bits and variable name for temp_sram11_dout0\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4d91ad8e191154ac9f11ba00b062dfe45a178684",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "ec805909fa90de117b5c2ffc7f0f43bd913a6dc8",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}