commit e0af8715d8a01d510fcfcaaf1b2ca32fb62a9def
author mrg <mrg@ucsc.edu> Fri Jun 25 12:08:15 2021 -0700
committer mrg <mrg@ucsc.edu> Fri Jun 25 12:08:15 2021 -0700
tree 5bf780bafa7131f59a5d9083c7e4bedf28037998
parent 1574e7b0ca53b23f02874ce4f4af7e16000288d9

Deassert gpio_sram_load

verilog/dv/gpio_test/gpio_test_tb.v

diff --git a/verilog/dv/gpio_test/gpio_test_tb.v b/verilog/dv/gpio_test/gpio_test_tb.v
index 625c9e4..af74209 100644
--- a/verilog/dv/gpio_test/gpio_test_tb.v
+++ b/verilog/dv/gpio_test/gpio_test_tb.v
@@ -135,6 +135,8 @@
 	 gpio_sram_load = 1;
 	 #25;
 
+	 gpio_sram_load = 1;
+
 	 // This should scan out the results and check they match the same thing expected here:
 	 in_data = {sel, addr0, din0, csb0, web0, 4'hF, addr1, din1, csb1, web1, 4'hF};
 	 gpio_scan = 1;