Test now starts and terminates
diff --git a/verilog/dv/la_test/la_test.c b/verilog/dv/la_test/la_test.c
index 00ade15..6a95619 100644
--- a/verilog/dv/la_test/la_test.c
+++ b/verilog/dv/la_test/la_test.c
@@ -88,6 +88,7 @@
// This is to signal when the code is ready to the test bench
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
// To start, set pin 0 to 1
reg_mprj_datal = 0x00000001;
@@ -111,7 +112,7 @@
reg_la1_data = 0x00000000;
reg_la2_data = 0x00000000;
reg_la3_data = 0x00000000;
-
+
union packet p;
p.bf.rst = 0;
// Only send the MSByte
@@ -146,7 +147,7 @@
reg_la3_data = p.wf.word3;
// On end, set pin 0 to 0
- reg_mprj_datal = 0x00000000;
+ reg_mprj_datal = 0x00000003;
/* Apply configuration */
reg_mprj_xfer = 1;
diff --git a/verilog/dv/la_test/la_test_tb.v b/verilog/dv/la_test/la_test_tb.v
index 97b1f10..81a4591 100644
--- a/verilog/dv/la_test/la_test_tb.v
+++ b/verilog/dv/la_test/la_test_tb.v
@@ -31,6 +31,7 @@
wire gpio;
wire [37:0] mprj_io;
wire mprj_io_0 = mprj_io[0];
+ wire mprj_io_1 = mprj_io[1];
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
@@ -65,12 +66,13 @@
$dumpfile("la_test.vcd");
$dumpvars(0, la_test_tb);
- wait(mprj_io_0 == 1'b0);
- $display($time, " Saw bit 0: VCD stopping");
+ wait(mprj_io_1 == 1'b1);
+ $display($time, " Saw bit 1: VCD stopping");
+
$finish;
end // initial begin
-
+
initial begin
$dumpfile("foo.vcd");
$dumpvars(0, la_test_tb);
