commit | d94563295b5bee3205666af49c2ad52dfee04576 | [log] [tgz] |
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author | AmoghLonkar <alonkar@ucsc.edu> | Sat Jun 26 07:24:04 2021 -0700 |
committer | AmoghLonkar <alonkar@ucsc.edu> | Sat Jun 26 07:24:04 2021 -0700 |
tree | 6cc5023df49eb8933592ad0d95ead35544c85cfb | |
parent | ee86546c79d3ee0d15e430ee399c064e61ae9462 [diff] |
Test now starts and terminates
:exclamation: Important Note |
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This project contains a test chip for several OpenRAM memory configurations. The configurations have varying levels of verification. In particular, it has these sizes:
There are two test modes available. Each one inputs an packet that configures the read and write operations of a particular SRAM. The GPIO pin io_in[16] determines whether to use GPIO (1) or LA mode (0).
The test packet is a 112-bit value that has the follow signals and bit size:
During a read operation, the din bits are replaced with the data output bits so that they can be verified.
Note: The 64-bit memory leaves the middle 32-bits as a value of 0 and instead reads/writes the upper and lower 16-bits to reduce the number of packet bits.
In GPIO mode, the test packet is scanned in/out with the GPIO pins in 112 cycles. The GPIO pins used are as follows:
In LA mode, the test packet is directly written from the output of the 128-bit LA. The top bits of the LA register are used for the control signals during test: