Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 2b7b886..e326646 100755 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -27,14 +27,15 @@ ## Source Verilog Files set ::env(VERILOG_FILES) "\ $script_dir/../../caravel/verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/clock_mux.v \ + $script_dir/../../verilog/rtl/openram_testchip.v \ $script_dir/../../verilog/rtl/user_project_wrapper.v " ## Clock configurations -set ::env(CLOCK_PORT) "clkmux.clk" -set ::env(CLOCK_NET) "clkmux.clk" +set ::env(CLOCK_PORT) {io_in\[17\]} +set ::env(CLOCK_NET) "CONTROL_LOGIC.clk" +set ::env(RESET_PORT) {io_in\[15\] wb_rst_i} -set ::env(CLOCK_PERIOD) "20" +set ::env(CLOCK_PERIOD) "30" set ::env(BASE_SDC_FILE) "$script_dir/user_project_wrapper.sdc" ## Internal Macros @@ -52,8 +53,8 @@ $script_dir/../../verilog/rtl/sram_1rw0r0w_32_1024_sky130.v \ $script_dir/../../verilog/rtl/sram_1rw0r0w_32_256_sky130.v \ $script_dir/../../verilog/rtl/sram_1rw0r0w_32_512_sky130.v \ - $script_dir/../../verilog/rtl/sram_1rw0r0w_64_512_sky130.v \ - $script_dir/../../verilog/rtl/openram_testchip.v " + $script_dir/../../verilog/rtl/sram_1rw0r0w_64_512_sky130.v" +#$script_dir/../../verilog/rtl/openram_testchip.v set ::env(EXTRA_LEFS) "\ $script_dir/../../lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef \ @@ -64,8 +65,8 @@ $script_dir/../../lef/sram_1rw0r0w_32_1024_sky130.lef \ $script_dir/../../lef/sram_1rw0r0w_32_256_sky130.lef \ $script_dir/../../lef/sram_1rw0r0w_32_512_sky130.lef \ - $script_dir/../../lef/sram_1rw0r0w_64_512_sky130.lef \ - $script_dir/../../lef/openram_testchip.lef " + $script_dir/../../lef/sram_1rw0r0w_64_512_sky130.lef" +# $script_dir/../../lef/openram_testchip.lef set ::env(EXTRA_GDS_FILES) "\ $script_dir/../../gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds \ @@ -74,10 +75,10 @@ $script_dir/../../gds/sky130_sram_4kbyte_1rw1r_32x1024_8.gds \ $script_dir/../../gds/sky130_sram_8kbyte_1rw1r_32x2048_8.gds \ $script_dir/../../gds/sram_1rw0r0w_32_1024_sky130.gds \ - $script_dir/../../gds/sram_1rw0r0w_32_256_sky130.gds \ +p $script_dir/../../gds/sram_1rw0r0w_32_256_sky130.gds \ $script_dir/../../gds/sram_1rw0r0w_32_512_sky130.gds \ - $script_dir/../../gds/sram_1rw0r0w_64_512_sky130.gds \ - $script_dir/../../gds/openram_testchip.gds " + $script_dir/../../gds/sram_1rw0r0w_64_512_sky130.gds" +# $script_dir/../../gds/openram_testchip.gds set ::env(GLB_RT_MAXLAYER) 5 @@ -89,10 +90,10 @@ # Placement config set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0 set ::env(PL_DIAMOND_SEARCH_HEIGHT) 500 -set ::env(PL_RANDOM_GLB_PLACEMENT) 1 +#set ::env(PL_RANDOM_GLB_PLACEMENT) 1 set ::env(GLB_RT_ADJUSTMENT) 0.25 -set ::env(PL_TARGET_DENSITY) 0.5 +set ::env(PL_TARGET_DENSITY) 0.3 #set ::env(MAGIC_DRC_USE_GDS) 0
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index ed4bc40..132d9a7 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -26,8 +26,8 @@ # 1094 x 721 SRAM4 200 2600 N -# sky130_sram_16kbyte_1rw1w_32x4096_8 -#SRAM6 +# sky130_sram_16kbyte_1rw1w_32x4096_8 +#SRAM6 # Control is 800 wide with 100 margin # so 2000 @@ -48,4 +48,4 @@ # 823 x 335 SRAM8 2000 2600 N -CONTROL_LOGIC 1300 100 N +#CONTROL_LOGIC 1300 100 N
diff --git a/verilog/rtl/clock_mux.v b/verilog/rtl/clock_mux.v deleted file mode 100644 index c1a92b1..0000000 --- a/verilog/rtl/clock_mux.v +++ /dev/null
@@ -1,11 +0,0 @@ -module clock_mux( - input clk0, - input clk1, - input sel, - output reg clk); - -always @(*) begin - clk = sel ? clk1 : clk0; -end - -endmodule // clock_mux
diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v index 0bff047..50a227b 100644 --- a/verilog/rtl/openram_testchip.v +++ b/verilog/rtl/openram_testchip.v
@@ -12,15 +12,11 @@ inout vssd2, // User area 2 digital ground `endif input resetn, - // Select either GPIO or LA mode - input in_select, - - input la_clk, + input clk, input la_in_load, input la_sram_load, input [`TOTAL_SIZE-1:0] la_data_in, // GPIO bit to clock control register - input gpio_clk, input gpio_in, input gpio_scan, input gpio_sram_load, @@ -105,16 +101,6 @@ wire [`WMASK_SIZE-1:0] right_wmask0 = left_wmask0; wire [`MAX_CHIPS-1:0] right_csb0 = left_csb0; - - - // Selecting clock pin - wire clk; - clock_mux clkmux(.clk0(la_clk), - .clk1(gpio_clk), - .sel(in_select), - .clk(clk)); - - always @ (posedge clk) begin if(!resetn) begin sram_register <= {`TOTAL_SIZE{1'b0}}; @@ -138,19 +124,20 @@ end end + // Splitting register bits into fields always @(*) begin chip_select = sram_register[`TOTAL_SIZE-1:`TOTAL_SIZE-`SELECT_SIZE]; left_addr0 = sram_register[`TOTAL_SIZE-`SELECT_SIZE-1:`TOTAL_SIZE-`SELECT_SIZE-`ADDR_SIZE]; left_din0 = sram_register[`DATA_SIZE+`PORT_SIZE+`WMASK_SIZE+1:`PORT_SIZE+`WMASK_SIZE+2]; - csb0_temp = sram_register[`PORT_SIZE+`WMASK_SIZE+1]; + csb0_temp = gpio_scan | la_in_load | sram_register[`PORT_SIZE+`WMASK_SIZE+1]; left_web0 = sram_register[`PORT_SIZE+`WMASK_SIZE]; left_wmask0 = sram_register[`PORT_SIZE+`WMASK_SIZE-1:`PORT_SIZE]; left_addr1 = sram_register[`PORT_SIZE-1:`DATA_SIZE+`WMASK_SIZE+2]; left_din1 = sram_register[`DATA_SIZE+`WMASK_SIZE+1:`WMASK_SIZE+2]; - csb1_temp = sram_register[`WMASK_SIZE+1]; + csb1_temp = gpio_scan | la_in_load | sram_register[`WMASK_SIZE+1]; left_web1 = sram_register[`WMASK_SIZE]; left_wmask1 = sram_register[`WMASK_SIZE-1:0]; end
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index b7b672d..9885f23 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -98,6 +98,9 @@ wire gpio_sram_clk = io_in[18]; wire gpio_scan = io_in[19]; wire gpio_sram_load = io_in[20]; + wire la_clk = la_data_in[127]; + wire la_in_load = la_data_in[125]; + wire la_sram_load = la_data_in[124]; // Only io_out[21] is output assign io_oeb = ~(1'b1 << 21); @@ -107,23 +110,19 @@ assign io_out[21] = gpio_out; assign io_out[20:0] = 0; - wire sram_clk; - clock_mux clkmux(.clk0(la_data_in[126]), - .clk1(gpio_sram_clk), - .sel(in_select), - .clk(sram_clk)); - + // Selecting clock pin + reg clk; + always @(*) begin + clk = in_select ? gpio_clk : la_clk; + end openram_testchip CONTROL_LOGIC( .resetn(resetn & wb_rst_i), - .in_select(in_select), - .gpio_clk(gpio_clk), + .clk(clk), .gpio_scan(gpio_scan), .gpio_sram_load(gpio_sram_load), - - .la_clk(la_data_in[127]), - .la_in_load(la_data_in[125]), - .la_sram_load(la_data_in[124]), + .la_in_load(la_in_load), + .la_sram_load(la_sram_load), .la_data_in(la_data_in[111:0]), .la_data_out(la_data_out[111:0]), .gpio_out(gpio_out), @@ -240,14 +239,14 @@ .vccd1(vccd1), .vssd1(vssd1), `endif - .clk0 (sram_clk), + .clk0 (clk), .csb0 (left_csb0[0]), .web0 (left_web0), .wmask0 (left_wmask0), .addr0 (left_addr0), .din0 (left_din0), .dout0 (sram0_dout0[7:0]), - .clk1 (sram_clk), + .clk1 (clk), .csb1 (left_csb1[0]), .addr1 (left_addr1), .dout1 (sram0_dout1[7:0]) @@ -261,14 +260,14 @@ .vccd1(vccd1), .vssd1(vssd1), `endif - .clk0 (sram_clk), + .clk0 (clk), .csb0 (left_csb0[1]), .web0 (left_web0), .wmask0 (left_wmask0), .addr0 (left_addr0), .din0 (left_din0), .dout0 (sram1_dout0), - .clk1 (sram_clk), + .clk1 (clk), .csb1 (left_csb1[1]), .addr1 (left_addr1), .dout1 (sram1_dout1) @@ -280,14 +279,14 @@ .vccd1(vccd1), .vssd1(vssd1), `endif - .clk0 (sram_clk), + .clk0 (clk), .csb0 (left_csb0[2]), .web0 (left_web0), .wmask0 (left_wmask0), .addr0 (left_addr0), .din0 (left_din0), .dout0 (sram2_dout0), - .clk1 (sram_clk), + .clk1 (clk), .csb1 (left_csb1[2]), .addr1 (left_addr1), .dout1 (sram2_dout1) @@ -299,14 +298,14 @@ .vccd1(vccd1), .vssd1(vssd1), `endif - .clk0 (sram_clk), + .clk0 (clk), .csb0 (left_csb0[3]), .web0 (left_web0), .wmask0 (left_wmask0), .addr0 (left_addr0), .din0 (left_din0), .dout0 (sram3_dout0), - .clk1 (sram_clk), + .clk1 (clk), .csb1 (left_csb1[3]), .addr1 (left_addr1), .dout1 (sram3_dout1) @@ -318,14 +317,14 @@ .vccd1(vccd1), .vssd1(vssd1), `endif - .clk0 (sram_clk), + .clk0 (clk), .csb0 (left_csb0[4]), .web0 (left_web0), .wmask0 (left_wmask0), .addr0 (left_addr0), .din0 (left_din0), .dout0 (sram4_dout0), - .clk1 (sram_clk), + .clk1 (clk), .csb1 (left_csb1[4]), .addr1 (left_addr1), .dout1 (sram4_dout1) @@ -338,14 +337,14 @@ // .vccd1(vccd1), // .vssd1(vssd1), // `endif -// .clk0 (sram_clk), +// .clk0 (clk), // .csb0 (csb0[6]), // .web0 (web0), // .wmask0 (wmask0), // .addr0 (addr0), // .din0 (din0), // .dout0 (sram6_dout0), -// .clk1 (sram_clk), +// .clk1 (clk), // .csb1 (csb1[6]), // .addr1 (addr1), // .dout1 (sram6_dout1) @@ -360,7 +359,7 @@ .vccd1(vccd1), .vssd1(vssd1), `endif - .clk0 (sram_clk), + .clk0 (clk), .csb0 (right_csb0[8]), .web0 (right_web0), .wmask0 (right_wmask0), @@ -376,7 +375,7 @@ .vccd1(vccd1), .vssd1(vssd1), `endif - .clk0 (sram_clk), + .clk0 (clk), .csb0 (right_csb0[9]), .web0 (right_web0), .wmask0 (right_wmask0), @@ -392,7 +391,7 @@ .vccd1(vccd1), .vssd1(vssd1), `endif - .clk0 (sram_clk), + .clk0 (clk), .csb0 (right_csb0[10]), .web0 (right_web0), .wmask0 (right_wmask0), @@ -409,7 +408,7 @@ .vccd1(vccd1), .vssd1(vssd1), `endif - .clk0 (sram_clk), + .clk0 (clk), .csb0 (right_csb0[11]), .web0 (right_web0), .wmask0 (right_wmask0), @@ -455,7 +454,7 @@ //reg [`DATA_SIZE-1:0] sram15_data0; //reg [`DATA_SIZE-1:0] sram15_data1; -always @(posedge sram_clk) begin +always @(posedge clk) begin if (!resetn) begin sram0_data0 <= 0; sram0_data1 <= 0; @@ -523,7 +522,7 @@ // sram14_data1 <= sram14_dout1; // sram15_data0 <= sram15_dout0; // sram15_data1 <= sram15_dout1; - end // else: !if(in_reset) + end end wire [`DATA_SIZE-1:0] sram5_data0 = 0;