| commit | d54b7b1f7339a70fdfadfe4408b0141cbc346917 | [log] [tgz] |
|---|---|---|
| author | mrg <mrg@ucsc.edu> | Thu Jun 17 11:23:27 2021 -0700 |
| committer | mrg <mrg@ucsc.edu> | Thu Jun 17 11:23:27 2021 -0700 |
| tree | a8690e1fabec18a6cab82c0bc17ca1bcf970a574 | |
| parent | 0d14b0b816d6a08ef1dbe0605053efdb6f0ab885 [diff] | |
| parent | 3ff7d0762ac4b96e46cf6fdad8509ef539a41cbf [diff] |
Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index d678690..25fa95d 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -34,4 +34,5 @@ `include "sram_1rw0r0w_32_512_sky130.v" `include "sram_1rw0r0w_32_1024_sky130.v" `include "sram_1rw0r0w_64_512_sky130.v" + `include "clock_mux.v" `endif \ No newline at end of file