Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main
diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
index e46077e..c3622d0 100644
--- a/verilog/rtl/openram_testchip.v
+++ b/verilog/rtl/openram_testchip.v
@@ -20,7 +20,7 @@
input gpio_in,
input gpio_scan,
input gpio_sram_load,
- input global_csr,
+ input global_csb,
// SRAM data outputs to be captured
input [`DATA_SIZE-1:0] sram0_data0,
input [`DATA_SIZE-1:0] sram0_data1,
@@ -116,13 +116,13 @@
addr0 = sram_register[`TOTAL_SIZE-`SELECT_SIZE-1:`TOTAL_SIZE-`SELECT_SIZE-`ADDR_SIZE];
din0 = sram_register[`DATA_SIZE+`PORT_SIZE+`WMASK_SIZE+1:`PORT_SIZE+`WMASK_SIZE+2];
- csb0_temp = global_csr | sram_register[`PORT_SIZE+`WMASK_SIZE+1];
+ csb0_temp = global_csb | sram_register[`PORT_SIZE+`WMASK_SIZE+1];
web0 = sram_register[`PORT_SIZE+`WMASK_SIZE];
wmask0 = sram_register[`PORT_SIZE+`WMASK_SIZE-1:`PORT_SIZE];
addr1 = sram_register[`PORT_SIZE-1:`DATA_SIZE+`WMASK_SIZE+2];
din1 = sram_register[`DATA_SIZE+`WMASK_SIZE+1:`WMASK_SIZE+2];
- csb1_temp = global_csr | sram_register[`WMASK_SIZE+1];
+ csb1_temp = global_csb | sram_register[`WMASK_SIZE+1];
web1 = sram_register[`WMASK_SIZE];
wmask1 = sram_register[`WMASK_SIZE-1:0];
end
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 7bfa7e0..90c187a 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -79,6 +79,7 @@
output [2:0] user_irq
);
+
// Shared control/data to the SRAMs
wire [`ADDR_SIZE-1:0] addr0;
wire [`DATA_SIZE-1:0] din0;
@@ -92,14 +93,14 @@
wire [`MAX_CHIPS-1:0] csb0;
wire [`MAX_CHIPS-1:0] csb1;
- wire in_select = io_in[15];
- wire resetn = io_in[14];
- wire gpio_clk = io_in[16];
- wire gpio_sram_clk = io_in[17];
- wire gpio_scan = io_in[18];
- wire gpio_sram_load = io_in[19];
- wire gpio_in = io_in[20];
- wire global_csr = io_in[21];
+ wire in_select = io_in[16];
+ wire resetn = io_in[15];
+ wire gpio_clk = io_in[17];
+ wire gpio_sram_clk = io_in[18];
+ wire gpio_scan = io_in[19];
+ wire gpio_sram_load = io_in[20];
+ wire global_csb = io_in[21];
+ wire gpio_in = io_in[22];
wire la_clk = la_data_in[127];
wire la_in_load = la_data_in[125];
wire la_sram_load = la_data_in[124];
@@ -120,27 +121,30 @@
openram_testchip CONTROL_LOGIC(
.resetn(resetn & wb_rst_i),
.clk(clk),
- .global_csr(global_csr),
+ .global_csb(global_csb),
.gpio_scan(gpio_scan),
.gpio_sram_load(gpio_sram_load),
- .gpio_in(gpio_in),
+ .gpio_in(gpio_in),
+ .gpio_out(gpio_out),
+
.la_in_load(la_in_load),
.la_sram_load(la_sram_load),
.la_data_in(la_data_in[111:0]),
.la_data_out(la_data_out[111:0]),
- .gpio_out(gpio_out),
// Shared control/data to the SRAMs
.addr0(addr0),
.din0(din0),
+ // One CSB for each SRAM
+ .csb0(csb0),
.web0(web0),
.wmask0(wmask0),
.addr1(addr1),
+ .din1(din1),
+ // One CSB for each SRAM
+ .csb1(csb1),
.web1(web1),
.wmask1(wmask1),
- // One CSB for each SRAM
- .csb0(csb0),
- .csb1(csb1),
// SRAM data outputs to be captured
.sram0_data0(sram0_data0),
@@ -392,113 +396,113 @@
.din0 ({din0[31:16], 32'd0, din0[15:0]}),
.dout0 (temp_sram11_dout0)
);
- assign sram11_dout0 = {temp_sram11_dout0[64:49], temp_sram11_dout0[15:0]};
+ assign sram11_dout0 = {temp_sram11_dout0[63:49], temp_sram11_dout0[15:0]};
-// Hold dout from SRAM
-// clocked by SRAM clk
-reg [`DATA_SIZE-1:0] sram0_data0;
-reg [`DATA_SIZE-1:0] sram0_data1;
-reg [`DATA_SIZE-1:0] sram1_data0;
-reg [`DATA_SIZE-1:0] sram1_data1;
-reg [`DATA_SIZE-1:0] sram2_data0;
-reg [`DATA_SIZE-1:0] sram2_data1;
-reg [`DATA_SIZE-1:0] sram3_data0;
-reg [`DATA_SIZE-1:0] sram3_data1;
-reg [`DATA_SIZE-1:0] sram4_data0;
-reg [`DATA_SIZE-1:0] sram4_data1;
-//reg [`DATA_SIZE-1:0] sram5_data0;
-//reg [`DATA_SIZE-1:0] sram5_data1;
-//reg [`DATA_SIZE-1:0] sram6_data0;
-//reg [`DATA_SIZE-1:0] sram6_data1;
-//reg [`DATA_SIZE-1:0] sram7_data0;
-//reg [`DATA_SIZE-1:0] sram7_data1;
-reg [`DATA_SIZE-1:0] sram8_data0;
-//reg [`DATA_SIZE-1:0] sram8_data1;
-reg [`DATA_SIZE-1:0] sram9_data0;
-//reg [`DATA_SIZE-1:0] sram9_data1;
-reg [`DATA_SIZE-1:0] sram10_data0;
-//reg [`DATA_SIZE-1:0] sram10_data1;
-reg [`DATA_SIZE-1:0] sram11_data0;
-//reg [`DATA_SIZE-1:0] sram11_data1;
-//reg [`DATA_SIZE-1:0] sram12_data0;
-//reg [`DATA_SIZE-1:0] sram12_data1;
-//reg [`DATA_SIZE-1:0] sram13_data0;
-//reg [`DATA_SIZE-1:0] sram13_data1;
-//reg [`DATA_SIZE-1:0] sram14_data0;
-//reg [`DATA_SIZE-1:0] sram14_data1;
-//reg [`DATA_SIZE-1:0] sram15_data0;
-//reg [`DATA_SIZE-1:0] sram15_data1;
+ // Hold dout from SRAM
+ // clocked by SRAM clk
+ reg [`DATA_SIZE-1:0] sram0_data0;
+ reg [`DATA_SIZE-1:0] sram0_data1;
+ reg [`DATA_SIZE-1:0] sram1_data0;
+ reg [`DATA_SIZE-1:0] sram1_data1;
+ reg [`DATA_SIZE-1:0] sram2_data0;
+ reg [`DATA_SIZE-1:0] sram2_data1;
+ reg [`DATA_SIZE-1:0] sram3_data0;
+ reg [`DATA_SIZE-1:0] sram3_data1;
+ reg [`DATA_SIZE-1:0] sram4_data0;
+ reg [`DATA_SIZE-1:0] sram4_data1;
+ //reg [`DATA_SIZE-1:0] sram5_data0;
+ //reg [`DATA_SIZE-1:0] sram5_data1;
+ //reg [`DATA_SIZE-1:0] sram6_data0;
+ //reg [`DATA_SIZE-1:0] sram6_data1;
+ //reg [`DATA_SIZE-1:0] sram7_data0;
+ //reg [`DATA_SIZE-1:0] sram7_data1;
+ reg [`DATA_SIZE-1:0] sram8_data0;
+ //reg [`DATA_SIZE-1:0] sram8_data1;
+ reg [`DATA_SIZE-1:0] sram9_data0;
+ //reg [`DATA_SIZE-1:0] sram9_data1;
+ reg [`DATA_SIZE-1:0] sram10_data0;
+ //reg [`DATA_SIZE-1:0] sram10_data1;
+ reg [`DATA_SIZE-1:0] sram11_data0;
+ //reg [`DATA_SIZE-1:0] sram11_data1;
+ //reg [`DATA_SIZE-1:0] sram12_data0;
+ //reg [`DATA_SIZE-1:0] sram12_data1;
+ //reg [`DATA_SIZE-1:0] sram13_data0;
+ //reg [`DATA_SIZE-1:0] sram13_data1;
+ //reg [`DATA_SIZE-1:0] sram14_data0;
+ //reg [`DATA_SIZE-1:0] sram14_data1;
+ //reg [`DATA_SIZE-1:0] sram15_data0;
+ //reg [`DATA_SIZE-1:0] sram15_data1;
-always @(posedge clk) begin
- if (!resetn) begin
- sram0_data0 <= 0;
- sram0_data1 <= 0;
- sram1_data0 <= 0;
- sram1_data1 <= 0;
- sram2_data0 <= 0;
- sram2_data1 <= 0;
- sram3_data0 <= 0;
- sram3_data1 <= 0;
- sram4_data0 <= 0;
- sram4_data1 <= 0;
- // sram5_data0 <= 0;
- // sram5_data1 <= 0;
- // sram6_data0 <= 0;
- // sram6_data1 <= 0;
- // sram7_data0 <= 0;
- // sram7_data1 <= 0;
- sram8_data0 <= 0;
- //sram8_data1 <= 0;
- sram9_data0 <= 0;
- //sram9_data1 <= 0;
- sram10_data0 <= 0;
- //sram10_data1 <= 0;
- sram11_data0 <= 0;
- //sram11_data1 <= 0;
- //sram12_data0 <= 0;
- //sram12_data1 <= 0;
- //sram13_data0 <= 0;
- //sram13_data1 <= 0;
- //sram14_data0 <= 0;
- //sram14_data1 <= 0;
- //sram15_data0 <= 0;
- //sram15_data1 <= 0;
+ always @(posedge clk) begin
+ if (!resetn) begin
+ sram0_data0 <= 0;
+ sram0_data1 <= 0;
+ sram1_data0 <= 0;
+ sram1_data1 <= 0;
+ sram2_data0 <= 0;
+ sram2_data1 <= 0;
+ sram3_data0 <= 0;
+ sram3_data1 <= 0;
+ sram4_data0 <= 0;
+ sram4_data1 <= 0;
+ // sram5_data0 <= 0;
+ // sram5_data1 <= 0;
+ // sram6_data0 <= 0;
+ // sram6_data1 <= 0;
+ // sram7_data0 <= 0;
+ // sram7_data1 <= 0;
+ sram8_data0 <= 0;
+ //sram8_data1 <= 0;
+ sram9_data0 <= 0;
+ //sram9_data1 <= 0;
+ sram10_data0 <= 0;
+ //sram10_data1 <= 0;
+ sram11_data0 <= 0;
+ //sram11_data1 <= 0;
+ //sram12_data0 <= 0;
+ //sram12_data1 <= 0;
+ //sram13_data0 <= 0;
+ //sram13_data1 <= 0;
+ //sram14_data0 <= 0;
+ //sram14_data1 <= 0;
+ //sram15_data0 <= 0;
+ //sram15_data1 <= 0;
+ end
+ else begin
+ sram0_data0 <= sram0_dout0;
+ sram0_data1 <= sram0_dout1;
+ sram1_data0 <= sram1_dout0;
+ sram1_data1 <= sram1_dout1;
+ sram2_data0 <= sram2_dout0;
+ sram2_data1 <= sram2_dout1;
+ sram3_data0 <= sram3_dout0;
+ sram3_data1 <= sram3_dout1;
+ sram4_data0 <= sram4_dout0;
+ sram4_data1 <= sram4_dout1;
+ // sram5_data0 <= sram5_dout0;
+ // sram5_data1 <= sram5_dout1;
+ // sram6_data0 <= sram6_dout0;
+ // sram6_data1 <= sram6_dout1;
+ // sram7_data0 <= sram7_dout0;
+ // sram7_data1 <= sram7_dout1;
+ sram8_data0 <= sram8_dout0;
+ // sram8_data1 <= sram8_dout1;
+ sram9_data0 <= sram9_dout0;
+ // sram9_data1 <= sram9_dout1;
+ sram10_data0 <= sram10_dout0;
+ // sram10_data1 <= sram10_dout1;
+ sram11_data0 <= sram11_dout0;
+ // sram11_data1 <= sram11_dout1;
+ // sram12_data0 <= sram12_dout0;
+ // sram12_data1 <= sram12_dout1;
+ // sram13_data0 <= sram13_dout0;
+ // sram13_data1 <= sram13_dout1;
+ // sram14_data0 <= sram14_dout0;
+ // sram14_data1 <= sram14_dout1;
+ // sram15_data0 <= sram15_dout0;
+ // sram15_data1 <= sram15_dout1;
+ end
end
- else begin
- sram0_data0 <= sram0_dout0;
- sram0_data1 <= sram0_dout1;
- sram1_data0 <= sram1_dout0;
- sram1_data1 <= sram1_dout1;
- sram2_data0 <= sram2_dout0;
- sram2_data1 <= sram2_dout1;
- sram3_data0 <= sram3_dout0;
- sram3_data1 <= sram3_dout1;
- sram4_data0 <= sram4_dout0;
- sram4_data1 <= sram4_dout1;
- // sram5_data0 <= sram5_dout0;
- // sram5_data1 <= sram5_dout1;
- // sram6_data0 <= sram6_dout0;
- // sram6_data1 <= sram6_dout1;
- // sram7_data0 <= sram7_dout0;
- // sram7_data1 <= sram7_dout1;
- sram8_data0 <= sram8_dout0;
- // sram8_data1 <= sram8_dout1;
- sram9_data0 <= sram9_dout0;
- // sram9_data1 <= sram9_dout1;
- sram10_data0 <= sram10_dout0;
- // sram10_data1 <= sram10_dout1;
- sram11_data0 <= sram11_dout0;
- // sram11_data1 <= sram11_dout1;
- // sram12_data0 <= sram12_dout0;
- // sram12_data1 <= sram12_dout1;
- // sram13_data0 <= sram13_dout0;
- // sram13_data1 <= sram13_dout1;
- // sram14_data0 <= sram14_dout0;
- // sram14_data1 <= sram14_dout1;
- // sram15_data0 <= sram15_dout0;
- // sram15_data1 <= sram15_dout1;
- end
-end
wire [`DATA_SIZE-1:0] sram8_data1 = 0;
wire [`DATA_SIZE-1:0] sram9_data1 = 0;
@@ -511,6 +515,11 @@
wire [`DATA_SIZE-1:0] sram6_data1 = 0;
wire [`DATA_SIZE-1:0] sram7_data0 = 0;
wire [`DATA_SIZE-1:0] sram7_data1 = 0;
+ wire [`DATA_SIZE-1:0] sram7_data1 = 0;
+ wire [`DATA_SIZE-1:0] sram8_data1 = 0;
+ wire [`DATA_SIZE-1:0] sram9_data1 = 0;
+ wire [`DATA_SIZE-1:0] sram10_data1 = 0;
+ wire [`DATA_SIZE-1:0] sram11_data1 = 0;
wire [`DATA_SIZE-1:0] sram12_data0 = 0;
wire [`DATA_SIZE-1:0] sram12_data1 = 0;
wire [`DATA_SIZE-1:0] sram13_data0 = 0;
