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foss-eda-tools
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third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
ad78217e5b29a97046e13d55d485e7f45aeef5e1
commit
ad78217e5b29a97046e13d55d485e7f45aeef5e1
[
log
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[
tgz
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author
mrg <mrg@ucsc.edu>
Thu Jun 17 16:48:55 2021 -0700
committer
mrg <mrg@ucsc.edu>
Thu Jun 17 16:48:55 2021 -0700
tree
e57e947dbfd24c80cb19b5ba48cbfc1a39c4e40a
parent
4a0200ec8174b24306e086ef7d39431f675d397b
[
diff
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Change csr to csb
verilog/rtl/openram_testchip.v
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diff
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verilog/rtl/user_project_wrapper.v
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diff
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2 files changed
tree: e57e947dbfd24c80cb19b5ba48cbfc1a39c4e40a
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
single_port/
spi/
verilog/
caravel
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README.md
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