)]}'
{
  "commit": "ad78217e5b29a97046e13d55d485e7f45aeef5e1",
  "tree": "e57e947dbfd24c80cb19b5ba48cbfc1a39c4e40a",
  "parents": [
    "4a0200ec8174b24306e086ef7d39431f675d397b"
  ],
  "author": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Thu Jun 17 16:48:55 2021 -0700"
  },
  "committer": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Thu Jun 17 16:48:55 2021 -0700"
  },
  "message": "Change csr to csb\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e46077eae3a3987252aabc4fff84e4623a8ec807",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip.v",
      "new_id": "c3622d0ef4ec3853c1e02c29b7f4c006eb9afc7a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip.v"
    },
    {
      "type": "modify",
      "old_id": "87b870dc0923fa0b08739858daa2f02eb07a028b",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
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}