Moved files to proper directories
diff --git a/gds/sram_1rw0r0w_32_1024_sky130.gds b/gds/sram_1rw0r0w_32_1024_sky130.gds new file mode 100644 index 0000000..12809dd --- /dev/null +++ b/gds/sram_1rw0r0w_32_1024_sky130.gds Binary files differ
diff --git a/gds/sram_1rw0r0w_32_256_sky130.gds b/gds/sram_1rw0r0w_32_256_sky130.gds new file mode 100644 index 0000000..517adc2 --- /dev/null +++ b/gds/sram_1rw0r0w_32_256_sky130.gds Binary files differ
diff --git a/gds/sram_1rw0r0w_32_512_sky130.gds b/gds/sram_1rw0r0w_32_512_sky130.gds new file mode 100644 index 0000000..89b5ad5 --- /dev/null +++ b/gds/sram_1rw0r0w_32_512_sky130.gds Binary files differ
diff --git a/gds/sram_1rw0r0w_64_512_sky130.gds b/gds/sram_1rw0r0w_64_512_sky130.gds new file mode 100644 index 0000000..8183185 --- /dev/null +++ b/gds/sram_1rw0r0w_64_512_sky130.gds Binary files differ
diff --git a/lef/sram_1rw0r0w_32_1024_sky130.lef b/lef/sram_1rw0r0w_32_1024_sky130.lef new file mode 100644 index 0000000..ca8c720 --- /dev/null +++ b/lef/sram_1rw0r0w_32_1024_sky130.lef
@@ -0,0 +1,779 @@ +VERSION 5.4 ; +NAMESCASESENSITIVE ON ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; +UNITS + DATABASE MICRONS 2000 ; +END UNITS +MACRO sram_1rw0r0w_32_1024_sky130 + CLASS BLOCK ; + SIZE 800.74 BY 347.18 ; + SYMMETRY X Y R90 ; + PIN din0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 124.44 0.0 124.82 0.38 ; + END + END din0[0] + PIN din0[1] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 131.24 0.0 131.62 0.38 ; + END + END din0[1] + PIN din0[2] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 136.0 0.0 136.38 0.38 ; + END + END din0[2] + PIN din0[3] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 142.12 0.0 142.5 0.38 ; + END + END din0[3] + PIN din0[4] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 148.92 0.0 149.3 0.38 ; + END + END din0[4] + PIN din0[5] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 153.68 0.0 154.06 0.38 ; + END + END din0[5] + PIN din0[6] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 160.48 0.0 160.86 0.38 ; + END + END din0[6] + PIN din0[7] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 165.24 0.0 165.62 0.38 ; + END + END din0[7] + PIN din0[8] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 172.04 0.0 172.42 0.38 ; + END + END din0[8] + PIN din0[9] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 178.16 0.0 178.54 0.38 ; + END + END din0[9] + PIN din0[10] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 183.6 0.0 183.98 0.38 ; + END + END din0[10] + PIN din0[11] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 189.72 0.0 190.1 0.38 ; + END + END din0[11] + PIN din0[12] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 195.16 0.0 195.54 0.38 ; + END + END din0[12] + PIN din0[13] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 201.28 0.0 201.66 0.38 ; + END + END din0[13] + PIN din0[14] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 206.04 0.0 206.42 0.38 ; + END + END din0[14] + PIN din0[15] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 212.84 0.0 213.22 0.38 ; + END + END din0[15] + PIN din0[16] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 218.96 0.0 219.34 0.38 ; + END + END din0[16] + PIN din0[17] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 224.4 0.0 224.78 0.38 ; + END + END din0[17] + PIN din0[18] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 230.52 0.0 230.9 0.38 ; + END + END din0[18] + PIN din0[19] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 235.96 0.0 236.34 0.38 ; + END + END din0[19] + PIN din0[20] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 242.08 0.0 242.46 0.38 ; + END + END din0[20] + PIN din0[21] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 248.2 0.0 248.58 0.38 ; + END + END din0[21] + PIN din0[22] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 253.64 0.0 254.02 0.38 ; + END + END din0[22] + PIN din0[23] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 259.76 0.0 260.14 0.38 ; + END + END din0[23] + PIN din0[24] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 264.52 0.0 264.9 0.38 ; + END + END din0[24] + PIN din0[25] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 271.32 0.0 271.7 0.38 ; + END + END din0[25] + PIN din0[26] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 276.08 0.0 276.46 0.38 ; + END + END din0[26] + PIN din0[27] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 282.2 0.0 282.58 0.38 ; + END + END din0[27] + PIN din0[28] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 288.32 0.0 288.7 0.38 ; + END + END din0[28] + PIN din0[29] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 293.76 0.0 294.14 0.38 ; + END + END din0[29] + PIN din0[30] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 300.56 0.0 300.94 0.38 ; + END + END din0[30] + PIN din0[31] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 305.32 0.0 305.7 0.38 ; + END + END din0[31] + PIN din0[32] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 312.12 0.0 312.5 0.38 ; + END + END din0[32] + PIN addr0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 83.64 0.0 84.02 0.38 ; + END + END addr0[0] + PIN addr0[1] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 89.76 0.0 90.14 0.38 ; + END + END addr0[1] + PIN addr0[2] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 95.2 0.0 95.58 0.38 ; + END + END addr0[2] + PIN addr0[3] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 167.96 0.38 168.34 ; + END + END addr0[3] + PIN addr0[4] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 175.44 0.38 175.82 ; + END + END addr0[4] + PIN addr0[5] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 181.56 0.38 181.94 ; + END + END addr0[5] + PIN addr0[6] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 189.72 0.38 190.1 ; + END + END addr0[6] + PIN addr0[7] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 196.52 0.38 196.9 ; + END + END addr0[7] + PIN addr0[8] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 204.68 0.38 205.06 ; + END + END addr0[8] + PIN addr0[9] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 209.44 0.38 209.82 ; + END + END addr0[9] + PIN csb0 + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 64.6 0.38 64.98 ; + END + END csb0 + PIN web0 + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 73.44 0.38 73.82 ; + END + END web0 + PIN clk0 + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 65.28 0.38 65.66 ; + END + END clk0 + PIN wmask0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 101.32 0.0 101.7 0.38 ; + END + END wmask0[0] + PIN wmask0[1] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 107.44 0.0 107.82 0.38 ; + END + END wmask0[1] + PIN wmask0[2] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 113.56 0.0 113.94 0.38 ; + END + END wmask0[2] + PIN wmask0[3] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 119.68 0.0 120.06 0.38 ; + END + END wmask0[3] + PIN spare_wen0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 317.56 0.0 317.94 0.38 ; + END + END spare_wen0[0] + PIN dout0[0] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 145.52 0.0 145.9 0.38 ; + END + END dout0[0] + PIN dout0[1] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 167.28 0.0 167.66 0.38 ; + END + END dout0[1] + PIN dout0[2] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 187.0 0.0 187.38 0.38 ; + END + END dout0[2] + PIN dout0[3] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 207.4 0.0 207.78 0.38 ; + END + END dout0[3] + PIN dout0[4] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 227.12 0.0 227.5 0.38 ; + END + END dout0[4] + PIN dout0[5] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 247.52 0.0 247.9 0.38 ; + END + END dout0[5] + PIN dout0[6] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 267.24 0.0 267.62 0.38 ; + END + END dout0[6] + PIN dout0[7] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 286.28 0.0 286.66 0.38 ; + END + END dout0[7] + PIN dout0[8] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 306.0 0.0 306.38 0.38 ; + END + END dout0[8] + PIN dout0[9] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 327.08 0.0 327.46 0.38 ; + END + END dout0[9] + PIN dout0[10] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 346.8 0.0 347.18 0.38 ; + END + END dout0[10] + PIN dout0[11] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 367.2 0.0 367.58 0.38 ; + END + END dout0[11] + PIN dout0[12] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 386.92 0.0 387.3 0.38 ; + END + END dout0[12] + PIN dout0[13] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 407.32 0.0 407.7 0.38 ; + END + END dout0[13] + PIN dout0[14] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 427.04 0.0 427.42 0.38 ; + END + END dout0[14] + PIN dout0[15] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 446.76 0.0 447.14 0.38 ; + END + END dout0[15] + PIN dout0[16] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 465.8 0.0 466.18 0.38 ; + END + END dout0[16] + PIN dout0[17] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 486.88 0.0 487.26 0.38 ; + END + END dout0[17] + PIN dout0[18] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 507.28 0.0 507.66 0.38 ; + END + END dout0[18] + PIN dout0[19] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 527.0 0.0 527.38 0.38 ; + END + END dout0[19] + PIN dout0[20] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 546.72 0.0 547.1 0.38 ; + END + END dout0[20] + PIN dout0[21] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 567.12 0.0 567.5 0.38 ; + END + END dout0[21] + PIN dout0[22] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 586.84 0.0 587.22 0.38 ; + END + END dout0[22] + PIN dout0[23] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 607.24 0.0 607.62 0.38 ; + END + END dout0[23] + PIN dout0[24] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 625.6 0.0 625.98 0.38 ; + END + END dout0[24] + PIN dout0[25] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 646.68 0.0 647.06 0.38 ; + END + END dout0[25] + PIN dout0[26] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 667.08 0.0 667.46 0.38 ; + END + END dout0[26] + PIN dout0[27] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 686.8 0.0 687.18 0.38 ; + END + END dout0[27] + PIN dout0[28] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 707.2 0.0 707.58 0.38 ; + END + END dout0[28] + PIN dout0[29] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 800.36 90.44 800.74 90.82 ; + END + END dout0[29] + PIN dout0[30] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 800.36 84.32 800.74 84.7 ; + END + END dout0[30] + PIN dout0[31] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 800.36 89.76 800.74 90.14 ; + END + END dout0[31] + PIN dout0[32] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 800.36 85.0 800.74 85.38 ; + END + END dout0[32] + PIN vpwr + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER met4 ; + RECT 1.36 1.36 3.1 347.18 ; + LAYER met3 ; + RECT 1.36 1.36 799.38 3.1 ; + LAYER met4 ; + RECT 797.64 1.36 799.38 347.18 ; + LAYER met3 ; + RECT 1.36 345.44 799.38 347.18 ; + END + END vpwr + PIN vgnd + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 4.76 4.76 795.98 6.5 ; + LAYER met4 ; + RECT 794.24 4.76 795.98 343.78 ; + LAYER met3 ; + RECT 4.76 342.04 795.98 343.78 ; + LAYER met4 ; + RECT 4.76 4.76 6.5 343.78 ; + END + END vgnd + OBS + LAYER met1 ; + RECT 0.62 0.62 800.12 346.56 ; + LAYER met2 ; + RECT 0.62 0.62 800.12 346.56 ; + LAYER met3 ; + RECT 0.98 167.36 800.12 168.94 ; + RECT 0.62 168.94 0.98 174.84 ; + RECT 0.62 176.42 0.98 180.96 ; + RECT 0.62 182.54 0.98 189.12 ; + RECT 0.62 190.7 0.98 195.92 ; + RECT 0.62 197.5 0.98 204.08 ; + RECT 0.62 205.66 0.98 208.84 ; + RECT 0.62 74.42 0.98 167.36 ; + RECT 0.62 66.26 0.98 72.84 ; + RECT 0.98 89.84 799.76 91.42 ; + RECT 0.98 91.42 799.76 167.36 ; + RECT 799.76 91.42 800.12 167.36 ; + RECT 799.76 85.98 800.12 89.16 ; + RECT 0.62 0.62 0.76 0.76 ; + RECT 0.62 0.76 0.76 3.7 ; + RECT 0.62 3.7 0.76 64.0 ; + RECT 0.76 0.62 0.98 0.76 ; + RECT 0.76 3.7 0.98 64.0 ; + RECT 0.98 0.62 799.76 0.76 ; + RECT 799.76 0.62 799.98 0.76 ; + RECT 799.76 3.7 799.98 83.72 ; + RECT 799.98 0.62 800.12 0.76 ; + RECT 799.98 0.76 800.12 3.7 ; + RECT 799.98 3.7 800.12 83.72 ; + RECT 799.98 168.94 800.12 344.84 ; + RECT 799.98 344.84 800.12 346.56 ; + RECT 0.62 210.42 0.76 344.84 ; + RECT 0.62 344.84 0.76 346.56 ; + RECT 0.76 210.42 0.98 344.84 ; + RECT 0.98 3.7 4.16 4.16 ; + RECT 0.98 4.16 4.16 7.1 ; + RECT 0.98 7.1 4.16 89.84 ; + RECT 4.16 3.7 796.58 4.16 ; + RECT 4.16 7.1 796.58 89.84 ; + RECT 796.58 3.7 799.76 4.16 ; + RECT 796.58 4.16 799.76 7.1 ; + RECT 796.58 7.1 799.76 89.84 ; + RECT 0.98 168.94 4.16 341.44 ; + RECT 0.98 341.44 4.16 344.38 ; + RECT 0.98 344.38 4.16 344.84 ; + RECT 4.16 168.94 796.58 341.44 ; + RECT 4.16 344.38 796.58 344.84 ; + RECT 796.58 168.94 799.98 341.44 ; + RECT 796.58 341.44 799.98 344.38 ; + RECT 796.58 344.38 799.98 344.84 ; + LAYER met4 ; + RECT 123.84 0.98 125.42 346.56 ; + RECT 125.42 0.62 130.64 0.98 ; + RECT 132.22 0.62 135.4 0.98 ; + RECT 136.98 0.62 141.52 0.98 ; + RECT 149.9 0.62 153.08 0.98 ; + RECT 154.66 0.62 159.88 0.98 ; + RECT 161.46 0.62 164.64 0.98 ; + RECT 173.02 0.62 177.56 0.98 ; + RECT 179.14 0.62 183.0 0.98 ; + RECT 190.7 0.62 194.56 0.98 ; + RECT 196.14 0.62 200.68 0.98 ; + RECT 202.26 0.62 205.44 0.98 ; + RECT 213.82 0.62 218.36 0.98 ; + RECT 219.94 0.62 223.8 0.98 ; + RECT 231.5 0.62 235.36 0.98 ; + RECT 236.94 0.62 241.48 0.98 ; + RECT 249.18 0.62 253.04 0.98 ; + RECT 254.62 0.62 259.16 0.98 ; + RECT 260.74 0.62 263.92 0.98 ; + RECT 272.3 0.62 275.48 0.98 ; + RECT 277.06 0.62 281.6 0.98 ; + RECT 289.3 0.62 293.16 0.98 ; + RECT 294.74 0.62 299.96 0.98 ; + RECT 301.54 0.62 304.72 0.98 ; + RECT 84.62 0.62 89.16 0.98 ; + RECT 90.74 0.62 94.6 0.98 ; + RECT 96.18 0.62 100.72 0.98 ; + RECT 102.3 0.62 106.84 0.98 ; + RECT 108.42 0.62 112.96 0.98 ; + RECT 114.54 0.62 119.08 0.98 ; + RECT 120.66 0.62 123.84 0.98 ; + RECT 313.1 0.62 316.96 0.98 ; + RECT 143.1 0.62 144.92 0.98 ; + RECT 146.5 0.62 148.32 0.98 ; + RECT 166.22 0.62 166.68 0.98 ; + RECT 168.26 0.62 171.44 0.98 ; + RECT 184.58 0.62 186.4 0.98 ; + RECT 187.98 0.62 189.12 0.98 ; + RECT 208.38 0.62 212.24 0.98 ; + RECT 225.38 0.62 226.52 0.98 ; + RECT 228.1 0.62 229.92 0.98 ; + RECT 243.06 0.62 246.92 0.98 ; + RECT 265.5 0.62 266.64 0.98 ; + RECT 268.22 0.62 270.72 0.98 ; + RECT 283.18 0.62 285.68 0.98 ; + RECT 287.26 0.62 287.72 0.98 ; + RECT 306.98 0.62 311.52 0.98 ; + RECT 318.54 0.62 326.48 0.98 ; + RECT 328.06 0.62 346.2 0.98 ; + RECT 347.78 0.62 366.6 0.98 ; + RECT 368.18 0.62 386.32 0.98 ; + RECT 387.9 0.62 406.72 0.98 ; + RECT 408.3 0.62 426.44 0.98 ; + RECT 428.02 0.62 446.16 0.98 ; + RECT 447.74 0.62 465.2 0.98 ; + RECT 466.78 0.62 486.28 0.98 ; + RECT 487.86 0.62 506.68 0.98 ; + RECT 508.26 0.62 526.4 0.98 ; + RECT 527.98 0.62 546.12 0.98 ; + RECT 547.7 0.62 566.52 0.98 ; + RECT 568.1 0.62 586.24 0.98 ; + RECT 587.82 0.62 606.64 0.98 ; + RECT 608.22 0.62 625.0 0.98 ; + RECT 626.58 0.62 646.08 0.98 ; + RECT 647.66 0.62 666.48 0.98 ; + RECT 668.06 0.62 686.2 0.98 ; + RECT 687.78 0.62 706.6 0.98 ; + RECT 0.62 0.98 0.76 346.56 ; + RECT 0.62 0.62 0.76 0.76 ; + RECT 0.62 0.76 0.76 0.98 ; + RECT 0.76 0.62 3.7 0.76 ; + RECT 3.7 0.62 83.04 0.76 ; + RECT 3.7 0.76 83.04 0.98 ; + RECT 799.98 0.98 800.12 346.56 ; + RECT 708.18 0.62 797.04 0.76 ; + RECT 708.18 0.76 797.04 0.98 ; + RECT 797.04 0.62 799.98 0.76 ; + RECT 799.98 0.62 800.12 0.76 ; + RECT 799.98 0.76 800.12 0.98 ; + RECT 125.42 0.98 793.64 4.16 ; + RECT 125.42 4.16 793.64 344.38 ; + RECT 125.42 344.38 793.64 346.56 ; + RECT 793.64 0.98 796.58 4.16 ; + RECT 793.64 344.38 796.58 346.56 ; + RECT 796.58 0.98 797.04 4.16 ; + RECT 796.58 4.16 797.04 344.38 ; + RECT 796.58 344.38 797.04 346.56 ; + RECT 3.7 0.98 4.16 4.16 ; + RECT 3.7 4.16 4.16 344.38 ; + RECT 3.7 344.38 4.16 346.56 ; + RECT 4.16 0.98 7.1 4.16 ; + RECT 4.16 344.38 7.1 346.56 ; + RECT 7.1 0.98 123.84 4.16 ; + RECT 7.1 4.16 123.84 344.38 ; + RECT 7.1 344.38 123.84 346.56 ; + END +END sram_1rw0r0w_32_1024_sky130 +END LIBRARY
diff --git a/lef/sram_1rw0r0w_32_256_sky130.lef b/lef/sram_1rw0r0w_32_256_sky130.lef new file mode 100644 index 0000000..c1d8347 --- /dev/null +++ b/lef/sram_1rw0r0w_32_256_sky130.lef
@@ -0,0 +1,771 @@ +VERSION 5.4 ; +NAMESCASESENSITIVE ON ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; +UNITS + DATABASE MICRONS 2000 ; +END UNITS +MACRO sram_1rw0r0w_32_256_sky130 + CLASS BLOCK ; + SIZE 472.3 BY 219.34 ; + SYMMETRY X Y R90 ; + PIN din0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 112.88 0.0 113.26 0.38 ; + END + END din0[0] + PIN din0[1] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 118.32 0.0 118.7 0.38 ; + END + END din0[1] + PIN din0[2] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 124.44 0.0 124.82 0.38 ; + END + END din0[2] + PIN din0[3] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 129.88 0.0 130.26 0.38 ; + END + END din0[3] + PIN din0[4] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 136.0 0.0 136.38 0.38 ; + END + END din0[4] + PIN din0[5] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 142.8 0.0 143.18 0.38 ; + END + END din0[5] + PIN din0[6] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 147.56 0.0 147.94 0.38 ; + END + END din0[6] + PIN din0[7] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 153.68 0.0 154.06 0.38 ; + END + END din0[7] + PIN din0[8] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 159.12 0.0 159.5 0.38 ; + END + END din0[8] + PIN din0[9] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 165.24 0.0 165.62 0.38 ; + END + END din0[9] + PIN din0[10] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 170.68 0.0 171.06 0.38 ; + END + END din0[10] + PIN din0[11] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 176.8 0.0 177.18 0.38 ; + END + END din0[11] + PIN din0[12] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 182.92 0.0 183.3 0.38 ; + END + END din0[12] + PIN din0[13] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 188.36 0.0 188.74 0.38 ; + END + END din0[13] + PIN din0[14] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 195.16 0.0 195.54 0.38 ; + END + END din0[14] + PIN din0[15] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 200.6 0.0 200.98 0.38 ; + END + END din0[15] + PIN din0[16] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 206.72 0.0 207.1 0.38 ; + END + END din0[16] + PIN din0[17] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 212.84 0.0 213.22 0.38 ; + END + END din0[17] + PIN din0[18] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 217.6 0.0 217.98 0.38 ; + END + END din0[18] + PIN din0[19] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 224.4 0.0 224.78 0.38 ; + END + END din0[19] + PIN din0[20] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 229.84 0.0 230.22 0.38 ; + END + END din0[20] + PIN din0[21] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 235.96 0.0 236.34 0.38 ; + END + END din0[21] + PIN din0[22] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 242.08 0.0 242.46 0.38 ; + END + END din0[22] + PIN din0[23] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 247.52 0.0 247.9 0.38 ; + END + END din0[23] + PIN din0[24] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 252.96 0.0 253.34 0.38 ; + END + END din0[24] + PIN din0[25] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 259.08 0.0 259.46 0.38 ; + END + END din0[25] + PIN din0[26] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 265.2 0.0 265.58 0.38 ; + END + END din0[26] + PIN din0[27] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 270.64 0.0 271.02 0.38 ; + END + END din0[27] + PIN din0[28] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 276.08 0.0 276.46 0.38 ; + END + END din0[28] + PIN din0[29] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 282.2 0.0 282.58 0.38 ; + END + END din0[29] + PIN din0[30] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 287.64 0.0 288.02 0.38 ; + END + END din0[30] + PIN din0[31] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 294.44 0.0 294.82 0.38 ; + END + END din0[31] + PIN din0[32] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 299.2 0.0 299.58 0.38 ; + END + END din0[32] + PIN addr0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 77.52 0.0 77.9 0.38 ; + END + END addr0[0] + PIN addr0[1] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 83.64 0.0 84.02 0.38 ; + END + END addr0[1] + PIN addr0[2] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 132.6 0.38 132.98 ; + END + END addr0[2] + PIN addr0[3] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 140.76 0.38 141.14 ; + END + END addr0[3] + PIN addr0[4] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 146.88 0.38 147.26 ; + END + END addr0[4] + PIN addr0[5] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 67.32 218.96 67.7 219.34 ; + END + END addr0[5] + PIN addr0[6] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 66.64 218.96 67.02 219.34 ; + END + END addr0[6] + PIN addr0[7] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 65.96 218.96 66.34 219.34 ; + END + END addr0[7] + PIN csb0 + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 36.72 0.38 37.1 ; + END + END csb0 + PIN web0 + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 45.56 0.38 45.94 ; + END + END web0 + PIN clk0 + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 37.4 0.38 37.78 ; + END + END clk0 + PIN wmask0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 89.76 0.0 90.14 0.38 ; + END + END wmask0[0] + PIN wmask0[1] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 95.2 0.0 95.58 0.38 ; + END + END wmask0[1] + PIN wmask0[2] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 102.0 0.0 102.38 0.38 ; + END + END wmask0[2] + PIN wmask0[3] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 107.44 0.0 107.82 0.38 ; + END + END wmask0[3] + PIN spare_wen0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 306.0 0.0 306.38 0.38 ; + END + END spare_wen0[0] + PIN dout0[0] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 139.4 0.0 139.78 0.38 ; + END + END dout0[0] + PIN dout0[1] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 148.92 0.0 149.3 0.38 ; + END + END dout0[1] + PIN dout0[2] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 157.76 0.0 158.14 0.38 ; + END + END dout0[2] + PIN dout0[3] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 168.64 0.0 169.02 0.38 ; + END + END dout0[3] + PIN dout0[4] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 178.84 0.0 179.22 0.38 ; + END + END dout0[4] + PIN dout0[5] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 189.04 0.0 189.42 0.38 ; + END + END dout0[5] + PIN dout0[6] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 198.56 0.0 198.94 0.38 ; + END + END dout0[6] + PIN dout0[7] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 208.76 0.0 209.14 0.38 ; + END + END dout0[7] + PIN dout0[8] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 216.24 0.0 216.62 0.38 ; + END + END dout0[8] + PIN dout0[9] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 227.8 0.0 228.18 0.38 ; + END + END dout0[9] + PIN dout0[10] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 238.68 0.0 239.06 0.38 ; + END + END dout0[10] + PIN dout0[11] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 248.88 0.0 249.26 0.38 ; + END + END dout0[11] + PIN dout0[12] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 257.04 0.0 257.42 0.38 ; + END + END dout0[12] + PIN dout0[13] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 268.6 0.0 268.98 0.38 ; + END + END dout0[13] + PIN dout0[14] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 278.8 0.0 279.18 0.38 ; + END + END dout0[14] + PIN dout0[15] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 289.0 0.0 289.38 0.38 ; + END + END dout0[15] + PIN dout0[16] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 297.84 0.0 298.22 0.38 ; + END + END dout0[16] + PIN dout0[17] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 309.4 0.0 309.78 0.38 ; + END + END dout0[17] + PIN dout0[18] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 318.92 0.0 319.3 0.38 ; + END + END dout0[18] + PIN dout0[19] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 329.12 0.0 329.5 0.38 ; + END + END dout0[19] + PIN dout0[20] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 338.64 0.0 339.02 0.38 ; + END + END dout0[20] + PIN dout0[21] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 348.84 0.0 349.22 0.38 ; + END + END dout0[21] + PIN dout0[22] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 359.04 0.0 359.42 0.38 ; + END + END dout0[22] + PIN dout0[23] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 369.24 0.0 369.62 0.38 ; + END + END dout0[23] + PIN dout0[24] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 377.4 0.0 377.78 0.38 ; + END + END dout0[24] + PIN dout0[25] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 388.96 0.0 389.34 0.38 ; + END + END dout0[25] + PIN dout0[26] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 399.16 0.0 399.54 0.38 ; + END + END dout0[26] + PIN dout0[27] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 408.68 0.0 409.06 0.38 ; + END + END dout0[27] + PIN dout0[28] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 471.92 58.48 472.3 58.86 ; + END + END dout0[28] + PIN dout0[29] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 471.92 59.16 472.3 59.54 ; + END + END dout0[29] + PIN dout0[30] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 471.92 63.92 472.3 64.3 ; + END + END dout0[30] + PIN dout0[31] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 471.92 59.84 472.3 60.22 ; + END + END dout0[31] + PIN dout0[32] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 471.92 61.88 472.3 62.26 ; + END + END dout0[32] + PIN vpwr + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER met4 ; + RECT 469.2 1.36 470.94 217.98 ; + LAYER met3 ; + RECT 1.36 216.24 470.94 217.98 ; + LAYER met3 ; + RECT 1.36 1.36 470.94 3.1 ; + LAYER met4 ; + RECT 1.36 1.36 3.1 217.98 ; + END + END vpwr + PIN vgnd + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER met4 ; + RECT 4.76 4.76 6.5 214.58 ; + LAYER met3 ; + RECT 4.76 212.84 467.54 214.58 ; + LAYER met3 ; + RECT 4.76 4.76 467.54 6.5 ; + LAYER met4 ; + RECT 465.8 4.76 467.54 214.58 ; + END + END vgnd + OBS + LAYER met1 ; + RECT 0.62 0.62 471.68 218.72 ; + LAYER met2 ; + RECT 0.62 0.62 471.68 218.72 ; + LAYER met3 ; + RECT 0.98 132.0 471.68 133.58 ; + RECT 0.62 133.58 0.98 140.16 ; + RECT 0.62 141.74 0.98 146.28 ; + RECT 0.62 46.54 0.98 132.0 ; + RECT 0.62 38.38 0.98 44.96 ; + RECT 0.98 57.88 471.32 59.46 ; + RECT 0.98 59.46 471.32 132.0 ; + RECT 471.32 64.9 471.68 132.0 ; + RECT 471.32 60.82 471.68 61.28 ; + RECT 471.32 62.86 471.68 63.32 ; + RECT 0.98 218.58 471.54 218.72 ; + RECT 471.54 133.58 471.68 215.64 ; + RECT 471.54 215.64 471.68 218.58 ; + RECT 471.54 218.58 471.68 218.72 ; + RECT 0.62 147.86 0.76 215.64 ; + RECT 0.62 215.64 0.76 218.58 ; + RECT 0.62 218.58 0.76 218.72 ; + RECT 0.76 147.86 0.98 215.64 ; + RECT 0.76 218.58 0.98 218.72 ; + RECT 0.62 0.62 0.76 0.76 ; + RECT 0.62 0.76 0.76 3.7 ; + RECT 0.62 3.7 0.76 36.12 ; + RECT 0.76 0.62 0.98 0.76 ; + RECT 0.76 3.7 0.98 36.12 ; + RECT 0.98 0.62 471.32 0.76 ; + RECT 471.32 0.62 471.54 0.76 ; + RECT 471.32 3.7 471.54 57.88 ; + RECT 471.54 0.62 471.68 0.76 ; + RECT 471.54 0.76 471.68 3.7 ; + RECT 471.54 3.7 471.68 57.88 ; + RECT 0.98 133.58 4.16 212.24 ; + RECT 0.98 212.24 4.16 215.18 ; + RECT 0.98 215.18 4.16 215.64 ; + RECT 4.16 133.58 468.14 212.24 ; + RECT 4.16 215.18 468.14 215.64 ; + RECT 468.14 133.58 471.54 212.24 ; + RECT 468.14 212.24 471.54 215.18 ; + RECT 468.14 215.18 471.54 215.64 ; + RECT 0.98 3.7 4.16 4.16 ; + RECT 0.98 4.16 4.16 7.1 ; + RECT 0.98 7.1 4.16 57.88 ; + RECT 4.16 3.7 468.14 4.16 ; + RECT 4.16 7.1 468.14 57.88 ; + RECT 468.14 3.7 471.32 4.16 ; + RECT 468.14 4.16 471.32 7.1 ; + RECT 468.14 7.1 471.32 57.88 ; + LAYER met4 ; + RECT 112.28 0.98 113.86 218.72 ; + RECT 113.86 0.62 117.72 0.98 ; + RECT 119.3 0.62 123.84 0.98 ; + RECT 125.42 0.62 129.28 0.98 ; + RECT 130.86 0.62 135.4 0.98 ; + RECT 143.78 0.62 146.96 0.98 ; + RECT 160.1 0.62 164.64 0.98 ; + RECT 171.66 0.62 176.2 0.98 ; + RECT 183.9 0.62 187.76 0.98 ; + RECT 201.58 0.62 206.12 0.98 ; + RECT 218.58 0.62 223.8 0.98 ; + RECT 230.82 0.62 235.36 0.98 ; + RECT 243.06 0.62 246.92 0.98 ; + RECT 260.06 0.62 264.6 0.98 ; + RECT 271.62 0.62 275.48 0.98 ; + RECT 283.18 0.62 287.04 0.98 ; + RECT 78.5 0.62 83.04 0.98 ; + RECT 66.72 0.98 68.3 218.36 ; + RECT 68.3 0.98 112.28 218.36 ; + RECT 68.3 218.36 112.28 218.72 ; + RECT 84.62 0.62 89.16 0.98 ; + RECT 90.74 0.62 94.6 0.98 ; + RECT 96.18 0.62 101.4 0.98 ; + RECT 102.98 0.62 106.84 0.98 ; + RECT 108.42 0.62 112.28 0.98 ; + RECT 300.18 0.62 305.4 0.98 ; + RECT 136.98 0.62 138.8 0.98 ; + RECT 140.38 0.62 142.2 0.98 ; + RECT 149.9 0.62 153.08 0.98 ; + RECT 154.66 0.62 157.16 0.98 ; + RECT 166.22 0.62 168.04 0.98 ; + RECT 169.62 0.62 170.08 0.98 ; + RECT 177.78 0.62 178.24 0.98 ; + RECT 179.82 0.62 182.32 0.98 ; + RECT 190.02 0.62 194.56 0.98 ; + RECT 196.14 0.62 197.96 0.98 ; + RECT 199.54 0.62 200.0 0.98 ; + RECT 207.7 0.62 208.16 0.98 ; + RECT 209.74 0.62 212.24 0.98 ; + RECT 213.82 0.62 215.64 0.98 ; + RECT 225.38 0.62 227.2 0.98 ; + RECT 228.78 0.62 229.24 0.98 ; + RECT 236.94 0.62 238.08 0.98 ; + RECT 239.66 0.62 241.48 0.98 ; + RECT 249.86 0.62 252.36 0.98 ; + RECT 253.94 0.62 256.44 0.98 ; + RECT 258.02 0.62 258.48 0.98 ; + RECT 266.18 0.62 268.0 0.98 ; + RECT 269.58 0.62 270.04 0.98 ; + RECT 277.06 0.62 278.2 0.98 ; + RECT 279.78 0.62 281.6 0.98 ; + RECT 289.98 0.62 293.84 0.98 ; + RECT 295.42 0.62 297.24 0.98 ; + RECT 306.98 0.62 308.8 0.98 ; + RECT 310.38 0.62 318.32 0.98 ; + RECT 319.9 0.62 328.52 0.98 ; + RECT 330.1 0.62 338.04 0.98 ; + RECT 339.62 0.62 348.24 0.98 ; + RECT 349.82 0.62 358.44 0.98 ; + RECT 360.02 0.62 368.64 0.98 ; + RECT 370.22 0.62 376.8 0.98 ; + RECT 378.38 0.62 388.36 0.98 ; + RECT 389.94 0.62 398.56 0.98 ; + RECT 400.14 0.62 408.08 0.98 ; + RECT 113.86 218.58 468.6 218.72 ; + RECT 468.6 218.58 471.54 218.72 ; + RECT 471.54 0.98 471.68 218.58 ; + RECT 471.54 218.58 471.68 218.72 ; + RECT 409.66 0.62 468.6 0.76 ; + RECT 409.66 0.76 468.6 0.98 ; + RECT 468.6 0.62 471.54 0.76 ; + RECT 471.54 0.62 471.68 0.76 ; + RECT 471.54 0.76 471.68 0.98 ; + RECT 0.62 0.62 0.76 0.76 ; + RECT 0.62 0.76 0.76 0.98 ; + RECT 0.76 0.62 3.7 0.76 ; + RECT 3.7 0.62 76.92 0.76 ; + RECT 3.7 0.76 76.92 0.98 ; + RECT 0.62 0.98 0.76 218.36 ; + RECT 0.62 218.36 0.76 218.58 ; + RECT 0.62 218.58 0.76 218.72 ; + RECT 0.76 218.58 3.7 218.72 ; + RECT 3.7 218.36 65.36 218.58 ; + RECT 3.7 218.58 65.36 218.72 ; + RECT 3.7 0.98 4.16 4.16 ; + RECT 3.7 4.16 4.16 215.18 ; + RECT 3.7 215.18 4.16 218.36 ; + RECT 4.16 0.98 7.1 4.16 ; + RECT 4.16 215.18 7.1 218.36 ; + RECT 7.1 0.98 66.72 4.16 ; + RECT 7.1 4.16 66.72 215.18 ; + RECT 7.1 215.18 66.72 218.36 ; + RECT 113.86 0.98 465.2 4.16 ; + RECT 113.86 4.16 465.2 215.18 ; + RECT 113.86 215.18 465.2 218.58 ; + RECT 465.2 0.98 468.14 4.16 ; + RECT 465.2 215.18 468.14 218.58 ; + RECT 468.14 0.98 468.6 4.16 ; + RECT 468.14 4.16 468.6 215.18 ; + RECT 468.14 215.18 468.6 218.58 ; + END +END sram_1rw0r0w_32_256_sky130 +END LIBRARY
diff --git a/lef/sram_1rw0r0w_32_512_sky130.lef b/lef/sram_1rw0r0w_32_512_sky130.lef new file mode 100644 index 0000000..85dd8f6 --- /dev/null +++ b/lef/sram_1rw0r0w_32_512_sky130.lef
@@ -0,0 +1,768 @@ +VERSION 5.4 ; +NAMESCASESENSITIVE ON ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; +UNITS + DATABASE MICRONS 2000 ; +END UNITS +MACRO sram_1rw0r0w_32_512_sky130 + CLASS BLOCK ; + SIZE 475.02 BY 319.3 ; + SYMMETRY X Y R90 ; + PIN din0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 113.56 0.0 113.94 0.38 ; + END + END din0[0] + PIN din0[1] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 119.0 0.0 119.38 0.38 ; + END + END din0[1] + PIN din0[2] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 125.12 0.0 125.5 0.38 ; + END + END din0[2] + PIN din0[3] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 130.56 0.0 130.94 0.38 ; + END + END din0[3] + PIN din0[4] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 136.68 0.0 137.06 0.38 ; + END + END din0[4] + PIN din0[5] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 143.48 0.0 143.86 0.38 ; + END + END din0[5] + PIN din0[6] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 148.24 0.0 148.62 0.38 ; + END + END din0[6] + PIN din0[7] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 154.36 0.0 154.74 0.38 ; + END + END din0[7] + PIN din0[8] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 159.8 0.0 160.18 0.38 ; + END + END din0[8] + PIN din0[9] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 165.92 0.0 166.3 0.38 ; + END + END din0[9] + PIN din0[10] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 171.36 0.0 171.74 0.38 ; + END + END din0[10] + PIN din0[11] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 177.48 0.0 177.86 0.38 ; + END + END din0[11] + PIN din0[12] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 183.6 0.0 183.98 0.38 ; + END + END din0[12] + PIN din0[13] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 189.04 0.0 189.42 0.38 ; + END + END din0[13] + PIN din0[14] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 195.84 0.0 196.22 0.38 ; + END + END din0[14] + PIN din0[15] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 201.28 0.0 201.66 0.38 ; + END + END din0[15] + PIN din0[16] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 207.4 0.0 207.78 0.38 ; + END + END din0[16] + PIN din0[17] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 213.52 0.0 213.9 0.38 ; + END + END din0[17] + PIN din0[18] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 218.28 0.0 218.66 0.38 ; + END + END din0[18] + PIN din0[19] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 225.08 0.0 225.46 0.38 ; + END + END din0[19] + PIN din0[20] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 230.52 0.0 230.9 0.38 ; + END + END din0[20] + PIN din0[21] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 236.64 0.0 237.02 0.38 ; + END + END din0[21] + PIN din0[22] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 242.76 0.0 243.14 0.38 ; + END + END din0[22] + PIN din0[23] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 248.2 0.0 248.58 0.38 ; + END + END din0[23] + PIN din0[24] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 253.64 0.0 254.02 0.38 ; + END + END din0[24] + PIN din0[25] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 259.76 0.0 260.14 0.38 ; + END + END din0[25] + PIN din0[26] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 265.88 0.0 266.26 0.38 ; + END + END din0[26] + PIN din0[27] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 271.32 0.0 271.7 0.38 ; + END + END din0[27] + PIN din0[28] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 276.76 0.0 277.14 0.38 ; + END + END din0[28] + PIN din0[29] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 282.88 0.0 283.26 0.38 ; + END + END din0[29] + PIN din0[30] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 288.32 0.0 288.7 0.38 ; + END + END din0[30] + PIN din0[31] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 295.12 0.0 295.5 0.38 ; + END + END din0[31] + PIN din0[32] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 299.88 0.0 300.26 0.38 ; + END + END din0[32] + PIN addr0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 78.2 0.0 78.58 0.38 ; + END + END addr0[0] + PIN addr0[1] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 84.32 0.0 84.7 0.38 ; + END + END addr0[1] + PIN addr0[2] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 138.72 0.38 139.1 ; + END + END addr0[2] + PIN addr0[3] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 147.56 0.38 147.94 ; + END + END addr0[3] + PIN addr0[4] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 152.32 0.38 152.7 ; + END + END addr0[4] + PIN addr0[5] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 163.2 0.38 163.58 ; + END + END addr0[5] + PIN addr0[6] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 167.96 0.38 168.34 ; + END + END addr0[6] + PIN addr0[7] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 175.44 0.38 175.82 ; + END + END addr0[7] + PIN addr0[8] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 181.56 0.38 181.94 ; + END + END addr0[8] + PIN csb0 + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 36.72 0.38 37.1 ; + END + END csb0 + PIN web0 + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 43.52 0.38 43.9 ; + END + END web0 + PIN clk0 + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 37.4 0.38 37.78 ; + END + END clk0 + PIN wmask0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 90.44 0.0 90.82 0.38 ; + END + END wmask0[0] + PIN wmask0[1] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 95.88 0.0 96.26 0.38 ; + END + END wmask0[1] + PIN wmask0[2] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 102.68 0.0 103.06 0.38 ; + END + END wmask0[2] + PIN wmask0[3] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 108.12 0.0 108.5 0.38 ; + END + END wmask0[3] + PIN spare_wen0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 306.68 0.0 307.06 0.38 ; + END + END spare_wen0[0] + PIN dout0[0] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 140.08 0.0 140.46 0.38 ; + END + END dout0[0] + PIN dout0[1] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 151.64 0.0 152.02 0.38 ; + END + END dout0[1] + PIN dout0[2] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 161.84 0.0 162.22 0.38 ; + END + END dout0[2] + PIN dout0[3] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 172.04 0.0 172.42 0.38 ; + END + END dout0[3] + PIN dout0[4] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 181.56 0.0 181.94 0.38 ; + END + END dout0[4] + PIN dout0[5] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 191.76 0.0 192.14 0.38 ; + END + END dout0[5] + PIN dout0[6] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 201.96 0.0 202.34 0.38 ; + END + END dout0[6] + PIN dout0[7] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 210.8 0.0 211.18 0.38 ; + END + END dout0[7] + PIN dout0[8] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 220.32 0.0 220.7 0.38 ; + END + END dout0[8] + PIN dout0[9] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 231.88 0.0 232.26 0.38 ; + END + END dout0[9] + PIN dout0[10] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 242.08 0.0 242.46 0.38 ; + END + END dout0[10] + PIN dout0[11] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 251.6 0.0 251.98 0.38 ; + END + END dout0[11] + PIN dout0[12] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 261.8 0.0 262.18 0.38 ; + END + END dout0[12] + PIN dout0[13] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 272.0 0.0 272.38 0.38 ; + END + END dout0[13] + PIN dout0[14] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 280.84 0.0 281.22 0.38 ; + END + END dout0[14] + PIN dout0[15] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 291.72 0.0 292.1 0.38 ; + END + END dout0[15] + PIN dout0[16] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 300.56 0.0 300.94 0.38 ; + END + END dout0[16] + PIN dout0[17] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 310.08 0.0 310.46 0.38 ; + END + END dout0[17] + PIN dout0[18] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 321.64 0.0 322.02 0.38 ; + END + END dout0[18] + PIN dout0[19] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 331.84 0.0 332.22 0.38 ; + END + END dout0[19] + PIN dout0[20] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 341.36 0.0 341.74 0.38 ; + END + END dout0[20] + PIN dout0[21] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 351.56 0.0 351.94 0.38 ; + END + END dout0[21] + PIN dout0[22] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 361.76 0.0 362.14 0.38 ; + END + END dout0[22] + PIN dout0[23] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 371.96 0.0 372.34 0.38 ; + END + END dout0[23] + PIN dout0[24] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 380.12 0.0 380.5 0.38 ; + END + END dout0[24] + PIN dout0[25] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 391.68 0.0 392.06 0.38 ; + END + END dout0[25] + PIN dout0[26] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 401.88 0.0 402.26 0.38 ; + END + END dout0[26] + PIN dout0[27] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 411.4 0.0 411.78 0.38 ; + END + END dout0[27] + PIN dout0[28] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 474.64 58.48 475.02 58.86 ; + END + END dout0[28] + PIN dout0[29] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 474.64 59.16 475.02 59.54 ; + END + END dout0[29] + PIN dout0[30] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 474.64 63.92 475.02 64.3 ; + END + END dout0[30] + PIN dout0[31] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 474.64 59.84 475.02 60.22 ; + END + END dout0[31] + PIN dout0[32] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 474.64 61.88 475.02 62.26 ; + END + END dout0[32] + PIN vpwr + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1.36 317.56 473.66 319.3 ; + LAYER met4 ; + RECT 1.36 1.36 3.1 319.3 ; + LAYER met3 ; + RECT 1.36 1.36 473.66 3.1 ; + LAYER met4 ; + RECT 471.92 1.36 473.66 319.3 ; + END + END vpwr + PIN vgnd + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 4.76 4.76 470.26 6.5 ; + LAYER met4 ; + RECT 4.76 4.76 6.5 315.9 ; + LAYER met3 ; + RECT 4.76 314.16 470.26 315.9 ; + LAYER met4 ; + RECT 468.52 4.76 470.26 315.9 ; + END + END vgnd + OBS + LAYER met1 ; + RECT 0.62 0.62 474.4 318.68 ; + LAYER met2 ; + RECT 0.62 0.62 474.4 318.68 ; + LAYER met3 ; + RECT 0.98 138.12 474.4 139.7 ; + RECT 0.62 139.7 0.98 146.96 ; + RECT 0.62 148.54 0.98 151.72 ; + RECT 0.62 153.3 0.98 162.6 ; + RECT 0.62 164.18 0.98 167.36 ; + RECT 0.62 168.94 0.98 174.84 ; + RECT 0.62 176.42 0.98 180.96 ; + RECT 0.62 44.5 0.98 138.12 ; + RECT 0.62 38.38 0.98 42.92 ; + RECT 0.98 57.88 474.04 59.46 ; + RECT 0.98 59.46 474.04 138.12 ; + RECT 474.04 64.9 474.4 138.12 ; + RECT 474.04 60.82 474.4 61.28 ; + RECT 474.04 62.86 474.4 63.32 ; + RECT 474.26 139.7 474.4 316.96 ; + RECT 474.26 316.96 474.4 318.68 ; + RECT 0.62 182.54 0.76 316.96 ; + RECT 0.62 316.96 0.76 318.68 ; + RECT 0.76 182.54 0.98 316.96 ; + RECT 0.62 0.62 0.76 0.76 ; + RECT 0.62 0.76 0.76 3.7 ; + RECT 0.62 3.7 0.76 36.12 ; + RECT 0.76 0.62 0.98 0.76 ; + RECT 0.76 3.7 0.98 36.12 ; + RECT 0.98 0.62 474.04 0.76 ; + RECT 474.04 0.62 474.26 0.76 ; + RECT 474.04 3.7 474.26 57.88 ; + RECT 474.26 0.62 474.4 0.76 ; + RECT 474.26 0.76 474.4 3.7 ; + RECT 474.26 3.7 474.4 57.88 ; + RECT 0.98 3.7 4.16 4.16 ; + RECT 0.98 4.16 4.16 7.1 ; + RECT 0.98 7.1 4.16 57.88 ; + RECT 4.16 3.7 470.86 4.16 ; + RECT 4.16 7.1 470.86 57.88 ; + RECT 470.86 3.7 474.04 4.16 ; + RECT 470.86 4.16 474.04 7.1 ; + RECT 470.86 7.1 474.04 57.88 ; + RECT 0.98 139.7 4.16 313.56 ; + RECT 0.98 313.56 4.16 316.5 ; + RECT 0.98 316.5 4.16 316.96 ; + RECT 4.16 139.7 470.86 313.56 ; + RECT 4.16 316.5 470.86 316.96 ; + RECT 470.86 139.7 474.26 313.56 ; + RECT 470.86 313.56 474.26 316.5 ; + RECT 470.86 316.5 474.26 316.96 ; + LAYER met4 ; + RECT 112.96 0.98 114.54 318.68 ; + RECT 114.54 0.62 118.4 0.98 ; + RECT 119.98 0.62 124.52 0.98 ; + RECT 126.1 0.62 129.96 0.98 ; + RECT 131.54 0.62 136.08 0.98 ; + RECT 144.46 0.62 147.64 0.98 ; + RECT 155.34 0.62 159.2 0.98 ; + RECT 166.9 0.62 170.76 0.98 ; + RECT 184.58 0.62 188.44 0.98 ; + RECT 196.82 0.62 200.68 0.98 ; + RECT 214.5 0.62 217.68 0.98 ; + RECT 226.06 0.62 229.92 0.98 ; + RECT 243.74 0.62 247.6 0.98 ; + RECT 254.62 0.62 259.16 0.98 ; + RECT 266.86 0.62 270.72 0.98 ; + RECT 283.86 0.62 287.72 0.98 ; + RECT 296.1 0.62 299.28 0.98 ; + RECT 79.18 0.62 83.72 0.98 ; + RECT 85.3 0.62 89.84 0.98 ; + RECT 91.42 0.62 95.28 0.98 ; + RECT 96.86 0.62 102.08 0.98 ; + RECT 103.66 0.62 107.52 0.98 ; + RECT 109.1 0.62 112.96 0.98 ; + RECT 137.66 0.62 139.48 0.98 ; + RECT 141.06 0.62 142.88 0.98 ; + RECT 149.22 0.62 151.04 0.98 ; + RECT 152.62 0.62 153.76 0.98 ; + RECT 160.78 0.62 161.24 0.98 ; + RECT 162.82 0.62 165.32 0.98 ; + RECT 173.02 0.62 176.88 0.98 ; + RECT 178.46 0.62 180.96 0.98 ; + RECT 182.54 0.62 183.0 0.98 ; + RECT 190.02 0.62 191.16 0.98 ; + RECT 192.74 0.62 195.24 0.98 ; + RECT 202.94 0.62 206.8 0.98 ; + RECT 208.38 0.62 210.2 0.98 ; + RECT 211.78 0.62 212.92 0.98 ; + RECT 219.26 0.62 219.72 0.98 ; + RECT 221.3 0.62 224.48 0.98 ; + RECT 232.86 0.62 236.04 0.98 ; + RECT 237.62 0.62 241.48 0.98 ; + RECT 249.18 0.62 251.0 0.98 ; + RECT 252.58 0.62 253.04 0.98 ; + RECT 260.74 0.62 261.2 0.98 ; + RECT 262.78 0.62 265.28 0.98 ; + RECT 272.98 0.62 276.16 0.98 ; + RECT 277.74 0.62 280.24 0.98 ; + RECT 281.82 0.62 282.28 0.98 ; + RECT 289.3 0.62 291.12 0.98 ; + RECT 292.7 0.62 294.52 0.98 ; + RECT 301.54 0.62 306.08 0.98 ; + RECT 307.66 0.62 309.48 0.98 ; + RECT 311.06 0.62 321.04 0.98 ; + RECT 322.62 0.62 331.24 0.98 ; + RECT 332.82 0.62 340.76 0.98 ; + RECT 342.34 0.62 350.96 0.98 ; + RECT 352.54 0.62 361.16 0.98 ; + RECT 362.74 0.62 371.36 0.98 ; + RECT 372.94 0.62 379.52 0.98 ; + RECT 381.1 0.62 391.08 0.98 ; + RECT 392.66 0.62 401.28 0.98 ; + RECT 402.86 0.62 410.8 0.98 ; + RECT 0.62 0.98 0.76 318.68 ; + RECT 0.62 0.62 0.76 0.76 ; + RECT 0.62 0.76 0.76 0.98 ; + RECT 0.76 0.62 3.7 0.76 ; + RECT 3.7 0.62 77.6 0.76 ; + RECT 3.7 0.76 77.6 0.98 ; + RECT 474.26 0.98 474.4 318.68 ; + RECT 412.38 0.62 471.32 0.76 ; + RECT 412.38 0.76 471.32 0.98 ; + RECT 471.32 0.62 474.26 0.76 ; + RECT 474.26 0.62 474.4 0.76 ; + RECT 474.26 0.76 474.4 0.98 ; + RECT 3.7 0.98 4.16 4.16 ; + RECT 3.7 4.16 4.16 316.5 ; + RECT 3.7 316.5 4.16 318.68 ; + RECT 4.16 0.98 7.1 4.16 ; + RECT 4.16 316.5 7.1 318.68 ; + RECT 7.1 0.98 112.96 4.16 ; + RECT 7.1 4.16 112.96 316.5 ; + RECT 7.1 316.5 112.96 318.68 ; + RECT 114.54 0.98 467.92 4.16 ; + RECT 114.54 4.16 467.92 316.5 ; + RECT 114.54 316.5 467.92 318.68 ; + RECT 467.92 0.98 470.86 4.16 ; + RECT 467.92 316.5 470.86 318.68 ; + RECT 470.86 0.98 471.32 4.16 ; + RECT 470.86 4.16 471.32 316.5 ; + RECT 470.86 316.5 471.32 318.68 ; + END +END sram_1rw0r0w_32_512_sky130 +END LIBRARY
diff --git a/lef/sram_1rw0r0w_64_512_sky130.lef b/lef/sram_1rw0r0w_64_512_sky130.lef new file mode 100644 index 0000000..8a2b202 --- /dev/null +++ b/lef/sram_1rw0r0w_64_512_sky130.lef
@@ -0,0 +1,1304 @@ +VERSION 5.4 ; +NAMESCASESENSITIVE ON ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; +UNITS + DATABASE MICRONS 2000 ; +END UNITS +MACRO sram_1rw0r0w_64_512_sky130 + CLASS BLOCK ; + SIZE 822.5 BY 334.94 ; + SYMMETRY X Y R90 ; + PIN din0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 163.88 0.0 164.26 0.38 ; + END + END din0[0] + PIN din0[1] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 170.68 0.0 171.06 0.38 ; + END + END din0[1] + PIN din0[2] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 176.12 0.0 176.5 0.38 ; + END + END din0[2] + PIN din0[3] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 181.56 0.0 181.94 0.38 ; + END + END din0[3] + PIN din0[4] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 187.68 0.0 188.06 0.38 ; + END + END din0[4] + PIN din0[5] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 193.12 0.0 193.5 0.38 ; + END + END din0[5] + PIN din0[6] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 199.92 0.0 200.3 0.38 ; + END + END din0[6] + PIN din0[7] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 204.68 0.0 205.06 0.38 ; + END + END din0[7] + PIN din0[8] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 211.48 0.0 211.86 0.38 ; + END + END din0[8] + PIN din0[9] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 216.24 0.0 216.62 0.38 ; + END + END din0[9] + PIN din0[10] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 223.04 0.0 223.42 0.38 ; + END + END din0[10] + PIN din0[11] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 229.16 0.0 229.54 0.38 ; + END + END din0[11] + PIN din0[12] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 234.6 0.0 234.98 0.38 ; + END + END din0[12] + PIN din0[13] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 240.04 0.0 240.42 0.38 ; + END + END din0[13] + PIN din0[14] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 246.16 0.0 246.54 0.38 ; + END + END din0[14] + PIN din0[15] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 252.28 0.0 252.66 0.38 ; + END + END din0[15] + PIN din0[16] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 257.72 0.0 258.1 0.38 ; + END + END din0[16] + PIN din0[17] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 263.84 0.0 264.22 0.38 ; + END + END din0[17] + PIN din0[18] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 269.96 0.0 270.34 0.38 ; + END + END din0[18] + PIN din0[19] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 274.72 0.0 275.1 0.38 ; + END + END din0[19] + PIN din0[20] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 281.52 0.0 281.9 0.38 ; + END + END din0[20] + PIN din0[21] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 286.28 0.0 286.66 0.38 ; + END + END din0[21] + PIN din0[22] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 293.08 0.0 293.46 0.38 ; + END + END din0[22] + PIN din0[23] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 298.52 0.0 298.9 0.38 ; + END + END din0[23] + PIN din0[24] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 304.64 0.0 305.02 0.38 ; + END + END din0[24] + PIN din0[25] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 310.08 0.0 310.46 0.38 ; + END + END din0[25] + PIN din0[26] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 316.2 0.0 316.58 0.38 ; + END + END din0[26] + PIN din0[27] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 321.64 0.0 322.02 0.38 ; + END + END din0[27] + PIN din0[28] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 327.76 0.0 328.14 0.38 ; + END + END din0[28] + PIN din0[29] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 333.2 0.0 333.58 0.38 ; + END + END din0[29] + PIN din0[30] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 340.0 0.0 340.38 0.38 ; + END + END din0[30] + PIN din0[31] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 344.76 0.0 345.14 0.38 ; + END + END din0[31] + PIN din0[32] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 351.56 0.0 351.94 0.38 ; + END + END din0[32] + PIN din0[33] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 357.0 0.0 357.38 0.38 ; + END + END din0[33] + PIN din0[34] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 362.44 0.0 362.82 0.38 ; + END + END din0[34] + PIN din0[35] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 368.56 0.0 368.94 0.38 ; + END + END din0[35] + PIN din0[36] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 374.68 0.0 375.06 0.38 ; + END + END din0[36] + PIN din0[37] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 380.12 0.0 380.5 0.38 ; + END + END din0[37] + PIN din0[38] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 386.24 0.0 386.62 0.38 ; + END + END din0[38] + PIN din0[39] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 391.68 0.0 392.06 0.38 ; + END + END din0[39] + PIN din0[40] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 397.8 0.0 398.18 0.38 ; + END + END din0[40] + PIN din0[41] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 403.92 0.0 404.3 0.38 ; + END + END din0[41] + PIN din0[42] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 410.04 0.0 410.42 0.38 ; + END + END din0[42] + PIN din0[43] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 415.48 0.0 415.86 0.38 ; + END + END din0[43] + PIN din0[44] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 420.92 0.0 421.3 0.38 ; + END + END din0[44] + PIN din0[45] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 426.36 0.0 426.74 0.38 ; + END + END din0[45] + PIN din0[46] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 432.48 0.0 432.86 0.38 ; + END + END din0[46] + PIN din0[47] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 438.6 0.0 438.98 0.38 ; + END + END din0[47] + PIN din0[48] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 444.04 0.0 444.42 0.38 ; + END + END din0[48] + PIN din0[49] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 450.16 0.0 450.54 0.38 ; + END + END din0[49] + PIN din0[50] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 455.6 0.0 455.98 0.38 ; + END + END din0[50] + PIN din0[51] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 461.72 0.0 462.1 0.38 ; + END + END din0[51] + PIN din0[52] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 468.52 0.0 468.9 0.38 ; + END + END din0[52] + PIN din0[53] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 473.28 0.0 473.66 0.38 ; + END + END din0[53] + PIN din0[54] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 479.4 0.0 479.78 0.38 ; + END + END din0[54] + PIN din0[55] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 484.84 0.0 485.22 0.38 ; + END + END din0[55] + PIN din0[56] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 490.96 0.0 491.34 0.38 ; + END + END din0[56] + PIN din0[57] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 497.08 0.0 497.46 0.38 ; + END + END din0[57] + PIN din0[58] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 502.52 0.0 502.9 0.38 ; + END + END din0[58] + PIN din0[59] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 509.32 0.0 509.7 0.38 ; + END + END din0[59] + PIN din0[60] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 514.76 0.0 515.14 0.38 ; + END + END din0[60] + PIN din0[61] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 520.88 0.0 521.26 0.38 ; + END + END din0[61] + PIN din0[62] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 526.32 0.0 526.7 0.38 ; + END + END din0[62] + PIN din0[63] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 532.44 0.0 532.82 0.38 ; + END + END din0[63] + PIN din0[64] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 537.88 0.0 538.26 0.38 ; + END + END din0[64] + PIN addr0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 106.08 0.0 106.46 0.38 ; + END + END addr0[0] + PIN addr0[1] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 112.2 0.0 112.58 0.38 ; + END + END addr0[1] + PIN addr0[2] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 154.36 0.38 154.74 ; + END + END addr0[2] + PIN addr0[3] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 163.2 0.38 163.58 ; + END + END addr0[3] + PIN addr0[4] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 168.64 0.38 169.02 ; + END + END addr0[4] + PIN addr0[5] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 177.48 0.38 177.86 ; + END + END addr0[5] + PIN addr0[6] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 183.6 0.38 183.98 ; + END + END addr0[6] + PIN addr0[7] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 191.08 0.38 191.46 ; + END + END addr0[7] + PIN addr0[8] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 197.2 0.38 197.58 ; + END + END addr0[8] + PIN csb0 + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 51.68 0.38 52.06 ; + END + END csb0 + PIN web0 + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 59.84 0.38 60.22 ; + END + END web0 + PIN clk0 + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.0 53.72 0.38 54.1 ; + END + END clk0 + PIN wmask0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 117.64 0.0 118.02 0.38 ; + END + END wmask0[0] + PIN wmask0[1] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 123.76 0.0 124.14 0.38 ; + END + END wmask0[1] + PIN wmask0[2] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 129.88 0.0 130.26 0.38 ; + END + END wmask0[2] + PIN wmask0[3] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 134.64 0.0 135.02 0.38 ; + END + END wmask0[3] + PIN wmask0[4] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 141.44 0.0 141.82 0.38 ; + END + END wmask0[4] + PIN wmask0[5] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 146.2 0.0 146.58 0.38 ; + END + END wmask0[5] + PIN wmask0[6] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 153.0 0.0 153.38 0.38 ; + END + END wmask0[6] + PIN wmask0[7] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 157.76 0.0 158.14 0.38 ; + END + END wmask0[7] + PIN spare_wen0[0] + DIRECTION INPUT ; + PORT + LAYER met4 ; + RECT 543.32 0.0 543.7 0.38 ; + END + END spare_wen0[0] + PIN dout0[0] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 167.28 0.0 167.66 0.38 ; + END + END dout0[0] + PIN dout0[1] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 178.84 0.0 179.22 0.38 ; + END + END dout0[1] + PIN dout0[2] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 189.04 0.0 189.42 0.38 ; + END + END dout0[2] + PIN dout0[3] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 199.24 0.0 199.62 0.38 ; + END + END dout0[3] + PIN dout0[4] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 208.76 0.0 209.14 0.38 ; + END + END dout0[4] + PIN dout0[5] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 218.96 0.0 219.34 0.38 ; + END + END dout0[5] + PIN dout0[6] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 228.48 0.0 228.86 0.38 ; + END + END dout0[6] + PIN dout0[7] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 238.0 0.0 238.38 0.38 ; + END + END dout0[7] + PIN dout0[8] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 247.52 0.0 247.9 0.38 ; + END + END dout0[8] + PIN dout0[9] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 259.08 0.0 259.46 0.38 ; + END + END dout0[9] + PIN dout0[10] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 269.28 0.0 269.66 0.38 ; + END + END dout0[10] + PIN dout0[11] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 278.8 0.0 279.18 0.38 ; + END + END dout0[11] + PIN dout0[12] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 289.0 0.0 289.38 0.38 ; + END + END dout0[12] + PIN dout0[13] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 299.2 0.0 299.58 0.38 ; + END + END dout0[13] + PIN dout0[14] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 308.04 0.0 308.42 0.38 ; + END + END dout0[14] + PIN dout0[15] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 318.92 0.0 319.3 0.38 ; + END + END dout0[15] + PIN dout0[16] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 325.72 0.0 326.1 0.38 ; + END + END dout0[16] + PIN dout0[17] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 337.28 0.0 337.66 0.38 ; + END + END dout0[17] + PIN dout0[18] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 348.84 0.0 349.22 0.38 ; + END + END dout0[18] + PIN dout0[19] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 359.04 0.0 359.42 0.38 ; + END + END dout0[19] + PIN dout0[20] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 369.24 0.0 369.62 0.38 ; + END + END dout0[20] + PIN dout0[21] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 378.08 0.0 378.46 0.38 ; + END + END dout0[21] + PIN dout0[22] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 388.96 0.0 389.34 0.38 ; + END + END dout0[22] + PIN dout0[23] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 399.16 0.0 399.54 0.38 ; + END + END dout0[23] + PIN dout0[24] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 407.32 0.0 407.7 0.38 ; + END + END dout0[24] + PIN dout0[25] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 418.88 0.0 419.26 0.38 ; + END + END dout0[25] + PIN dout0[26] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 429.08 0.0 429.46 0.38 ; + END + END dout0[26] + PIN dout0[27] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 439.28 0.0 439.66 0.38 ; + END + END dout0[27] + PIN dout0[28] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 448.12 0.0 448.5 0.38 ; + END + END dout0[28] + PIN dout0[29] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 459.0 0.0 459.38 0.38 ; + END + END dout0[29] + PIN dout0[30] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 469.2 0.0 469.58 0.38 ; + END + END dout0[30] + PIN dout0[31] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 477.36 0.0 477.74 0.38 ; + END + END dout0[31] + PIN dout0[32] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 487.56 0.0 487.94 0.38 ; + END + END dout0[32] + PIN dout0[33] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 499.12 0.0 499.5 0.38 ; + END + END dout0[33] + PIN dout0[34] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 508.64 0.0 509.02 0.38 ; + END + END dout0[34] + PIN dout0[35] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 518.16 0.0 518.54 0.38 ; + END + END dout0[35] + PIN dout0[36] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 529.04 0.0 529.42 0.38 ; + END + END dout0[36] + PIN dout0[37] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 538.56 0.0 538.94 0.38 ; + END + END dout0[37] + PIN dout0[38] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 547.4 0.0 547.78 0.38 ; + END + END dout0[38] + PIN dout0[39] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 558.96 0.0 559.34 0.38 ; + END + END dout0[39] + PIN dout0[40] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 567.8 0.0 568.18 0.38 ; + END + END dout0[40] + PIN dout0[41] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 578.68 0.0 579.06 0.38 ; + END + END dout0[41] + PIN dout0[42] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 588.88 0.0 589.26 0.38 ; + END + END dout0[42] + PIN dout0[43] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 599.08 0.0 599.46 0.38 ; + END + END dout0[43] + PIN dout0[44] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 608.6 0.0 608.98 0.38 ; + END + END dout0[44] + PIN dout0[45] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 618.8 0.0 619.18 0.38 ; + END + END dout0[45] + PIN dout0[46] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 629.0 0.0 629.38 0.38 ; + END + END dout0[46] + PIN dout0[47] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 638.52 0.0 638.9 0.38 ; + END + END dout0[47] + PIN dout0[48] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 647.36 0.0 647.74 0.38 ; + END + END dout0[48] + PIN dout0[49] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 658.92 0.0 659.3 0.38 ; + END + END dout0[49] + PIN dout0[50] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 669.12 0.0 669.5 0.38 ; + END + END dout0[50] + PIN dout0[51] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 678.64 0.0 679.02 0.38 ; + END + END dout0[51] + PIN dout0[52] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 688.84 0.0 689.22 0.38 ; + END + END dout0[52] + PIN dout0[53] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 699.04 0.0 699.42 0.38 ; + END + END dout0[53] + PIN dout0[54] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 708.56 0.0 708.94 0.38 ; + END + END dout0[54] + PIN dout0[55] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 718.76 0.0 719.14 0.38 ; + END + END dout0[55] + PIN dout0[56] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 727.6 0.0 727.98 0.38 ; + END + END dout0[56] + PIN dout0[57] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 739.16 0.0 739.54 0.38 ; + END + END dout0[57] + PIN dout0[58] + DIRECTION OUTPUT ; + PORT + LAYER met4 ; + RECT 748.68 0.0 749.06 0.38 ; + END + END dout0[58] + PIN dout0[59] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 822.12 74.12 822.5 74.5 ; + END + END dout0[59] + PIN dout0[60] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 822.12 80.24 822.5 80.62 ; + END + END dout0[60] + PIN dout0[61] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 822.12 79.56 822.5 79.94 ; + END + END dout0[61] + PIN dout0[62] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 822.12 74.8 822.5 75.18 ; + END + END dout0[62] + PIN dout0[63] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 822.12 75.48 822.5 75.86 ; + END + END dout0[63] + PIN dout0[64] + DIRECTION OUTPUT ; + PORT + LAYER met3 ; + RECT 822.12 76.84 822.5 77.22 ; + END + END dout0[64] + PIN vpwr + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER met4 ; + RECT 1.36 1.36 3.1 334.94 ; + LAYER met3 ; + RECT 1.36 1.36 821.14 3.1 ; + LAYER met4 ; + RECT 819.4 1.36 821.14 334.94 ; + LAYER met3 ; + RECT 1.36 333.2 821.14 334.94 ; + END + END vpwr + PIN vgnd + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 4.76 4.76 817.74 6.5 ; + LAYER met3 ; + RECT 4.76 329.8 817.74 331.54 ; + LAYER met4 ; + RECT 816.0 4.76 817.74 331.54 ; + LAYER met4 ; + RECT 4.76 4.76 6.5 331.54 ; + END + END vgnd + OBS + LAYER met1 ; + RECT 0.62 0.62 821.88 334.32 ; + LAYER met2 ; + RECT 0.62 0.62 821.88 334.32 ; + LAYER met3 ; + RECT 0.98 153.76 821.88 155.34 ; + RECT 0.62 155.34 0.98 162.6 ; + RECT 0.62 164.18 0.98 168.04 ; + RECT 0.62 169.62 0.98 176.88 ; + RECT 0.62 178.46 0.98 183.0 ; + RECT 0.62 184.58 0.98 190.48 ; + RECT 0.62 192.06 0.98 196.6 ; + RECT 0.62 60.82 0.98 153.76 ; + RECT 0.62 52.66 0.98 53.12 ; + RECT 0.62 54.7 0.98 59.24 ; + RECT 0.98 73.52 821.52 75.1 ; + RECT 0.98 75.1 821.52 153.76 ; + RECT 821.52 81.22 821.88 153.76 ; + RECT 821.52 77.82 821.88 78.96 ; + RECT 0.62 0.62 0.76 0.76 ; + RECT 0.62 0.76 0.76 3.7 ; + RECT 0.62 3.7 0.76 51.08 ; + RECT 0.76 0.62 0.98 0.76 ; + RECT 0.76 3.7 0.98 51.08 ; + RECT 0.98 0.62 821.52 0.76 ; + RECT 821.52 0.62 821.74 0.76 ; + RECT 821.52 3.7 821.74 73.52 ; + RECT 821.74 0.62 821.88 0.76 ; + RECT 821.74 0.76 821.88 3.7 ; + RECT 821.74 3.7 821.88 73.52 ; + RECT 821.74 155.34 821.88 332.6 ; + RECT 821.74 332.6 821.88 334.32 ; + RECT 0.62 198.18 0.76 332.6 ; + RECT 0.62 332.6 0.76 334.32 ; + RECT 0.76 198.18 0.98 332.6 ; + RECT 0.98 3.7 4.16 4.16 ; + RECT 0.98 4.16 4.16 7.1 ; + RECT 0.98 7.1 4.16 73.52 ; + RECT 4.16 3.7 818.34 4.16 ; + RECT 4.16 7.1 818.34 73.52 ; + RECT 818.34 3.7 821.52 4.16 ; + RECT 818.34 4.16 821.52 7.1 ; + RECT 818.34 7.1 821.52 73.52 ; + RECT 0.98 155.34 4.16 329.2 ; + RECT 0.98 329.2 4.16 332.14 ; + RECT 0.98 332.14 4.16 332.6 ; + RECT 4.16 155.34 818.34 329.2 ; + RECT 4.16 332.14 818.34 332.6 ; + RECT 818.34 155.34 821.74 329.2 ; + RECT 818.34 329.2 821.74 332.14 ; + RECT 818.34 332.14 821.74 332.6 ; + LAYER met4 ; + RECT 163.28 0.98 164.86 334.32 ; + RECT 171.66 0.62 175.52 0.98 ; + RECT 182.54 0.62 187.08 0.98 ; + RECT 200.9 0.62 204.08 0.98 ; + RECT 212.46 0.62 215.64 0.98 ; + RECT 230.14 0.62 234.0 0.98 ; + RECT 241.02 0.62 245.56 0.98 ; + RECT 253.26 0.62 257.12 0.98 ; + RECT 270.94 0.62 274.12 0.98 ; + RECT 282.5 0.62 285.68 0.98 ; + RECT 294.06 0.62 297.92 0.98 ; + RECT 311.06 0.62 315.6 0.98 ; + RECT 328.74 0.62 332.6 0.98 ; + RECT 340.98 0.62 344.16 0.98 ; + RECT 352.54 0.62 356.4 0.98 ; + RECT 363.42 0.62 367.96 0.98 ; + RECT 381.1 0.62 385.64 0.98 ; + RECT 392.66 0.62 397.2 0.98 ; + RECT 411.02 0.62 414.88 0.98 ; + RECT 421.9 0.62 425.76 0.98 ; + RECT 433.46 0.62 438.0 0.98 ; + RECT 451.14 0.62 455.0 0.98 ; + RECT 462.7 0.62 467.92 0.98 ; + RECT 480.38 0.62 484.24 0.98 ; + RECT 491.94 0.62 496.48 0.98 ; + RECT 510.3 0.62 514.16 0.98 ; + RECT 521.86 0.62 525.72 0.98 ; + RECT 533.42 0.62 537.28 0.98 ; + RECT 107.06 0.62 111.6 0.98 ; + RECT 113.18 0.62 117.04 0.98 ; + RECT 118.62 0.62 123.16 0.98 ; + RECT 124.74 0.62 129.28 0.98 ; + RECT 130.86 0.62 134.04 0.98 ; + RECT 135.62 0.62 140.84 0.98 ; + RECT 142.42 0.62 145.6 0.98 ; + RECT 147.18 0.62 152.4 0.98 ; + RECT 153.98 0.62 157.16 0.98 ; + RECT 158.74 0.62 163.28 0.98 ; + RECT 164.86 0.62 166.68 0.98 ; + RECT 168.26 0.62 170.08 0.98 ; + RECT 177.1 0.62 178.24 0.98 ; + RECT 179.82 0.62 180.96 0.98 ; + RECT 190.02 0.62 192.52 0.98 ; + RECT 194.1 0.62 198.64 0.98 ; + RECT 205.66 0.62 208.16 0.98 ; + RECT 209.74 0.62 210.88 0.98 ; + RECT 217.22 0.62 218.36 0.98 ; + RECT 219.94 0.62 222.44 0.98 ; + RECT 224.02 0.62 227.88 0.98 ; + RECT 235.58 0.62 237.4 0.98 ; + RECT 238.98 0.62 239.44 0.98 ; + RECT 248.5 0.62 251.68 0.98 ; + RECT 260.06 0.62 263.24 0.98 ; + RECT 264.82 0.62 268.68 0.98 ; + RECT 275.7 0.62 278.2 0.98 ; + RECT 279.78 0.62 280.92 0.98 ; + RECT 287.26 0.62 288.4 0.98 ; + RECT 289.98 0.62 292.48 0.98 ; + RECT 300.18 0.62 304.04 0.98 ; + RECT 305.62 0.62 307.44 0.98 ; + RECT 309.02 0.62 309.48 0.98 ; + RECT 317.18 0.62 318.32 0.98 ; + RECT 319.9 0.62 321.04 0.98 ; + RECT 322.62 0.62 325.12 0.98 ; + RECT 326.7 0.62 327.16 0.98 ; + RECT 334.18 0.62 336.68 0.98 ; + RECT 338.26 0.62 339.4 0.98 ; + RECT 345.74 0.62 348.24 0.98 ; + RECT 349.82 0.62 350.96 0.98 ; + RECT 357.98 0.62 358.44 0.98 ; + RECT 360.02 0.62 361.84 0.98 ; + RECT 370.22 0.62 374.08 0.98 ; + RECT 375.66 0.62 377.48 0.98 ; + RECT 379.06 0.62 379.52 0.98 ; + RECT 387.22 0.62 388.36 0.98 ; + RECT 389.94 0.62 391.08 0.98 ; + RECT 400.14 0.62 403.32 0.98 ; + RECT 404.9 0.62 406.72 0.98 ; + RECT 408.3 0.62 409.44 0.98 ; + RECT 416.46 0.62 418.28 0.98 ; + RECT 419.86 0.62 420.32 0.98 ; + RECT 427.34 0.62 428.48 0.98 ; + RECT 430.06 0.62 431.88 0.98 ; + RECT 440.26 0.62 443.44 0.98 ; + RECT 445.02 0.62 447.52 0.98 ; + RECT 449.1 0.62 449.56 0.98 ; + RECT 456.58 0.62 458.4 0.98 ; + RECT 459.98 0.62 461.12 0.98 ; + RECT 470.18 0.62 472.68 0.98 ; + RECT 474.26 0.62 476.76 0.98 ; + RECT 478.34 0.62 478.8 0.98 ; + RECT 485.82 0.62 486.96 0.98 ; + RECT 488.54 0.62 490.36 0.98 ; + RECT 498.06 0.62 498.52 0.98 ; + RECT 500.1 0.62 501.92 0.98 ; + RECT 503.5 0.62 508.04 0.98 ; + RECT 515.74 0.62 517.56 0.98 ; + RECT 519.14 0.62 520.28 0.98 ; + RECT 527.3 0.62 528.44 0.98 ; + RECT 530.02 0.62 531.84 0.98 ; + RECT 539.54 0.62 542.72 0.98 ; + RECT 544.3 0.62 546.8 0.98 ; + RECT 548.38 0.62 558.36 0.98 ; + RECT 559.94 0.62 567.2 0.98 ; + RECT 568.78 0.62 578.08 0.98 ; + RECT 579.66 0.62 588.28 0.98 ; + RECT 589.86 0.62 598.48 0.98 ; + RECT 600.06 0.62 608.0 0.98 ; + RECT 609.58 0.62 618.2 0.98 ; + RECT 619.78 0.62 628.4 0.98 ; + RECT 629.98 0.62 637.92 0.98 ; + RECT 639.5 0.62 646.76 0.98 ; + RECT 648.34 0.62 658.32 0.98 ; + RECT 659.9 0.62 668.52 0.98 ; + RECT 670.1 0.62 678.04 0.98 ; + RECT 679.62 0.62 688.24 0.98 ; + RECT 689.82 0.62 698.44 0.98 ; + RECT 700.02 0.62 707.96 0.98 ; + RECT 709.54 0.62 718.16 0.98 ; + RECT 719.74 0.62 727.0 0.98 ; + RECT 728.58 0.62 738.56 0.98 ; + RECT 740.14 0.62 748.08 0.98 ; + RECT 0.62 0.98 0.76 334.32 ; + RECT 0.62 0.62 0.76 0.76 ; + RECT 0.62 0.76 0.76 0.98 ; + RECT 0.76 0.62 3.7 0.76 ; + RECT 3.7 0.62 105.48 0.76 ; + RECT 3.7 0.76 105.48 0.98 ; + RECT 821.74 0.98 821.88 334.32 ; + RECT 749.66 0.62 818.8 0.76 ; + RECT 749.66 0.76 818.8 0.98 ; + RECT 818.8 0.62 821.74 0.76 ; + RECT 821.74 0.62 821.88 0.76 ; + RECT 821.74 0.76 821.88 0.98 ; + RECT 164.86 0.98 815.4 4.16 ; + RECT 164.86 4.16 815.4 332.14 ; + RECT 164.86 332.14 815.4 334.32 ; + RECT 815.4 0.98 818.34 4.16 ; + RECT 815.4 332.14 818.34 334.32 ; + RECT 818.34 0.98 818.8 4.16 ; + RECT 818.34 4.16 818.8 332.14 ; + RECT 818.34 332.14 818.8 334.32 ; + RECT 3.7 0.98 4.16 4.16 ; + RECT 3.7 4.16 4.16 332.14 ; + RECT 3.7 332.14 4.16 334.32 ; + RECT 4.16 0.98 7.1 4.16 ; + RECT 4.16 332.14 7.1 334.32 ; + RECT 7.1 0.98 163.28 4.16 ; + RECT 7.1 4.16 163.28 332.14 ; + RECT 7.1 332.14 163.28 334.32 ; + END +END sram_1rw0r0w_64_512_sky130 +END LIBRARY
diff --git a/verilog/rtl/sram_1rw0r0w_32_1024_sky130.v b/verilog/rtl/sram_1rw0r0w_32_1024_sky130.v new file mode 100644 index 0000000..2b4de78 --- /dev/null +++ b/verilog/rtl/sram_1rw0r0w_32_1024_sky130.v
@@ -0,0 +1,84 @@ +// OpenRAM SRAM model +// Words: 1024 +// Word size: 32 +// Write size: 8 + +module sram_1rw0r0w_32_1024_sky130( +`ifdef USE_POWER_PINS + vccd1, + vssd1, +`endif +// Port 0: RW + clk0,csb0,web0,wmask0,addr0,din0,dout0 + ); + + parameter NUM_WMASKS = 4 ; + parameter DATA_WIDTH = 32 ; + parameter ADDR_WIDTH = 10 ; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + // FIXME: This delay is arbitrary. + parameter DELAY = 3 ; + parameter VERBOSE = 1 ; //Set to 0 to only display warnings + parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary + +`ifdef USE_POWER_PINS + inout vccd1 + inout vssd1; +`endif + input clk0; // clock + input csb0; // active low chip select + input web0; // active low write control + input [NUM_WMASKS-1:0] wmask0; // write mask + input [ADDR_WIDTH-1:0] addr0; + input [DATA_WIDTH-1:0] din0; + output [DATA_WIDTH-1:0] dout0; + + reg csb0_reg; + reg web0_reg; + reg [NUM_WMASKS-1:0] wmask0_reg; + reg [ADDR_WIDTH-1:0] addr0_reg; + reg [DATA_WIDTH-1:0] din0_reg; + reg [DATA_WIDTH-1:0] dout0; + + // All inputs are registers + always @(posedge clk0) + begin + csb0_reg = csb0; + web0_reg = web0; + wmask0_reg = wmask0; + addr0_reg = addr0; + din0_reg = din0; + #(T_HOLD) dout0 = 32'bx; + if ( !csb0_reg && web0_reg && VERBOSE ) + $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]); + if ( !csb0_reg && !web0_reg && VERBOSE ) + $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg); + end + +reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; + + // Memory Write Block Port 0 + // Write Operation : When web0 = 0, csb0 = 0 + always @ (negedge clk0) + begin : MEM_WRITE0 + if ( !csb0_reg && !web0_reg ) begin + if (wmask0_reg[0]) + mem[addr0_reg][7:0] = din0_reg[7:0]; + if (wmask0_reg[1]) + mem[addr0_reg][15:8] = din0_reg[15:8]; + if (wmask0_reg[2]) + mem[addr0_reg][23:16] = din0_reg[23:16]; + if (wmask0_reg[3]) + mem[addr0_reg][31:24] = din0_reg[31:24]; + end + end + + // Memory Read Block Port 0 + // Read Operation : When web0 = 1, csb0 = 0 + always @ (negedge clk0) + begin : MEM_READ0 + if (!csb0_reg && web0_reg) + dout0 <= #(DELAY) mem[addr0_reg]; + end + +endmodule
diff --git a/verilog/rtl/sram_1rw0r0w_32_256_sky130.v b/verilog/rtl/sram_1rw0r0w_32_256_sky130.v new file mode 100644 index 0000000..8af0030 --- /dev/null +++ b/verilog/rtl/sram_1rw0r0w_32_256_sky130.v
@@ -0,0 +1,84 @@ +// OpenRAM SRAM model +// Words: 256 +// Word size: 32 +// Write size: 8 + +module sram_1rw0r0w_32_256_sky130( +`ifdef USE_POWER_PINS + vccd1, + vssd1, +`endif +// Port 0: RW + clk0,csb0,web0,wmask0,addr0,din0,dout0 + ); + + parameter NUM_WMASKS = 4 ; + parameter DATA_WIDTH = 32 ; + parameter ADDR_WIDTH = 8 ; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + // FIXME: This delay is arbitrary. + parameter DELAY = 3 ; + parameter VERBOSE = 1 ; //Set to 0 to only display warnings + parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary + +`ifdef USE_POWER_PINS + inout vccd1; + inout vssd1; +`endif + input clk0; // clock + input csb0; // active low chip select + input web0; // active low write control + input [NUM_WMASKS-1:0] wmask0; // write mask + input [ADDR_WIDTH-1:0] addr0; + input [DATA_WIDTH-1:0] din0; + output [DATA_WIDTH-1:0] dout0; + + reg csb0_reg; + reg web0_reg; + reg [NUM_WMASKS-1:0] wmask0_reg; + reg [ADDR_WIDTH-1:0] addr0_reg; + reg [DATA_WIDTH-1:0] din0_reg; + reg [DATA_WIDTH-1:0] dout0; + + // All inputs are registers + always @(posedge clk0) + begin + csb0_reg = csb0; + web0_reg = web0; + wmask0_reg = wmask0; + addr0_reg = addr0; + din0_reg = din0; + #(T_HOLD) dout0 = 32'bx; + if ( !csb0_reg && web0_reg && VERBOSE ) + $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]); + if ( !csb0_reg && !web0_reg && VERBOSE ) + $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg); + end + +reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; + + // Memory Write Block Port 0 + // Write Operation : When web0 = 0, csb0 = 0 + always @ (negedge clk0) + begin : MEM_WRITE0 + if ( !csb0_reg && !web0_reg ) begin + if (wmask0_reg[0]) + mem[addr0_reg][7:0] = din0_reg[7:0]; + if (wmask0_reg[1]) + mem[addr0_reg][15:8] = din0_reg[15:8]; + if (wmask0_reg[2]) + mem[addr0_reg][23:16] = din0_reg[23:16]; + if (wmask0_reg[3]) + mem[addr0_reg][31:24] = din0_reg[31:24]; + end + end + + // Memory Read Block Port 0 + // Read Operation : When web0 = 1, csb0 = 0 + always @ (negedge clk0) + begin : MEM_READ0 + if (!csb0_reg && web0_reg) + dout0 <= #(DELAY) mem[addr0_reg]; + end + +endmodule
diff --git a/verilog/rtl/sram_1rw0r0w_32_512_sky130.v b/verilog/rtl/sram_1rw0r0w_32_512_sky130.v new file mode 100644 index 0000000..a406b4f --- /dev/null +++ b/verilog/rtl/sram_1rw0r0w_32_512_sky130.v
@@ -0,0 +1,84 @@ +// OpenRAM SRAM model +// Words: 512 +// Word size: 32 +// Write size: 8 + +module sram_1rw0r0w_32_512_sky130( +`ifdef USE_POWER_PINS + vccd1, + vssd1, +`endif +// Port 0: RW + clk0,csb0,web0,wmask0,addr0,din0,dout0 + ); + + parameter NUM_WMASKS = 4 ; + parameter DATA_WIDTH = 32 ; + parameter ADDR_WIDTH = 9 ; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + // FIXME: This delay is arbitrary. + parameter DELAY = 3 ; + parameter VERBOSE = 1 ; //Set to 0 to only display warnings + parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary + +`ifdef USE_POWER_PINS + inout vccd1; + inout vssd1; +`endif + input clk0; // clock + input csb0; // active low chip select + input web0; // active low write control + input [NUM_WMASKS-1:0] wmask0; // write mask + input [ADDR_WIDTH-1:0] addr0; + input [DATA_WIDTH-1:0] din0; + output [DATA_WIDTH-1:0] dout0; + + reg csb0_reg; + reg web0_reg; + reg [NUM_WMASKS-1:0] wmask0_reg; + reg [ADDR_WIDTH-1:0] addr0_reg; + reg [DATA_WIDTH-1:0] din0_reg; + reg [DATA_WIDTH-1:0] dout0; + + // All inputs are registers + always @(posedge clk0) + begin + csb0_reg = csb0; + web0_reg = web0; + wmask0_reg = wmask0; + addr0_reg = addr0; + din0_reg = din0; + #(T_HOLD) dout0 = 32'bx; + if ( !csb0_reg && web0_reg && VERBOSE ) + $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]); + if ( !csb0_reg && !web0_reg && VERBOSE ) + $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg); + end + +reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; + + // Memory Write Block Port 0 + // Write Operation : When web0 = 0, csb0 = 0 + always @ (negedge clk0) + begin : MEM_WRITE0 + if ( !csb0_reg && !web0_reg ) begin + if (wmask0_reg[0]) + mem[addr0_reg][7:0] = din0_reg[7:0]; + if (wmask0_reg[1]) + mem[addr0_reg][15:8] = din0_reg[15:8]; + if (wmask0_reg[2]) + mem[addr0_reg][23:16] = din0_reg[23:16]; + if (wmask0_reg[3]) + mem[addr0_reg][31:24] = din0_reg[31:24]; + end + end + + // Memory Read Block Port 0 + // Read Operation : When web0 = 1, csb0 = 0 + always @ (negedge clk0) + begin : MEM_READ0 + if (!csb0_reg && web0_reg) + dout0 <= #(DELAY) mem[addr0_reg]; + end + +endmodule
diff --git a/verilog/rtl/sram_1rw0r0w_64_512_sky130.v b/verilog/rtl/sram_1rw0r0w_64_512_sky130.v new file mode 100644 index 0000000..1fabb08 --- /dev/null +++ b/verilog/rtl/sram_1rw0r0w_64_512_sky130.v
@@ -0,0 +1,92 @@ +// OpenRAM SRAM model +// Words: 512 +// Word size: 64 +// Write size: 8 + +module sram_1rw0r0w_64_512_sky130( +`ifdef USE_POWER_PINS + vccd1, + vssd1, +`endif +// Port 0: RW + clk0,csb0,web0,wmask0,addr0,din0,dout0 + ); + + parameter NUM_WMASKS = 8 ; + parameter DATA_WIDTH = 64 ; + parameter ADDR_WIDTH = 9 ; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + // FIXME: This delay is arbitrary. + parameter DELAY = 3 ; + parameter VERBOSE = 1 ; //Set to 0 to only display warnings + parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary + +`ifdef USE_POWER_PINS + inout vccd1; + inout vssd1; +`endif + input clk0; // clock + input csb0; // active low chip select + input web0; // active low write control + input [NUM_WMASKS-1:0] wmask0; // write mask + input [ADDR_WIDTH-1:0] addr0; + input [DATA_WIDTH-1:0] din0; + output [DATA_WIDTH-1:0] dout0; + + reg csb0_reg; + reg web0_reg; + reg [NUM_WMASKS-1:0] wmask0_reg; + reg [ADDR_WIDTH-1:0] addr0_reg; + reg [DATA_WIDTH-1:0] din0_reg; + reg [DATA_WIDTH-1:0] dout0; + + // All inputs are registers + always @(posedge clk0) + begin + csb0_reg = csb0; + web0_reg = web0; + wmask0_reg = wmask0; + addr0_reg = addr0; + din0_reg = din0; + #(T_HOLD) dout0 = 64'bx; + if ( !csb0_reg && web0_reg && VERBOSE ) + $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]); + if ( !csb0_reg && !web0_reg && VERBOSE ) + $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg); + end + +reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; + + // Memory Write Block Port 0 + // Write Operation : When web0 = 0, csb0 = 0 + always @ (negedge clk0) + begin : MEM_WRITE0 + if ( !csb0_reg && !web0_reg ) begin + if (wmask0_reg[0]) + mem[addr0_reg][7:0] = din0_reg[7:0]; + if (wmask0_reg[1]) + mem[addr0_reg][15:8] = din0_reg[15:8]; + if (wmask0_reg[2]) + mem[addr0_reg][23:16] = din0_reg[23:16]; + if (wmask0_reg[3]) + mem[addr0_reg][31:24] = din0_reg[31:24]; + if (wmask0_reg[4]) + mem[addr0_reg][39:32] = din0_reg[39:32]; + if (wmask0_reg[5]) + mem[addr0_reg][47:40] = din0_reg[47:40]; + if (wmask0_reg[6]) + mem[addr0_reg][55:48] = din0_reg[55:48]; + if (wmask0_reg[7]) + mem[addr0_reg][63:56] = din0_reg[63:56]; + end + end + + // Memory Read Block Port 0 + // Read Operation : When web0 = 1, csb0 = 0 + always @ (negedge clk0) + begin : MEM_READ0 + if (!csb0_reg && web0_reg) + dout0 <= #(DELAY) mem[addr0_reg]; + end + +endmodule