Debugged la_test clock error
diff --git a/verilog/dv/la_test/la_test.c b/verilog/dv/la_test/la_test.c
index 16a8284..0b78219 100644
--- a/verilog/dv/la_test/la_test.c
+++ b/verilog/dv/la_test/la_test.c
@@ -85,9 +85,12 @@
{
reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
// connect to housekeeping SPI
- // Configure Pin 22 as user output
- // Observe counter value in the testbench
- reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+
+ // This is to signal when the code is ready to the test bench
+ reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // To start, set pin 0 to 1
+ reg_mprj_datal = 0x000000001;
// Configure LA probes as outputs from the cpu
reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
@@ -98,12 +101,14 @@
reg_la1_data = 0x00000000;
reg_la2_data = 0x00000000;
reg_la3_data = 0x00000000;
-
- // On success, set pin 22 to 1
- reg_mprj_datal = 0xFFFFFFFF;
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
+ reg_la0_data = 0x10101111;
+ reg_la1_data = 0x20202222;
+ reg_la2_data = 0x30303333;
+ reg_la3_data = 0x40404444;
+ reg_la0_data = 0x00000000;
+ reg_la1_data = 0x00000000;
+ reg_la2_data = 0x00000000;
+ reg_la3_data = 0x00000000;
union packet p;
p.bf.rst = 0;
@@ -127,16 +132,25 @@
p.wf.word2 = reg_la2_data;
p.wf.word3 = reg_la3_data;
- /* p.bf.addr0 = 0x000000001; */
- /* p.bf.din0 = 0xDEADBEEF; */
- /* p.bf.csb0 = 0; */
- /* p.bf.web0 = 0; */
- /* p.bf.csb1 = 1; */
- /* p.bf.web1 = 1; */
- /* reg_la0_data = p.wf.word0; */
- /* reg_la1_data = p.wf.word1; */
- /* reg_la2_data = p.wf.word2; */
- /* reg_la3_data = p.wf.word3; */
+ p.bf.addr0 = 0x000000001;
+ p.bf.din0 = 0xDEADBEEF;
+ p.bf.csb0 = 0;
+ p.bf.web0 = 0;
+ p.bf.csb1 = 1;
+ p.bf.web1 = 1;
+ reg_la0_data = p.wf.word0;
+ reg_la1_data = p.wf.word1;
+ reg_la2_data = p.wf.word2;
+ reg_la3_data = p.wf.word3;
+
+
+ // On end, set pin 0 to 0
+ reg_mprj_datal = 0x000000000;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
}
diff --git a/verilog/dv/la_test/la_test_tb.v b/verilog/dv/la_test/la_test_tb.v
index 4e1a6bd..97b1f10 100644
--- a/verilog/dv/la_test/la_test_tb.v
+++ b/verilog/dv/la_test/la_test_tb.v
@@ -30,13 +30,7 @@
wire gpio;
wire [37:0] mprj_io;
- wire mprj_io_22;
-
- assign mprj_io_22 = mprj_io[22];
- // assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
-
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
- // assign mprj_io[3] = 1'b1;
+ wire mprj_io_0 = mprj_io[0];
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
@@ -48,11 +42,12 @@
clock = 0;
end
- wire gpio_clk = 1'b0;
+ wire gpio_clk = 1'b1;
wire gpio_scan = 1'b0;
wire gpio_sram_load = 1'b0;
wire global_csb = 1'b1;
wire gpio_in = 1'b0;
+ wire gpio_out = mprj_io[22];
assign mprj_io[15] = 1'b0; // in_select
assign mprj_io[16] = 1'b1; // resetn
@@ -63,26 +58,31 @@
assign mprj_io[21] = global_csb;
initial begin
- //#170000;
+
+ wait(mprj_io_0 == 1'b1);
+ $display($time, " Saw bit 0: VCD starting");
$dumpfile("la_test.vcd");
$dumpvars(0, la_test_tb);
- // #200000 $display("TIMEOUT");
- // $finish;
+ wait(mprj_io_0 == 1'b0);
+ $display($time, " Saw bit 0: VCD stopping");
+ $finish;
- end
+ end // initial begin
+
+ initial begin
+ $dumpfile("foo.vcd");
+ $dumpvars(0, la_test_tb);
+
+ #500000
+ $display("Timeout");
+ $finish;
+ end
- initial begin
- // Observe Output pin 22
- wait(mprj_io_22 == 8'h01);
- $display("Saw bit 22");
- $finish;
- end
-
initial begin
RSTB <= 1'b0;
CSB <= 1'b1; // Force CSB high
@@ -107,10 +107,6 @@
power4 <= 1'b1;
end
- always @(mprj_io) begin
- //#1 $display("MPRJ-IO state = %b ", mprj_io[22]);
- end
-
wire flash_csb;
wire flash_clk;
wire flash_io0;
