Fix wire width output from SRAM11

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index a58195e..d74db1e 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -454,7 +454,7 @@
       .dout0  (temp_sram11_dout0)
      );
    
-   wire [`DATA_SIZE-1:0] temp_sram11_dout0;
+   wire [63:0] temp_sram11_dout0;
    assign sram11_dout1 = 0;
    assign sram11_dout0 = {temp_sram11_dout0[64:33], temp_sram11_dout[15:0]};