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foss-eda-tools
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third_party
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shuttle
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sky130
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mpw-002
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slot-009
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7f4fa4bd9643ab7fb33c124a7f8be9b2e9a0a1ba
commit
7f4fa4bd9643ab7fb33c124a7f8be9b2e9a0a1ba
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log
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author
mrg <mrg@ucsc.edu>
Mon Jun 14 13:30:20 2021 -0700
committer
mrg <mrg@ucsc.edu>
Mon Jun 14 13:30:20 2021 -0700
tree
beeb5aca3d232f3a7ec1a88abfe0f14a5e26e8f4
parent
2f1a8ef2cebf784aa74ff39015e9fa4bd0d4f25b
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diff
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Fix wire width output from SRAM11
verilog/rtl/user_project_wrapper.v
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diff
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1 file changed
tree: beeb5aca3d232f3a7ec1a88abfe0f14a5e26e8f4
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
single_port/
spi/
verilog/
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