Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main
diff --git a/verilog/rtl/openram_testchip_tb.v b/verilog/rtl/openram_testchip_tb.v
index 4b43c1d..c7803a0 100644
--- a/verilog/rtl/openram_testchip_tb.v
+++ b/verilog/rtl/openram_testchip_tb.v
@@ -6,160 +6,365 @@
`timescale 1ns/1ns
+`include "openram_testchip.v"
+`include "openram_defines.v"
`include "sky130_sram_1kbyte_1rw1r_32x256_8.v"
+`include "sky130_sram_1kbyte_1rw1r_8x1024_8.v"
+`include "sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "sky130_sram_4kbyte_1rw1r_32x1024_8.v"
+`include "sky130_sram_8kbyte_1rw1r_32x2048_8.v"
`include "sram_1rw0r0w_32_256_sky130.v"
`include "sram_1rw0r0w_32_512_sky130.v"
`include "sram_1rw0r0w_32_1024_sky130.v"
-//`include "sram_1rw0r0w_64_512_sky130.v"
-`include "openram_testchip.v"
+`include "sram_1rw0r0w_64_512_sky130.v"
module test_chip_tb;
- reg la_clk;
- reg gpio_clk;
- reg la_sram_clk;
- reg gpio_sram_clk;
reg reset;
- reg la_in_load;
- reg gpio_scan;
- reg la_sram_load;
- reg gpio_sram_load;
- reg [111:0] la_bits;
- reg gpio_bit;
reg in_select;
- wire [31:0] sram0_rw_in;
- wire [31:0] sram0_ro_in;
- wire [31:0] sram1_rw_in;
- wire [31:0] sram1_ro_in;
- wire [31:0] sram2_rw_in;
- wire [31:0] sram3_rw_in;
- wire [31:0] sram4_rw_in;
- //wire [63:0] sram5_rw_in;
- wire [54:0] sram0_connections;
- wire [54:0] sram1_connections;
- wire [47:0] sram2_connections;
- wire [45:0] sram3_connections;
- wire [46:0] sram4_connections;
- //wire [82:0] sram5_connections;
+ reg la_clk;
+ reg la_sram_clk;
+ reg la_in_load;
+ reg la_sram_load;
+ reg [`TOTAL_SIZE-1:0] la_data_in;
+ reg gpio_clk;
+ reg gpio_in;
+ reg gpio_sram_clk;
+ reg gpio_scan;
+ reg gpio_sram_load;
+
+ wire [`ADDR_SIZE-1:0] left_addr0;
+ wire [`DATA_SIZE-1:0] left_din0;
+ wire left_web0;
+ wire [`WMASK_SIZE-1:0] left_wmask0;
+ wire [`ADDR_SIZE-1:0] left_addr1;
+ wire [`DATA_SIZE-1:0] left_din1;
+ wire left_web1;
+ wire [`WMASK_SIZE-1:0] left_wmask1;
+ // One CSB for each SRAM
+ wire [`MAX_CHIPS-1:0] left_csb0;
+ wire [`MAX_CHIPS-1:0] left_csb1;
+
+ wire [`ADDR_SIZE-1:0] right_addr0;
+ wire [`DATA_SIZE-1:0] right_din0;
+ wire right_web0;
+ wire [`WMASK_SIZE-1:0] right_wmask0;
+ wire [`MAX_CHIPS-1:0] right_csb0;
+
+ wire [31:0] sram0_dout0;
+ wire [31:0] sram0_dout1;
+ wire [31:0] sram1_dout0;
+ wire [31:0] sram1_dout1;
+ wire [31:0] sram2_dout0;
+ wire [31:0] sram2_dout1;
+ wire [31:0] sram3_dout0;
+ wire [31:0] sram3_dout1;
+ wire [31:0] sram4_dout0;
+ wire [31:0] sram4_dout1;
+ wire [31:0] sram5_dout0;
+ wire [31:0] sram5_dout1;
+ wire [31:0] sram6_dout0;
+ wire [31:0] sram6_dout1;
+ wire [31:0] sram7_dout0;
+ wire [31:0] sram7_dout1;
+ wire [31:0] sram8_dout0;
+ wire [31:0] sram8_dout1;
+ wire [31:0] sram9_dout0;
+ wire [31:0] sram9_dout1;
+ wire [31:0] sram10_dout0;
+ wire [31:0] sram10_dout1;
+ wire [31:0] sram11_dout0;
+ wire [31:0] sram11_dout1;
+ wire [31:0] sram12_dout0;
+ wire [31:0] sram12_dout1;
+ wire [31:0] sram13_dout0;
+ wire [31:0] sram13_dout1;
+ wire [31:0] sram14_dout0;
+ wire [31:0] sram14_dout1;
+
wire sram0_clk;
wire sram1_clk;
wire sram2_clk;
wire sram3_clk;
wire sram4_clk;
- //wire sram5_clk;
- wire [31:0] la_data0;
- wire [31:0] la_data1;
- wire gpio_data0;
- wire gpio_data1;
+ wire sram5_clk;
+ wire sram6_clk;
+ wire sram7_clk;
+ wire sram8_clk;
+ wire sram9_clk;
+ wire sram10_clk;
+ wire sram11_clk;
+ wire sram12_clk;
+ wire sram13_clk;
+ wire sram14_clk;
+ wire sram15_clk;
openram_testchip CONTROL_LOGIC(
- .la_clk(la_clk),
- .gpio_clk(gpio_clk),
- .la_sram_clk(la_sram_clk),
- .gpio_sram_clk(gpio_sram_clk),
.reset(reset),
- .la_in_load(la_in_load),
- .gpio_scan(gpio_scan),
- .la_sram_load(la_sram_load),
- .gpio_sram_load(gpio_sram_load),
- .la_bits(la_bits),
- .gpio_bit(gpio_bit),
.in_select(in_select),
- .sram0_rw_in(sram0_rw_in),
- .sram0_ro_in(sram0_ro_in),
- .sram1_rw_in(sram1_rw_in),
- .sram1_ro_in(sram1_ro_in),
- .sram2_rw_in(sram2_rw_in),
- .sram3_rw_in(sram3_rw_in),
- .sram4_rw_in(sram4_rw_in),
- //.sram5_rw_in(sram5_rw_out),
- .sram0_connections(sram0_connections),
- .sram1_connections(sram1_connections),
- .sram2_connections(sram2_connections),
- .sram3_connections(sram3_connections),
- .sram4_connections(sram4_connections),
- //.sram5_connections(sram5_connections),
+ .la_clk(la_clk),
+ .la_sram_clk(la_sram_clk),
+ .la_in_load(la_in_load),
+ .la_data_in(la_data_in),
+ .la_sram_load(la_sram_load),
+ .gpio_clk(gpio_clk),
+ .gpio_in(gpio_in),
+ .gpio_sram_clk(gpio_sram_clk),
+ .gpio_scan(gpio_scan),
+ .gpio_sram_load(gpio_sram_load),
+ .sram0_dout0(sram0_dout0),
+ .sram0_dout1(sram0_dout1),
+ .sram1_dout0(sram1_dout0),
+ .sram1_dout1(sram1_dout1),
+ .sram2_dout0(sram2_dout0),
+ .sram2_dout1(sram2_dout1),
+ .sram3_dout0(sram3_dout0),
+ .sram3_dout1(sram3_dout1),
+ .sram4_dout0(sram4_dout0),
+ .sram4_dout1(sram4_dout1),
+ .sram5_dout0(sram5_dout0),
+ .sram5_dout1(sram5_dout1),
+ .sram6_dout0(sram6_dout0),
+ .sram6_dout1(sram6_dout1),
+ .sram7_dout0(sram7_dout0),
+ .sram7_dout1(sram7_dout1),
+ .sram8_dout0(sram8_dout0),
+ .sram8_dout1(sram8_dout1),
+ .sram9_dout0(sram9_dout0),
+ .sram9_dout1(sram9_dout1),
+ .sram10_dout0(sram10_dout0),
+ .sram10_dout1(sram10_dout1),
+ .sram11_dout0(sram11_dout0),
+ .sram11_dout1(sram11_dout1),
+ .sram12_dout0(sram12_dout0),
+ .sram12_dout1(sram12_dout1),
+ .sram13_dout0(sram13_dout0),
+ .sram13_dout1(sram13_dout1),
+ .sram14_dout0(sram14_dout0),
+ .sram14_dout1(sram14_dout1),
+ .sram15_dout0(sram15_dout0),
+ .sram15_dout1(sram15_dout1),
+ .left_addr0(left_addr0),
+ .left_din0(left_din0),
+ .left_web0(left_web0),
+ .left_wmask0(left_wmask0),
+ .left_addr1(left_addr1),
+ .left_din1(left_din1),
+ .left_web1(left_web1),
+ .left_wmask1(wmask1),
+ .left_csb0(left_csb0),
+ .left_csb1(left_csb1),
+ .right_addr0(right_addr0),
+ .right_din0(right_din0),
+ .right_web0(right_web0),
+ .right_wmask0(right_wmask0),
+ .right_csb0(right_csb0),
.sram0_clk(sram0_clk),
.sram1_clk(sram1_clk),
.sram2_clk(sram2_clk),
.sram3_clk(sram3_clk),
.sram4_clk(sram4_clk),
- //.sram5_clk(sram5_clk),
- .la_data0(la_data0),
- .la_data1(la_data1),
- .gpio_data0(gpio_data0),
- .gpio_data1(gpio_data1)
+ .sram5_clk(sram5_clk),
+ .sram6_clk(sram6_clk),
+ .sram7_clk(sram7_clk),
+ .sram8_clk(sram8_clk),
+ .sram9_clk(sram9_clk),
+ .sram10_clk(sram10_clk),
+ .sram11_clk(sram11_clk),
+ .sram12_clk(sram12_clk),
+ .sram13_clk(sram13_clk),
+ .sram14_clk(sram14_clk),
+ .sram15_clk(sram15_clk),
+ .la_data_out(la_data_out),
+ .gpio_out(gpio_out)
);
-sky130_sram_1kbyte_1rw1r_32x256_8 SRAM0
+sky130_sram_1kbyte_1rw1r_8x1024_8 SRAM0
(
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ `endif
.clk0 (sram0_clk),
- .csb0 (sram0_connections[54]),
- .web0 (sram0_connections[53]),
- .wmask0 (sram0_connections[52:49]),
- .addr0 (sram0_connections[48:41]),
- .din0 (sram0_connections[40:9]),
- .dout0 (sram0_rw_in),
+ .csb0 (left_csb0[0]),
+ .web0 (left_web0),
+ .wmask0 (left_wmask0),
+ .addr0 (left_addr0),
+ .din0 (left_din0),
+ .dout0 (sram0_dout0[7:0]),
.clk1 (sram0_clk),
- .csb1 (sram0_connections[8]),
- .addr1 (sram0_connections[7:0]),
- .dout1 (sram0_ro_in));
-
+ .csb1 (left_csb1[0]),
+ .addr1 (left_addr0),
+ .dout1 (sram0_dout1[7:0])
+ );
+assign sram0_dout0[`DATA_SIZE-1:8] = 0;
+assign sram0_dout1[`DATA_SIZE-1:8] = 0;
+
sky130_sram_1kbyte_1rw1r_32x256_8 SRAM1
(
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ `endif
.clk0 (sram1_clk),
- .csb0 (sram1_connections[54]),
- .web0 (sram1_connections[53]),
- .wmask0 (sram1_connections[52:49]),
- .addr0 (sram1_connections[48:41]),
- .din0 (sram1_connections[40:9]),
- .dout0 (sram1_rw_in),
+ .csb0 (left_csb0[1]),
+ .web0 (left_web0),
+ .wmask0 (left_wmask0),
+ .addr0 (left_addr0),
+ .din0 (left_din0),
+ .dout0 (sram1_dout0),
.clk1 (sram1_clk),
- .csb1 (sram1_connections[8]),
- .addr1 (sram1_connections[7:0]),
- .dout1 (sram1_ro_in));
-
-sram_1rw0r0w_32_1024_sky130 SRAM2
- (
+ .csb1 (left_csb1[1]),
+ .addr1 (left_addr1),
+ .dout1 (sram1_dout1)
+ );
+
+sky130_sram_2kbyte_1rw1r_32x512_8 SRAM2
+ (
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ `endif
.clk0 (sram2_clk),
- .csb0 (sram2_connections[47]),
- .web0 (sram2_connections[46]),
- .wmask0 (sram2_connections[45:42]),
- .addr0 (sram2_connections[41:32]),
- .din0 (sram2_connections[31:0]),
- .dout0 (sram2_rw_in));
+ .csb0 (left_csb0[2]),
+ .web0 (left_web0),
+ .wmask0 (left_wmask0),
+ .addr0 (left_addr0),
+ .din0 (left_din0),
+ .dout0 (sram2_dout0),
+ .clk1 (sram2_clk),
+ .csb1 (left_csb1[2]),
+ .addr1 (left_addr1),
+ .dout1 (sram2_dout1)
+ );
-sram_1rw0r0w_32_256_sky130 SRAM3
- (
+sky130_sram_4kbyte_1rw1r_32x1024_8 SRAM3
+ (
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ `endif
.clk0 (sram3_clk),
- .csb0 (sram3_connections[45]),
- .web0 (sram3_connections[44]),
- .wmask0 (sram3_connections[43:40]),
- .addr0 (sram3_connections[39:32]),
- .din0 (sram3_connections[31:0]),
- .dout0 (sram3_rw_in));
-
-sram_1rw0r0w_32_512_sky130 SRAM4
- (
+ .csb0 (left_csb0[3]),
+ .web0 (left_web0),
+ .wmask0 (left_wmask0),
+ .addr0 (left_addr0),
+ .din0 (left_din0),
+ .dout0 (sram3_dout0),
+ .clk1 (sram3_clk),
+ .csb1 (left_csb1[3]),
+ .addr1 (left_addr1),
+ .dout1 (sram3_dout1)
+ );
+
+sky130_sram_8kbyte_1rw1r_32x2048_8 SRAM4
+ (
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ `endif
.clk0 (sram4_clk),
- .csb0 (sram4_connections[46]),
- .web0 (sram4_connections[45]),
- .wmask0 (sram4_connections[44:41]),
- .addr0 (sram4_connections[40:32]),
- .din0 (sram4_connections[31:0]),
- .dout0 (sram4_rw_in));
+ .csb0 (left_csb0[4]),
+ .web0 (left_web0),
+ .wmask0 (left_wmask0),
+ .addr0 (left_addr0),
+ .din0 (left_din0),
+ .dout0 (sram4_dout0),
+ .clk1 (sram4_clk),
+ .csb1 (left_csb1[4]),
+ .addr1 (left_addr1),
+ .dout1 (sram4_dout1)
+ );
-/*
-sram_1rw0r0w_64_512_sky130 SRAM5
+// Not working yet
+// sky130_sram_16kbyte_1rw1r_32x4096_8 SRAM6
+// (
+// `ifdef USE_POWER_PINS
+// .vccd1(vccd1),
+// .vssd1(vssd1),
+// `endif
+// .clk0 (sram6_clk),
+// .csb0 (csb0[6]),
+// .web0 (web0),
+// .wmask0 (wmask0),
+// .addr0 (addr0),
+// .din0 (din0),
+// .dout0 (sram6_dout0),
+// .clk1 (sram6_clk),
+// .csb1 (csb1[6]),
+// .addr1 (addr1),
+// .dout1 (sram6_dout1)
+// );
+
+
+
+// Single port memories
+sram_1rw0r0w_32_256_sky130 SRAM8
(
- .clk0 (sram5_clk),
- .csb0 (sram5_connections[82]),
- .web0 (sram5_connections[81]),
- .wmask0 (sram5_connections[80:73]),
- .addr0 (sram5_connections[72:64]),
- .din0 (sram5_connections[63:0]),
- .dout0 (sram5_rw_in));
-*/
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ `endif
+ .clk0 (sram8_clk),
+ .csb0 (right_csb0[8]),
+ .web0 (right_web0),
+ .wmask0 (right_wmask0),
+ .addr0 (right_addr0),
+ .din0 (right_din0),
+ .dout0 (sram8_dout0)
+ );
+assign sram8_dout1 = 0;
+
+sram_1rw0r0w_32_512_sky130 SRAM9
+ (
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ `endif
+ .clk0 (sram9_clk),
+ .csb0 (right_csb0[9]),
+ .web0 (right_web0),
+ .wmask0 (right_wmask0),
+ .addr0 (right_addr0),
+ .din0 (right_din0),
+ .dout0 (sram9_dout0)
+ );
+assign sram9_dout1 = 0;
+
+sram_1rw0r0w_32_1024_sky130 SRAM10
+ (
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ `endif
+ .clk0 (sram10_clk),
+ .csb0 (right_csb0[10]),
+ .web0 (right_web0),
+ .wmask0 (right_wmask0),
+ .addr0 (right_addr0),
+ .din0 (right_din0),
+ .dout0 (sram10_dout0)
+ );
+assign sram10_dout1 = 0;
+
+sram_1rw0r0w_64_512_sky130 SRAM11
+ (
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ `endif
+ .clk0 (sram11_clk),
+ .csb0 (right_csb0[11]),
+ .web0 (right_web0),
+ .wmask0 (right_wmask0),
+ .addr0 (right_addr0),
+ .din0 ({right_din0[31:16], 32'd0, right_din0[15:0]}),
+ .dout0 (temp_sram11_dout0)
+ );
+
+wire [63:0] temp_sram11_dout0;
+assign sram11_dout1 = 0;
+assign sram11_dout0 = {temp_sram11_dout0[64:33], temp_sram11_dout[15:0]};
initial begin
$dumpfile("testchip_tb.vcd");
