Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main
diff --git a/openlane/openram_testchip/config.tcl b/openlane/openram_testchip/config.tcl
index 20be68e..de26d8b 100644
--- a/openlane/openram_testchip/config.tcl
+++ b/openlane/openram_testchip/config.tcl
@@ -8,15 +8,16 @@
set ::env(VERILOG_FILES) "$script_dir/../../verilog/rtl/openram_defines.v \
$script_dir/../../verilog/rtl/openram_testchip.v"
-#set ::env(BASE_SDC_FILE) "$script_dir/clks.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/openram_testchip.sdc"
-set ::env(CLOCK_PORT) "la_clk"
-#set ::env(CLOCK_NET) "clk sram_clk"
-set ::env(CLOCK_NET) ""
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_NET) "clk sram_clk"
+#set ::env(CLOCK_NET) ""
+set ::env(CLOCK_PERIOD) "20"
+set ::env(IO_PCT) 0.1
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 400 2900"
+set ::env(DIE_AREA) "0 0 400 2600"
set ::env(DESIGN_IS_CORE) 0
set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
diff --git a/openlane/openram_testchip/openram_testchip.sdc b/openlane/openram_testchip/openram_testchip.sdc
new file mode 100644
index 0000000..644e49a
--- /dev/null
+++ b/openlane/openram_testchip/openram_testchip.sdc
@@ -0,0 +1,24 @@
+create_clock [get_port $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
+set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
+
+set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
+#set rst_indx [lsearch [all_inputs] [get_port resetn]]
+set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
+#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
+set all_inputs_wo_clk_rst $all_inputs_wo_clk
+
+# correct resetn
+set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
+#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
+set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index edc95f9..9a9ef9c 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -48,4 +48,4 @@
# 823 x 335
SRAM8 2000 2600 N
-CONTROL_LOGIC 1500 100 N
+CONTROL_LOGIC 1475 100 N
