commit: 741732cb13fbb5f5f57d0f56d8a217175d5eae72
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Tue Jun 15 14:00:53 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Tue Jun 15 14:00:53 2021 -0700
tree: 25f3af2a645324e60481e06074f869fdd81dcae8
parent: dca58fabcb30648f59072d74a44064bbcf52ac6e [diff]

Switched to for loops, check why assertion fails

verilog/rtl/openram_testchip_tb.v[diff]

1 file changed

tree: 25f3af2a645324e60481e06074f869fdd81dcae8

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.