)]}'
{
  "commit": "741732cb13fbb5f5f57d0f56d8a217175d5eae72",
  "tree": "25f3af2a645324e60481e06074f869fdd81dcae8",
  "parents": [
    "dca58fabcb30648f59072d74a44064bbcf52ac6e"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Tue Jun 15 14:00:53 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Tue Jun 15 14:00:53 2021 -0700"
  },
  "message": "Switched to for loops, check why assertion fails\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3ff7d952ff353cb342a73000516c7918849eff80",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip_tb.v",
      "new_id": "1bd2955106b4af945ac716cf7684f5e8a906d132",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip_tb.v"
    }
  ]
}