commit 73a59ccb753e4b9c6b75350a5834215ea772a13f
author mrg <mrg@ucsc.edu> Fri Jun 25 14:39:40 2021 -0700
committer mrg <mrg@ucsc.edu> Fri Jun 25 14:39:40 2021 -0700
tree 325a86cfd288a24eee15d2f0acf8fa4cde1e91bd
parent 8411fd268b91b25f5594d49b4a1af43c52cedaff

Add gpio_clk back and it is sync with clock

verilog/dv/gpio_test/gpio_test_tb.v

diff --git a/verilog/dv/gpio_test/gpio_test_tb.v b/verilog/dv/gpio_test/gpio_test_tb.v
index 9bb2c82..bf043b4 100644
--- a/verilog/dv/gpio_test/gpio_test_tb.v
+++ b/verilog/dv/gpio_test/gpio_test_tb.v
@@ -37,9 +37,11 @@
 	// would be the fast clock.
 
 	always #12.5 clock <= (clock === 1'b0);
+	always #12.5 gpio_clk <= (gpio_clk === 1'b0);
 
 	initial begin
-		clock = 0;
+	   clock = 0;
+	   gpio_clk = 0;
 	end
 
 	reg gpio_clk;
@@ -77,7 +79,6 @@
       begin
 
 
-	 gpio_clk = 1;
 	 global_csb = 1;
 	 gpio_scan = 1;
 	 gpio_sram_load = 0;
@@ -110,7 +111,6 @@
       begin
 
 
-	 gpio_clk = 1;
 	 global_csb = 1;
 	 gpio_scan = 1;
 	 gpio_sram_load = 0;
@@ -158,7 +158,6 @@
 		$dumpfile("gpio_test.vcd");
 		$dumpvars(0, gpio_test_tb);
 
-		gpio_clk = 1;
 		global_csb = 1;
 
 	   # 100;