Writes to SRAM0 correctly
diff --git a/verilog/rtl/openram_testchip_tb.v b/verilog/rtl/openram_testchip_tb.v index 7edbb93..6c6dcfd 100644 --- a/verilog/rtl/openram_testchip_tb.v +++ b/verilog/rtl/openram_testchip_tb.v
@@ -42,14 +42,14 @@ wire [45:0] sram3_connections; wire [46:0] sram4_connections; //wire [82:0] sram5_connections; - wire [63:0] la_data0; - wire [63:0] la_data1; + wire [31:0] la_data0; + wire [31:0] la_data1; wire gpio_data0; wire gpio_data1; openram_testchip CONTROL_LOGIC( - .la_clk(clk_in), - .gpio_clk(clk_in), + .la_clk(la_clk), + .gpio_clk(gpio_clk), .la_sram_clk(la_sram_clk), .gpio_sram_clk(gpio_sram_clk), .reset(reset), @@ -83,35 +83,35 @@ sky130_sram_1kbyte_1rw1r_32x256_8 SRAM0 ( - .clk0 (sram0_connections[55]), + .clk0 (la_sram_clk), .csb0 (sram0_connections[54]), .web0 (sram0_connections[53]), .wmask0 (sram0_connections[52:49]), .addr0 (sram0_connections[48:41]), .din0 (sram0_connections[40:9]), .dout0 (sram0_rw_in), - .clk1 (sram0_connections[55]), + .clk1 (la_sram_clk), .csb1 (sram0_connections[8]), .addr1 (sram0_connections[7:0]), .dout1 (sram0_ro_in)); sky130_sram_1kbyte_1rw1r_32x256_8 SRAM1 ( - .clk0 (sram1_connections[55]), + .clk0 (la_sram_clk), .csb0 (sram1_connections[54]), .web0 (sram1_connections[53]), .wmask0 (sram1_connections[52:49]), .addr0 (sram1_connections[48:41]), .din0 (sram1_connections[40:9]), .dout0 (sram1_rw_in), - .clk1 (sram1_connections[55]), + .clk1 (la_sram_clk), .csb1 (sram1_connections[8]), .addr1 (sram1_connections[7:0]), .dout1 (sram1_ro_in)); sram_1rw0r0w_32_1024_sky130 SRAM2 ( - .clk0 (sram2_connections[48]), + .clk0 (la_sram_clk), .csb0 (sram2_connections[47]), .web0 (sram2_connections[46]), .wmask0 (sram2_connections[45:42]), @@ -121,7 +121,7 @@ sram_1rw0r0w_32_256_sky130 SRAM3 ( - .clk0 (sram3_connections[46]), + .clk0 (la_sram_clk), .csb0 (sram3_connections[45]), .web0 (sram3_connections[44]), .wmask0 (sram3_connections[43:40]), @@ -131,7 +131,7 @@ sram_1rw0r0w_32_512_sky130 SRAM4 ( - .clk0 (sram4_connections[47]), + .clk0 (la_sram_clk), .csb0 (sram4_connections[46]), .web0 (sram4_connections[45]), .wmask0 (sram4_connections[44:41]), @@ -155,9 +155,26 @@ $dumpfile("testchip_tb.vcd"); $dumpvars(0, test_chip_tb); la_clk = 1; + gpio_clk = 0; + gpio_sram_clk = 0; + gpio_in_scan = 0; + gpio_bit = 0; + gpio_out_scan = 0; reset = 0; - //Send packet using logic analyzer + + //Send bits using logic analyzer in_select = 0; + la_in_load = 1; + la_bits = {4'd0, 16'd1, 32'd1, 1'b0, 1'b0, 4'd15, 16'd0, 32'd0, 1'b1, 1'b1, 4'd0}; + + #10; + la_in_load = 0; + la_sram_load = 1; + la_sram_clk = 1; + #5 + la_sram_clk = 0; + #5 + /* from_analyzer = 86'd0; @@ -171,66 +188,7 @@ from_analyzer = {3'd0, 28'd0, 1'b0, 1'b1, 4'd0, 8'd1, 32'd0, 1'b1, 8'd0}; #60; `assert(to_la, 64'd1); - - //Read from address 1 in SRAM 0 using RO Port - from_analyzer = {3'd0, 28'd0, 1'b1, 1'b1, 4'd0, 8'd0, 32'd0, 1'b0, 8'd1}; - #60; - `assert(to_la, 64'd1); - - //Write 1 to address 1 in SRAM 1 - from_analyzer = {3'd1, 28'd0, 1'b0, 1'b0, 4'd15, 8'd1, 32'd1, 1'b0, 8'd0}; - #20 - - //Read from address 1 in SRAM 1 - from_analyzer = {3'd1, 28'd0, 1'b0, 1'b1, 4'd0, 8'd1, 32'd0, 1'b1, 8'd0}; - #60; - - `assert(to_la, 64'd1); - - //Read from address 1 in SRAM 1 using RO Port - from_analyzer = {3'd0, 28'd0, 1'b1, 1'b1, 4'd0, 8'd0, 32'd0, 1'b0, 8'd1}; - #60; - `assert(to_la, 64'd1); - - //Write 2 to address 2 in SRAM 2 - from_analyzer = {3'd2, 35'd0, 1'b0, 1'b0, 4'd15, 10'd2, 32'd2}; - #20 - - //Read from address 2 in SRAM 2 - from_analyzer = {3'd2, 35'd0, 1'b0, 1'b1, 4'd0, 10'd2, 32'd0}; - #60; - - `assert(to_la, 64'd2); - - //Write 3 to address 3 in SRAM 3 - from_analyzer = {3'd3, 37'd0, 1'b0, 1'b0, 4'd15, 8'd3, 32'd3}; - #20 - - //Read from address 3 in SRAM 3 - from_analyzer = {3'd3, 37'd0, 1'b0, 1'b1, 4'd0, 8'd3, 32'd0}; - #60; - `assert(to_la, 64'd3); - - //Write 4 to address 4 in SRAM 4 - from_analyzer = {3'd4, 36'd0, 1'b0, 1'b0, 4'd15, 9'd4, 32'd4}; - #20 - - //Read from address 4 in SRAM 4 - from_analyzer = {3'd4, 36'd0, 1'b0, 1'b1, 4'd0, 9'd4, 32'd0}; - #60; - - `assert(to_la, 64'd4); - - //Write 5 to address 5 in SRAM 5 - from_analyzer = {3'd5, 1'b0, 1'b0, 8'd255, 9'd5, 64'd5}; - #20 - - //Read from address 5 in SRAM 5 - from_analyzer = {3'd5, 1'b0, 1'b1, 8'd0, 9'd5, 64'd0}; - #60; - `assert(to_la, 64'd5); - */ - #10;$finish; + #30;$finish; end always