Fix port size

verilog/rtl/openram_defines.v

diff --git a/verilog/rtl/openram_defines.v b/verilog/rtl/openram_defines.v
index ff695e8..13e9a65 100644
--- a/verilog/rtl/openram_defines.v
+++ b/verilog/rtl/openram_defines.v
@@ -3,5 +3,5 @@
 `define DATA_SIZE 32
 `define SELECT_SIZE 4
 `define MAX_CHIPS 16
-`define PORT_SIZE `DATA_SIZE+`DATA_SIZE+`WMASK_SIZE+2
+`define PORT_SIZE `ADDR_SIZE+`DATA_SIZE+`WMASK_SIZE+2
 `define TOTAL_SIZE 2*`PORT_SIZE + `SELECT_SIZE