commit: 5d991a9b00bb98cb998102b1922efddd991ac4bc
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Sat Jun 12 12:14:55 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Sat Jun 12 12:14:55 2021 -0700
tree: f60c0ab756efa683bfc9c0b28d9cbbdca03ccb63
parent: caefc5838f8a00ad83331eb62bbcc3e04f73ceb2 [diff]

Made connections, compiles, set proper values

verilog/rtl/openram_testchip_tb.v[diff]

1 file changed

tree: f60c0ab756efa683bfc9c0b28d9cbbdca03ccb63

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.