)]}'
{
  "commit": "5d991a9b00bb98cb998102b1922efddd991ac4bc",
  "tree": "f60c0ab756efa683bfc9c0b28d9cbbdca03ccb63",
  "parents": [
    "caefc5838f8a00ad83331eb62bbcc3e04f73ceb2"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 12:14:55 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 12:14:55 2021 -0700"
  },
  "message": "Made connections, compiles, set proper values\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "5ff4a6dcdacc281812232bba5e44fb2905fe63b5",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip_tb.v",
      "new_id": "7edbb9369b63ed24ec8db588c73f9c0f09bec07a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip_tb.v"
    }
  ]
}