Add all dual port memories
diff --git a/gds/sky130_sram_1kbyte_1rw1r_8x1024_8.gds b/gds/sky130_sram_1kbyte_1rw1r_8x1024_8.gds
new file mode 100644
index 0000000..24b326b
--- /dev/null
+++ b/gds/sky130_sram_1kbyte_1rw1r_8x1024_8.gds
Binary files differ
diff --git a/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds b/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds
new file mode 100644
index 0000000..281682f
--- /dev/null
+++ b/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds
Binary files differ
diff --git a/gds/sky130_sram_4kbyte_1rw1r_32x1024_8.gds b/gds/sky130_sram_4kbyte_1rw1r_32x1024_8.gds
new file mode 100644
index 0000000..51f9f25
--- /dev/null
+++ b/gds/sky130_sram_4kbyte_1rw1r_32x1024_8.gds
Binary files differ
diff --git a/gds/sky130_sram_8kbyte_1rw1r_32x2048_8.gds b/gds/sky130_sram_8kbyte_1rw1r_32x2048_8.gds
new file mode 100644
index 0000000..28394f3
--- /dev/null
+++ b/gds/sky130_sram_8kbyte_1rw1r_32x2048_8.gds
Binary files differ
diff --git a/lef/sky130_sram_1kbyte_1rw1r_8x1024_8.lef b/lef/sky130_sram_1kbyte_1rw1r_8x1024_8.lef
new file mode 100644
index 0000000..16eaf4b
--- /dev/null
+++ b/lef/sky130_sram_1kbyte_1rw1r_8x1024_8.lef
@@ -0,0 +1,529 @@
+VERSION 5.4 ;
+NAMESCASESENSITIVE ON ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+UNITS
+ DATABASE MICRONS 2000 ;
+END UNITS
+MACRO sky130_sram_1kbyte_1rw1r_8x1024_8
+ CLASS BLOCK ;
+ SIZE 451.9 BY 443.06 ;
+ SYMMETRY X Y R90 ;
+ PIN din0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 87.04 0.0 87.42 0.38 ;
+ END
+ END din0[0]
+ PIN din0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 93.16 0.0 93.54 0.38 ;
+ END
+ END din0[1]
+ PIN din0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 98.6 0.0 98.98 0.38 ;
+ END
+ END din0[2]
+ PIN din0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 104.04 0.0 104.42 0.38 ;
+ END
+ END din0[3]
+ PIN din0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 110.16 0.0 110.54 0.38 ;
+ END
+ END din0[4]
+ PIN din0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 115.6 0.0 115.98 0.38 ;
+ END
+ END din0[5]
+ PIN din0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 122.4 0.0 122.78 0.38 ;
+ END
+ END din0[6]
+ PIN din0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 127.16 0.0 127.54 0.38 ;
+ END
+ END din0[7]
+ PIN addr0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 63.24 0.0 63.62 0.38 ;
+ END
+ END addr0[0]
+ PIN addr0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 70.04 0.0 70.42 0.38 ;
+ END
+ END addr0[1]
+ PIN addr0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 75.48 0.0 75.86 0.38 ;
+ END
+ END addr0[2]
+ PIN addr0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 141.44 0.38 141.82 ;
+ END
+ END addr0[3]
+ PIN addr0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 149.6 0.38 149.98 ;
+ END
+ END addr0[4]
+ PIN addr0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 156.4 0.38 156.78 ;
+ END
+ END addr0[5]
+ PIN addr0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 164.56 0.38 164.94 ;
+ END
+ END addr0[6]
+ PIN addr0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 169.32 0.38 169.7 ;
+ END
+ END addr0[7]
+ PIN addr0[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 177.48 0.38 177.86 ;
+ END
+ END addr0[8]
+ PIN addr0[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 183.6 0.38 183.98 ;
+ END
+ END addr0[9]
+ PIN addr1[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 382.16 442.68 382.54 443.06 ;
+ END
+ END addr1[0]
+ PIN addr1[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 376.72 442.68 377.1 443.06 ;
+ END
+ END addr1[1]
+ PIN addr1[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 371.28 442.68 371.66 443.06 ;
+ END
+ END addr1[2]
+ PIN addr1[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 97.24 451.9 97.62 ;
+ END
+ END addr1[3]
+ PIN addr1[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 88.4 451.9 88.78 ;
+ END
+ END addr1[4]
+ PIN addr1[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 82.96 451.9 83.34 ;
+ END
+ END addr1[5]
+ PIN addr1[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 74.12 451.9 74.5 ;
+ END
+ END addr1[6]
+ PIN addr1[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 68.68 451.9 69.06 ;
+ END
+ END addr1[7]
+ PIN addr1[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 59.84 451.9 60.22 ;
+ END
+ END addr1[8]
+ PIN addr1[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 53.72 451.9 54.1 ;
+ END
+ END addr1[9]
+ PIN csb0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 41.48 0.38 41.86 ;
+ END
+ END csb0
+ PIN csb1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 395.76 451.9 396.14 ;
+ END
+ END csb1
+ PIN web0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 49.64 0.38 50.02 ;
+ END
+ END web0
+ PIN clk0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 42.16 0.38 42.54 ;
+ END
+ END clk0
+ PIN clk1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 395.08 451.9 395.46 ;
+ END
+ END clk1
+ PIN wmask0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 80.92 0.0 81.3 0.38 ;
+ END
+ END wmask0[0]
+ PIN dout0[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 125.12 0.0 125.5 0.38 ;
+ END
+ END dout0[0]
+ PIN dout0[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 150.96 0.0 151.34 0.38 ;
+ END
+ END dout0[1]
+ PIN dout0[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 176.12 0.0 176.5 0.38 ;
+ END
+ END dout0[2]
+ PIN dout0[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 201.28 0.0 201.66 0.38 ;
+ END
+ END dout0[3]
+ PIN dout0[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 226.44 0.0 226.82 0.38 ;
+ END
+ END dout0[4]
+ PIN dout0[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 250.92 0.0 251.3 0.38 ;
+ END
+ END dout0[5]
+ PIN dout0[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 276.08 0.0 276.46 0.38 ;
+ END
+ END dout0[6]
+ PIN dout0[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 301.24 0.0 301.62 0.38 ;
+ END
+ END dout0[7]
+ PIN dout1[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 126.48 442.68 126.86 443.06 ;
+ END
+ END dout1[0]
+ PIN dout1[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 151.64 442.68 152.02 443.06 ;
+ END
+ END dout1[1]
+ PIN dout1[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 176.8 442.68 177.18 443.06 ;
+ END
+ END dout1[2]
+ PIN dout1[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 201.96 442.68 202.34 443.06 ;
+ END
+ END dout1[3]
+ PIN dout1[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 226.44 442.68 226.82 443.06 ;
+ END
+ END dout1[4]
+ PIN dout1[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 250.92 442.68 251.3 443.06 ;
+ END
+ END dout1[5]
+ PIN dout1[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 276.76 442.68 277.14 443.06 ;
+ END
+ END dout1[6]
+ PIN dout1[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 301.92 442.68 302.3 443.06 ;
+ END
+ END dout1[7]
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met4 ;
+ RECT 448.8 1.36 450.54 441.7 ;
+ LAYER met3 ;
+ RECT 1.36 439.96 450.54 441.7 ;
+ LAYER met4 ;
+ RECT 1.36 1.36 3.1 441.7 ;
+ LAYER met3 ;
+ RECT 1.36 1.36 450.54 3.1 ;
+ END
+ END vccd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met3 ;
+ RECT 4.76 4.76 447.14 6.5 ;
+ LAYER met4 ;
+ RECT 4.76 4.76 6.5 438.3 ;
+ LAYER met3 ;
+ RECT 4.76 436.56 447.14 438.3 ;
+ LAYER met4 ;
+ RECT 445.4 4.76 447.14 438.3 ;
+ END
+ END vssd1
+ OBS
+ LAYER met1 ;
+ RECT 0.62 0.62 451.28 442.44 ;
+ LAYER met2 ;
+ RECT 0.62 0.62 451.28 442.44 ;
+ LAYER met3 ;
+ RECT 0.98 140.84 451.28 142.42 ;
+ RECT 0.62 142.42 0.98 149.0 ;
+ RECT 0.62 150.58 0.98 155.8 ;
+ RECT 0.62 157.38 0.98 163.96 ;
+ RECT 0.62 165.54 0.98 168.72 ;
+ RECT 0.62 170.3 0.98 176.88 ;
+ RECT 0.62 178.46 0.98 183.0 ;
+ RECT 0.98 96.64 450.92 98.22 ;
+ RECT 0.98 98.22 450.92 140.84 ;
+ RECT 450.92 98.22 451.28 140.84 ;
+ RECT 450.92 89.38 451.28 96.64 ;
+ RECT 450.92 83.94 451.28 87.8 ;
+ RECT 450.92 75.1 451.28 82.36 ;
+ RECT 450.92 69.66 451.28 73.52 ;
+ RECT 450.92 60.82 451.28 68.08 ;
+ RECT 450.92 54.7 451.28 59.24 ;
+ RECT 0.98 142.42 450.92 395.16 ;
+ RECT 0.98 395.16 450.92 396.74 ;
+ RECT 0.62 50.62 0.98 140.84 ;
+ RECT 0.62 43.14 0.98 49.04 ;
+ RECT 450.92 142.42 451.28 394.48 ;
+ RECT 0.62 184.58 0.76 439.36 ;
+ RECT 0.62 439.36 0.76 442.3 ;
+ RECT 0.62 442.3 0.76 442.44 ;
+ RECT 0.76 184.58 0.98 439.36 ;
+ RECT 0.76 442.3 0.98 442.44 ;
+ RECT 0.98 442.3 450.92 442.44 ;
+ RECT 450.92 396.74 451.14 439.36 ;
+ RECT 450.92 442.3 451.14 442.44 ;
+ RECT 451.14 396.74 451.28 439.36 ;
+ RECT 451.14 439.36 451.28 442.3 ;
+ RECT 451.14 442.3 451.28 442.44 ;
+ RECT 0.98 0.62 450.92 0.76 ;
+ RECT 450.92 0.62 451.14 0.76 ;
+ RECT 450.92 3.7 451.14 53.12 ;
+ RECT 451.14 0.62 451.28 0.76 ;
+ RECT 451.14 0.76 451.28 3.7 ;
+ RECT 451.14 3.7 451.28 53.12 ;
+ RECT 0.62 0.62 0.76 0.76 ;
+ RECT 0.62 0.76 0.76 3.7 ;
+ RECT 0.62 3.7 0.76 40.88 ;
+ RECT 0.76 0.62 0.98 0.76 ;
+ RECT 0.76 3.7 0.98 40.88 ;
+ RECT 0.98 3.7 4.16 4.16 ;
+ RECT 0.98 4.16 4.16 7.1 ;
+ RECT 0.98 7.1 4.16 96.64 ;
+ RECT 4.16 3.7 447.74 4.16 ;
+ RECT 4.16 7.1 447.74 96.64 ;
+ RECT 447.74 3.7 450.92 4.16 ;
+ RECT 447.74 4.16 450.92 7.1 ;
+ RECT 447.74 7.1 450.92 96.64 ;
+ RECT 0.98 396.74 4.16 435.96 ;
+ RECT 0.98 435.96 4.16 438.9 ;
+ RECT 0.98 438.9 4.16 439.36 ;
+ RECT 4.16 396.74 447.74 435.96 ;
+ RECT 4.16 438.9 447.74 439.36 ;
+ RECT 447.74 396.74 450.92 435.96 ;
+ RECT 447.74 435.96 450.92 438.9 ;
+ RECT 447.74 438.9 450.92 439.36 ;
+ LAYER met4 ;
+ RECT 86.44 0.98 88.02 442.44 ;
+ RECT 88.02 0.62 92.56 0.98 ;
+ RECT 94.14 0.62 98.0 0.98 ;
+ RECT 99.58 0.62 103.44 0.98 ;
+ RECT 105.02 0.62 109.56 0.98 ;
+ RECT 111.14 0.62 115.0 0.98 ;
+ RECT 116.58 0.62 121.8 0.98 ;
+ RECT 64.22 0.62 69.44 0.98 ;
+ RECT 71.02 0.62 74.88 0.98 ;
+ RECT 88.02 0.98 381.56 442.08 ;
+ RECT 381.56 0.98 383.14 442.08 ;
+ RECT 377.7 442.08 381.56 442.44 ;
+ RECT 372.26 442.08 376.12 442.44 ;
+ RECT 76.46 0.62 80.32 0.98 ;
+ RECT 81.9 0.62 86.44 0.98 ;
+ RECT 123.38 0.62 124.52 0.98 ;
+ RECT 126.1 0.62 126.56 0.98 ;
+ RECT 128.14 0.62 150.36 0.98 ;
+ RECT 151.94 0.62 175.52 0.98 ;
+ RECT 177.1 0.62 200.68 0.98 ;
+ RECT 202.26 0.62 225.84 0.98 ;
+ RECT 227.42 0.62 250.32 0.98 ;
+ RECT 251.9 0.62 275.48 0.98 ;
+ RECT 277.06 0.62 300.64 0.98 ;
+ RECT 88.02 442.08 125.88 442.44 ;
+ RECT 127.46 442.08 151.04 442.44 ;
+ RECT 152.62 442.08 176.2 442.44 ;
+ RECT 177.78 442.08 201.36 442.44 ;
+ RECT 202.94 442.08 225.84 442.44 ;
+ RECT 227.42 442.08 250.32 442.44 ;
+ RECT 251.9 442.08 276.16 442.44 ;
+ RECT 277.74 442.08 301.32 442.44 ;
+ RECT 302.9 442.08 370.68 442.44 ;
+ RECT 451.14 0.98 451.28 442.08 ;
+ RECT 383.14 442.08 448.2 442.3 ;
+ RECT 383.14 442.3 448.2 442.44 ;
+ RECT 448.2 442.3 451.14 442.44 ;
+ RECT 451.14 442.08 451.28 442.3 ;
+ RECT 451.14 442.3 451.28 442.44 ;
+ RECT 302.22 0.62 448.2 0.76 ;
+ RECT 302.22 0.76 448.2 0.98 ;
+ RECT 448.2 0.62 451.14 0.76 ;
+ RECT 451.14 0.62 451.28 0.76 ;
+ RECT 451.14 0.76 451.28 0.98 ;
+ RECT 0.62 0.98 0.76 442.3 ;
+ RECT 0.62 442.3 0.76 442.44 ;
+ RECT 0.76 442.3 3.7 442.44 ;
+ RECT 3.7 442.3 86.44 442.44 ;
+ RECT 0.62 0.62 0.76 0.76 ;
+ RECT 0.62 0.76 0.76 0.98 ;
+ RECT 0.76 0.62 3.7 0.76 ;
+ RECT 3.7 0.62 62.64 0.76 ;
+ RECT 3.7 0.76 62.64 0.98 ;
+ RECT 3.7 0.98 4.16 4.16 ;
+ RECT 3.7 4.16 4.16 438.9 ;
+ RECT 3.7 438.9 4.16 442.3 ;
+ RECT 4.16 0.98 7.1 4.16 ;
+ RECT 4.16 438.9 7.1 442.3 ;
+ RECT 7.1 0.98 86.44 4.16 ;
+ RECT 7.1 4.16 86.44 438.9 ;
+ RECT 7.1 438.9 86.44 442.3 ;
+ RECT 383.14 0.98 444.8 4.16 ;
+ RECT 383.14 4.16 444.8 438.9 ;
+ RECT 383.14 438.9 444.8 442.08 ;
+ RECT 444.8 0.98 447.74 4.16 ;
+ RECT 444.8 438.9 447.74 442.08 ;
+ RECT 447.74 0.98 448.2 4.16 ;
+ RECT 447.74 4.16 448.2 438.9 ;
+ RECT 447.74 438.9 448.2 442.08 ;
+ END
+END sky130_sram_1kbyte_1rw1r_8x1024_8
+END LIBRARY
diff --git a/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef b/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef
new file mode 100644
index 0000000..e66b47e
--- /dev/null
+++ b/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef
@@ -0,0 +1,1108 @@
+VERSION 5.4 ;
+NAMESCASESENSITIVE ON ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+UNITS
+ DATABASE MICRONS 2000 ;
+END UNITS
+MACRO sky130_sram_2kbyte_1rw1r_32x512_8
+ CLASS BLOCK ;
+ SIZE 679.02 BY 413.14 ;
+ SYMMETRY X Y R90 ;
+ PIN din0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 113.56 0.0 113.94 0.38 ;
+ END
+ END din0[0]
+ PIN din0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 119.0 0.0 119.38 0.38 ;
+ END
+ END din0[1]
+ PIN din0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 125.12 0.0 125.5 0.38 ;
+ END
+ END din0[2]
+ PIN din0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 130.56 0.0 130.94 0.38 ;
+ END
+ END din0[3]
+ PIN din0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 136.0 0.0 136.38 0.38 ;
+ END
+ END din0[4]
+ PIN din0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 141.44 0.0 141.82 0.38 ;
+ END
+ END din0[5]
+ PIN din0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 148.24 0.0 148.62 0.38 ;
+ END
+ END din0[6]
+ PIN din0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 154.36 0.0 154.74 0.38 ;
+ END
+ END din0[7]
+ PIN din0[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 159.8 0.0 160.18 0.38 ;
+ END
+ END din0[8]
+ PIN din0[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 165.24 0.0 165.62 0.38 ;
+ END
+ END din0[9]
+ PIN din0[10]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 170.68 0.0 171.06 0.38 ;
+ END
+ END din0[10]
+ PIN din0[11]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 177.48 0.0 177.86 0.38 ;
+ END
+ END din0[11]
+ PIN din0[12]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 182.92 0.0 183.3 0.38 ;
+ END
+ END din0[12]
+ PIN din0[13]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 188.36 0.0 188.74 0.38 ;
+ END
+ END din0[13]
+ PIN din0[14]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 195.16 0.0 195.54 0.38 ;
+ END
+ END din0[14]
+ PIN din0[15]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 201.28 0.0 201.66 0.38 ;
+ END
+ END din0[15]
+ PIN din0[16]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 206.72 0.0 207.1 0.38 ;
+ END
+ END din0[16]
+ PIN din0[17]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 212.16 0.0 212.54 0.38 ;
+ END
+ END din0[17]
+ PIN din0[18]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 217.6 0.0 217.98 0.38 ;
+ END
+ END din0[18]
+ PIN din0[19]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 224.4 0.0 224.78 0.38 ;
+ END
+ END din0[19]
+ PIN din0[20]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 229.84 0.0 230.22 0.38 ;
+ END
+ END din0[20]
+ PIN din0[21]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 235.96 0.0 236.34 0.38 ;
+ END
+ END din0[21]
+ PIN din0[22]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 241.4 0.0 241.78 0.38 ;
+ END
+ END din0[22]
+ PIN din0[23]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 246.84 0.0 247.22 0.38 ;
+ END
+ END din0[23]
+ PIN din0[24]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 253.64 0.0 254.02 0.38 ;
+ END
+ END din0[24]
+ PIN din0[25]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 259.08 0.0 259.46 0.38 ;
+ END
+ END din0[25]
+ PIN din0[26]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 264.52 0.0 264.9 0.38 ;
+ END
+ END din0[26]
+ PIN din0[27]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 269.96 0.0 270.34 0.38 ;
+ END
+ END din0[27]
+ PIN din0[28]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 276.76 0.0 277.14 0.38 ;
+ END
+ END din0[28]
+ PIN din0[29]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 282.88 0.0 283.26 0.38 ;
+ END
+ END din0[29]
+ PIN din0[30]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 288.32 0.0 288.7 0.38 ;
+ END
+ END din0[30]
+ PIN din0[31]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 293.76 0.0 294.14 0.38 ;
+ END
+ END din0[31]
+ PIN addr0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 78.2 0.0 78.58 0.38 ;
+ END
+ END addr0[0]
+ PIN addr0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 83.64 0.0 84.02 0.38 ;
+ END
+ END addr0[1]
+ PIN addr0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 139.4 0.38 139.78 ;
+ END
+ END addr0[2]
+ PIN addr0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 148.24 0.38 148.62 ;
+ END
+ END addr0[3]
+ PIN addr0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 154.36 0.38 154.74 ;
+ END
+ END addr0[4]
+ PIN addr0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 162.52 0.38 162.9 ;
+ END
+ END addr0[5]
+ PIN addr0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 167.96 0.38 168.34 ;
+ END
+ END addr0[6]
+ PIN addr0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 177.48 0.38 177.86 ;
+ END
+ END addr0[7]
+ PIN addr0[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 182.92 0.38 183.3 ;
+ END
+ END addr0[8]
+ PIN addr1[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 596.36 412.76 596.74 413.14 ;
+ END
+ END addr1[0]
+ PIN addr1[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 590.24 412.76 590.62 413.14 ;
+ END
+ END addr1[1]
+ PIN addr1[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 678.64 95.2 679.02 95.58 ;
+ END
+ END addr1[2]
+ PIN addr1[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 678.64 87.04 679.02 87.42 ;
+ END
+ END addr1[3]
+ PIN addr1[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 678.64 80.24 679.02 80.62 ;
+ END
+ END addr1[4]
+ PIN addr1[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 678.64 72.76 679.02 73.14 ;
+ END
+ END addr1[5]
+ PIN addr1[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 678.64 66.64 679.02 67.02 ;
+ END
+ END addr1[6]
+ PIN addr1[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 614.04 0.0 614.42 0.38 ;
+ END
+ END addr1[7]
+ PIN addr1[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 614.72 0.0 615.1 0.38 ;
+ END
+ END addr1[8]
+ PIN csb0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 38.76 0.38 39.14 ;
+ END
+ END csb0
+ PIN csb1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 678.64 394.4 679.02 394.78 ;
+ END
+ END csb1
+ PIN web0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 48.28 0.38 48.66 ;
+ END
+ END web0
+ PIN clk0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 40.12 0.38 40.5 ;
+ END
+ END clk0
+ PIN clk1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 652.12 412.76 652.5 413.14 ;
+ END
+ END clk1
+ PIN wmask0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 89.08 0.0 89.46 0.38 ;
+ END
+ END wmask0[0]
+ PIN wmask0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 95.88 0.0 96.26 0.38 ;
+ END
+ END wmask0[1]
+ PIN wmask0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 100.64 0.0 101.02 0.38 ;
+ END
+ END wmask0[2]
+ PIN wmask0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 106.76 0.0 107.14 0.38 ;
+ END
+ END wmask0[3]
+ PIN dout0[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 139.4 0.0 139.78 0.38 ;
+ END
+ END dout0[0]
+ PIN dout0[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 151.64 0.0 152.02 0.38 ;
+ END
+ END dout0[1]
+ PIN dout0[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 165.92 0.0 166.3 0.38 ;
+ END
+ END dout0[2]
+ PIN dout0[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 178.16 0.0 178.54 0.38 ;
+ END
+ END dout0[3]
+ PIN dout0[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 190.4 0.0 190.78 0.38 ;
+ END
+ END dout0[4]
+ PIN dout0[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 203.32 0.0 203.7 0.38 ;
+ END
+ END dout0[5]
+ PIN dout0[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 215.56 0.0 215.94 0.38 ;
+ END
+ END dout0[6]
+ PIN dout0[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 227.8 0.0 228.18 0.38 ;
+ END
+ END dout0[7]
+ PIN dout0[8]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 239.36 0.0 239.74 0.38 ;
+ END
+ END dout0[8]
+ PIN dout0[9]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 252.96 0.0 253.34 0.38 ;
+ END
+ END dout0[9]
+ PIN dout0[10]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 265.88 0.0 266.26 0.38 ;
+ END
+ END dout0[10]
+ PIN dout0[11]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 278.12 0.0 278.5 0.38 ;
+ END
+ END dout0[11]
+ PIN dout0[12]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 290.36 0.0 290.74 0.38 ;
+ END
+ END dout0[12]
+ PIN dout0[13]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 302.6 0.0 302.98 0.38 ;
+ END
+ END dout0[13]
+ PIN dout0[14]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 315.52 0.0 315.9 0.38 ;
+ END
+ END dout0[14]
+ PIN dout0[15]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 327.76 0.0 328.14 0.38 ;
+ END
+ END dout0[15]
+ PIN dout0[16]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 339.32 0.0 339.7 0.38 ;
+ END
+ END dout0[16]
+ PIN dout0[17]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 352.92 0.0 353.3 0.38 ;
+ END
+ END dout0[17]
+ PIN dout0[18]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 365.16 0.0 365.54 0.38 ;
+ END
+ END dout0[18]
+ PIN dout0[19]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 377.4 0.0 377.78 0.38 ;
+ END
+ END dout0[19]
+ PIN dout0[20]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 390.32 0.0 390.7 0.38 ;
+ END
+ END dout0[20]
+ PIN dout0[21]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 402.56 0.0 402.94 0.38 ;
+ END
+ END dout0[21]
+ PIN dout0[22]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 415.48 0.0 415.86 0.38 ;
+ END
+ END dout0[22]
+ PIN dout0[23]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 427.72 0.0 428.1 0.38 ;
+ END
+ END dout0[23]
+ PIN dout0[24]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 440.64 0.0 441.02 0.38 ;
+ END
+ END dout0[24]
+ PIN dout0[25]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 452.88 0.0 453.26 0.38 ;
+ END
+ END dout0[25]
+ PIN dout0[26]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 465.12 0.0 465.5 0.38 ;
+ END
+ END dout0[26]
+ PIN dout0[27]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 477.36 0.0 477.74 0.38 ;
+ END
+ END dout0[27]
+ PIN dout0[28]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 490.28 0.0 490.66 0.38 ;
+ END
+ END dout0[28]
+ PIN dout0[29]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 502.52 0.0 502.9 0.38 ;
+ END
+ END dout0[29]
+ PIN dout0[30]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 514.76 0.0 515.14 0.38 ;
+ END
+ END dout0[30]
+ PIN dout0[31]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 527.68 0.0 528.06 0.38 ;
+ END
+ END dout0[31]
+ PIN dout1[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 141.44 412.76 141.82 413.14 ;
+ END
+ END dout1[0]
+ PIN dout1[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 153.0 412.76 153.38 413.14 ;
+ END
+ END dout1[1]
+ PIN dout1[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 165.24 412.76 165.62 413.14 ;
+ END
+ END dout1[2]
+ PIN dout1[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 178.84 412.76 179.22 413.14 ;
+ END
+ END dout1[3]
+ PIN dout1[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 190.4 412.76 190.78 413.14 ;
+ END
+ END dout1[4]
+ PIN dout1[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 203.32 412.76 203.7 413.14 ;
+ END
+ END dout1[5]
+ PIN dout1[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 215.56 412.76 215.94 413.14 ;
+ END
+ END dout1[6]
+ PIN dout1[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 228.48 412.76 228.86 413.14 ;
+ END
+ END dout1[7]
+ PIN dout1[8]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 240.72 412.76 241.1 413.14 ;
+ END
+ END dout1[8]
+ PIN dout1[9]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 253.64 412.76 254.02 413.14 ;
+ END
+ END dout1[9]
+ PIN dout1[10]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 265.88 412.76 266.26 413.14 ;
+ END
+ END dout1[10]
+ PIN dout1[11]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 278.8 412.76 279.18 413.14 ;
+ END
+ END dout1[11]
+ PIN dout1[12]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 290.36 412.76 290.74 413.14 ;
+ END
+ END dout1[12]
+ PIN dout1[13]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 302.6 412.76 302.98 413.14 ;
+ END
+ END dout1[13]
+ PIN dout1[14]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 316.2 412.76 316.58 413.14 ;
+ END
+ END dout1[14]
+ PIN dout1[15]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 328.44 412.76 328.82 413.14 ;
+ END
+ END dout1[15]
+ PIN dout1[16]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 340.68 412.76 341.06 413.14 ;
+ END
+ END dout1[16]
+ PIN dout1[17]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 352.92 412.76 353.3 413.14 ;
+ END
+ END dout1[17]
+ PIN dout1[18]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 365.84 412.76 366.22 413.14 ;
+ END
+ END dout1[18]
+ PIN dout1[19]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 377.4 412.76 377.78 413.14 ;
+ END
+ END dout1[19]
+ PIN dout1[20]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 391.0 412.76 391.38 413.14 ;
+ END
+ END dout1[20]
+ PIN dout1[21]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 403.24 412.76 403.62 413.14 ;
+ END
+ END dout1[21]
+ PIN dout1[22]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 415.48 412.76 415.86 413.14 ;
+ END
+ END dout1[22]
+ PIN dout1[23]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 427.72 412.76 428.1 413.14 ;
+ END
+ END dout1[23]
+ PIN dout1[24]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 439.96 412.76 440.34 413.14 ;
+ END
+ END dout1[24]
+ PIN dout1[25]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 452.88 412.76 453.26 413.14 ;
+ END
+ END dout1[25]
+ PIN dout1[26]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 465.8 412.76 466.18 413.14 ;
+ END
+ END dout1[26]
+ PIN dout1[27]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 478.04 412.76 478.42 413.14 ;
+ END
+ END dout1[27]
+ PIN dout1[28]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 490.28 412.76 490.66 413.14 ;
+ END
+ END dout1[28]
+ PIN dout1[29]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 503.2 412.76 503.58 413.14 ;
+ END
+ END dout1[29]
+ PIN dout1[30]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 514.76 412.76 515.14 413.14 ;
+ END
+ END dout1[30]
+ PIN dout1[31]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 528.36 412.76 528.74 413.14 ;
+ END
+ END dout1[31]
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met3 ;
+ RECT 1.36 1.36 677.66 3.1 ;
+ LAYER met4 ;
+ RECT 675.92 1.36 677.66 411.78 ;
+ LAYER met4 ;
+ RECT 1.36 1.36 3.1 411.78 ;
+ LAYER met3 ;
+ RECT 1.36 410.04 677.66 411.78 ;
+ END
+ END vccd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met3 ;
+ RECT 4.76 4.76 674.26 6.5 ;
+ LAYER met4 ;
+ RECT 4.76 4.76 6.5 408.38 ;
+ LAYER met3 ;
+ RECT 4.76 406.64 674.26 408.38 ;
+ LAYER met4 ;
+ RECT 672.52 4.76 674.26 408.38 ;
+ END
+ END vssd1
+ OBS
+ LAYER met1 ;
+ RECT 0.62 0.62 678.4 412.52 ;
+ LAYER met2 ;
+ RECT 0.62 0.62 678.4 412.52 ;
+ LAYER met3 ;
+ RECT 0.98 138.8 678.4 140.38 ;
+ RECT 0.62 140.38 0.98 147.64 ;
+ RECT 0.62 149.22 0.98 153.76 ;
+ RECT 0.62 155.34 0.98 161.92 ;
+ RECT 0.62 163.5 0.98 167.36 ;
+ RECT 0.62 168.94 0.98 176.88 ;
+ RECT 0.62 178.46 0.98 182.32 ;
+ RECT 0.98 94.6 678.04 96.18 ;
+ RECT 0.98 96.18 678.04 138.8 ;
+ RECT 678.04 96.18 678.4 138.8 ;
+ RECT 678.04 88.02 678.4 94.6 ;
+ RECT 678.04 81.22 678.4 86.44 ;
+ RECT 678.04 73.74 678.4 79.64 ;
+ RECT 678.04 67.62 678.4 72.16 ;
+ RECT 0.98 140.38 678.04 393.8 ;
+ RECT 0.98 393.8 678.04 395.38 ;
+ RECT 678.04 140.38 678.4 393.8 ;
+ RECT 0.62 49.26 0.98 138.8 ;
+ RECT 0.62 41.1 0.98 47.68 ;
+ RECT 0.98 0.62 678.04 0.76 ;
+ RECT 678.04 0.62 678.26 0.76 ;
+ RECT 678.04 3.7 678.26 66.04 ;
+ RECT 678.26 0.62 678.4 0.76 ;
+ RECT 678.26 0.76 678.4 3.7 ;
+ RECT 678.26 3.7 678.4 66.04 ;
+ RECT 0.62 0.62 0.76 0.76 ;
+ RECT 0.62 0.76 0.76 3.7 ;
+ RECT 0.62 3.7 0.76 38.16 ;
+ RECT 0.76 0.62 0.98 0.76 ;
+ RECT 0.76 3.7 0.98 38.16 ;
+ RECT 0.62 183.9 0.76 409.44 ;
+ RECT 0.62 409.44 0.76 412.38 ;
+ RECT 0.62 412.38 0.76 412.52 ;
+ RECT 0.76 183.9 0.98 409.44 ;
+ RECT 0.76 412.38 0.98 412.52 ;
+ RECT 0.98 412.38 678.04 412.52 ;
+ RECT 678.04 395.38 678.26 409.44 ;
+ RECT 678.04 412.38 678.26 412.52 ;
+ RECT 678.26 395.38 678.4 409.44 ;
+ RECT 678.26 409.44 678.4 412.38 ;
+ RECT 678.26 412.38 678.4 412.52 ;
+ RECT 0.98 3.7 4.16 4.16 ;
+ RECT 0.98 4.16 4.16 7.1 ;
+ RECT 0.98 7.1 4.16 94.6 ;
+ RECT 4.16 3.7 674.86 4.16 ;
+ RECT 4.16 7.1 674.86 94.6 ;
+ RECT 674.86 3.7 678.04 4.16 ;
+ RECT 674.86 4.16 678.04 7.1 ;
+ RECT 674.86 7.1 678.04 94.6 ;
+ RECT 0.98 395.38 4.16 406.04 ;
+ RECT 0.98 406.04 4.16 408.98 ;
+ RECT 0.98 408.98 4.16 409.44 ;
+ RECT 4.16 395.38 674.86 406.04 ;
+ RECT 4.16 408.98 674.86 409.44 ;
+ RECT 674.86 395.38 678.04 406.04 ;
+ RECT 674.86 406.04 678.04 408.98 ;
+ RECT 674.86 408.98 678.04 409.44 ;
+ LAYER met4 ;
+ RECT 112.96 0.98 114.54 412.52 ;
+ RECT 114.54 0.62 118.4 0.98 ;
+ RECT 119.98 0.62 124.52 0.98 ;
+ RECT 126.1 0.62 129.96 0.98 ;
+ RECT 131.54 0.62 135.4 0.98 ;
+ RECT 142.42 0.62 147.64 0.98 ;
+ RECT 155.34 0.62 159.2 0.98 ;
+ RECT 160.78 0.62 164.64 0.98 ;
+ RECT 171.66 0.62 176.88 0.98 ;
+ RECT 183.9 0.62 187.76 0.98 ;
+ RECT 196.14 0.62 200.68 0.98 ;
+ RECT 207.7 0.62 211.56 0.98 ;
+ RECT 218.58 0.62 223.8 0.98 ;
+ RECT 230.82 0.62 235.36 0.98 ;
+ RECT 242.38 0.62 246.24 0.98 ;
+ RECT 254.62 0.62 258.48 0.98 ;
+ RECT 260.06 0.62 263.92 0.98 ;
+ RECT 270.94 0.62 276.16 0.98 ;
+ RECT 283.86 0.62 287.72 0.98 ;
+ RECT 79.18 0.62 83.04 0.98 ;
+ RECT 114.54 0.98 595.76 412.16 ;
+ RECT 595.76 0.98 597.34 412.16 ;
+ RECT 591.22 412.16 595.76 412.52 ;
+ RECT 597.34 412.16 651.52 412.52 ;
+ RECT 84.62 0.62 88.48 0.98 ;
+ RECT 90.06 0.62 95.28 0.98 ;
+ RECT 96.86 0.62 100.04 0.98 ;
+ RECT 101.62 0.62 106.16 0.98 ;
+ RECT 107.74 0.62 112.96 0.98 ;
+ RECT 136.98 0.62 138.8 0.98 ;
+ RECT 140.38 0.62 140.84 0.98 ;
+ RECT 149.22 0.62 151.04 0.98 ;
+ RECT 152.62 0.62 153.76 0.98 ;
+ RECT 166.9 0.62 170.08 0.98 ;
+ RECT 179.14 0.62 182.32 0.98 ;
+ RECT 189.34 0.62 189.8 0.98 ;
+ RECT 191.38 0.62 194.56 0.98 ;
+ RECT 202.26 0.62 202.72 0.98 ;
+ RECT 204.3 0.62 206.12 0.98 ;
+ RECT 213.14 0.62 214.96 0.98 ;
+ RECT 216.54 0.62 217.0 0.98 ;
+ RECT 225.38 0.62 227.2 0.98 ;
+ RECT 228.78 0.62 229.24 0.98 ;
+ RECT 236.94 0.62 238.76 0.98 ;
+ RECT 240.34 0.62 240.8 0.98 ;
+ RECT 247.82 0.62 252.36 0.98 ;
+ RECT 266.86 0.62 269.36 0.98 ;
+ RECT 279.1 0.62 282.28 0.98 ;
+ RECT 289.3 0.62 289.76 0.98 ;
+ RECT 291.34 0.62 293.16 0.98 ;
+ RECT 294.74 0.62 302.0 0.98 ;
+ RECT 303.58 0.62 314.92 0.98 ;
+ RECT 316.5 0.62 327.16 0.98 ;
+ RECT 328.74 0.62 338.72 0.98 ;
+ RECT 340.3 0.62 352.32 0.98 ;
+ RECT 353.9 0.62 364.56 0.98 ;
+ RECT 366.14 0.62 376.8 0.98 ;
+ RECT 378.38 0.62 389.72 0.98 ;
+ RECT 391.3 0.62 401.96 0.98 ;
+ RECT 403.54 0.62 414.88 0.98 ;
+ RECT 416.46 0.62 427.12 0.98 ;
+ RECT 428.7 0.62 440.04 0.98 ;
+ RECT 441.62 0.62 452.28 0.98 ;
+ RECT 453.86 0.62 464.52 0.98 ;
+ RECT 466.1 0.62 476.76 0.98 ;
+ RECT 478.34 0.62 489.68 0.98 ;
+ RECT 491.26 0.62 501.92 0.98 ;
+ RECT 503.5 0.62 514.16 0.98 ;
+ RECT 515.74 0.62 527.08 0.98 ;
+ RECT 528.66 0.62 613.44 0.98 ;
+ RECT 114.54 412.16 140.84 412.52 ;
+ RECT 142.42 412.16 152.4 412.52 ;
+ RECT 153.98 412.16 164.64 412.52 ;
+ RECT 166.22 412.16 178.24 412.52 ;
+ RECT 179.82 412.16 189.8 412.52 ;
+ RECT 191.38 412.16 202.72 412.52 ;
+ RECT 204.3 412.16 214.96 412.52 ;
+ RECT 216.54 412.16 227.88 412.52 ;
+ RECT 229.46 412.16 240.12 412.52 ;
+ RECT 241.7 412.16 253.04 412.52 ;
+ RECT 254.62 412.16 265.28 412.52 ;
+ RECT 266.86 412.16 278.2 412.52 ;
+ RECT 279.78 412.16 289.76 412.52 ;
+ RECT 291.34 412.16 302.0 412.52 ;
+ RECT 303.58 412.16 315.6 412.52 ;
+ RECT 317.18 412.16 327.84 412.52 ;
+ RECT 329.42 412.16 340.08 412.52 ;
+ RECT 341.66 412.16 352.32 412.52 ;
+ RECT 353.9 412.16 365.24 412.52 ;
+ RECT 366.82 412.16 376.8 412.52 ;
+ RECT 378.38 412.16 390.4 412.52 ;
+ RECT 391.98 412.16 402.64 412.52 ;
+ RECT 404.22 412.16 414.88 412.52 ;
+ RECT 416.46 412.16 427.12 412.52 ;
+ RECT 428.7 412.16 439.36 412.52 ;
+ RECT 440.94 412.16 452.28 412.52 ;
+ RECT 453.86 412.16 465.2 412.52 ;
+ RECT 466.78 412.16 477.44 412.52 ;
+ RECT 479.02 412.16 489.68 412.52 ;
+ RECT 491.26 412.16 502.6 412.52 ;
+ RECT 504.18 412.16 514.16 412.52 ;
+ RECT 515.74 412.16 527.76 412.52 ;
+ RECT 529.34 412.16 589.64 412.52 ;
+ RECT 678.26 0.98 678.4 412.16 ;
+ RECT 615.7 0.62 675.32 0.76 ;
+ RECT 615.7 0.76 675.32 0.98 ;
+ RECT 675.32 0.62 678.26 0.76 ;
+ RECT 678.26 0.62 678.4 0.76 ;
+ RECT 678.26 0.76 678.4 0.98 ;
+ RECT 653.1 412.16 675.32 412.38 ;
+ RECT 653.1 412.38 675.32 412.52 ;
+ RECT 675.32 412.38 678.26 412.52 ;
+ RECT 678.26 412.16 678.4 412.38 ;
+ RECT 678.26 412.38 678.4 412.52 ;
+ RECT 0.62 0.98 0.76 412.38 ;
+ RECT 0.62 412.38 0.76 412.52 ;
+ RECT 0.76 412.38 3.7 412.52 ;
+ RECT 3.7 412.38 112.96 412.52 ;
+ RECT 0.62 0.62 0.76 0.76 ;
+ RECT 0.62 0.76 0.76 0.98 ;
+ RECT 0.76 0.62 3.7 0.76 ;
+ RECT 3.7 0.62 77.6 0.76 ;
+ RECT 3.7 0.76 77.6 0.98 ;
+ RECT 3.7 0.98 4.16 4.16 ;
+ RECT 3.7 4.16 4.16 408.98 ;
+ RECT 3.7 408.98 4.16 412.38 ;
+ RECT 4.16 0.98 7.1 4.16 ;
+ RECT 4.16 408.98 7.1 412.38 ;
+ RECT 7.1 0.98 112.96 4.16 ;
+ RECT 7.1 4.16 112.96 408.98 ;
+ RECT 7.1 408.98 112.96 412.38 ;
+ RECT 597.34 0.98 671.92 4.16 ;
+ RECT 597.34 4.16 671.92 408.98 ;
+ RECT 597.34 408.98 671.92 412.16 ;
+ RECT 671.92 0.98 674.86 4.16 ;
+ RECT 671.92 408.98 674.86 412.16 ;
+ RECT 674.86 0.98 675.32 4.16 ;
+ RECT 674.86 4.16 675.32 408.98 ;
+ RECT 674.86 408.98 675.32 412.16 ;
+ END
+END sky130_sram_2kbyte_1rw1r_32x512_8
+END LIBRARY
diff --git a/lef/sky130_sram_4kbyte_1rw1r_32x1024_8.lef b/lef/sky130_sram_4kbyte_1rw1r_32x1024_8.lef
new file mode 100644
index 0000000..508b91e
--- /dev/null
+++ b/lef/sky130_sram_4kbyte_1rw1r_32x1024_8.lef
@@ -0,0 +1,1123 @@
+VERSION 5.4 ;
+NAMESCASESENSITIVE ON ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+UNITS
+ DATABASE MICRONS 2000 ;
+END UNITS
+MACRO sky130_sram_4kbyte_1rw1r_32x1024_8
+ CLASS BLOCK ;
+ SIZE 689.9 BY 666.1 ;
+ SYMMETRY X Y R90 ;
+ PIN din0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 116.28 0.0 116.66 0.38 ;
+ END
+ END din0[0]
+ PIN din0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 121.72 0.0 122.1 0.38 ;
+ END
+ END din0[1]
+ PIN din0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 127.84 0.0 128.22 0.38 ;
+ END
+ END din0[2]
+ PIN din0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 133.28 0.0 133.66 0.38 ;
+ END
+ END din0[3]
+ PIN din0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 138.72 0.0 139.1 0.38 ;
+ END
+ END din0[4]
+ PIN din0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 144.16 0.0 144.54 0.38 ;
+ END
+ END din0[5]
+ PIN din0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 150.96 0.0 151.34 0.38 ;
+ END
+ END din0[6]
+ PIN din0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 157.08 0.0 157.46 0.38 ;
+ END
+ END din0[7]
+ PIN din0[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 162.52 0.0 162.9 0.38 ;
+ END
+ END din0[8]
+ PIN din0[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 167.96 0.0 168.34 0.38 ;
+ END
+ END din0[9]
+ PIN din0[10]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 173.4 0.0 173.78 0.38 ;
+ END
+ END din0[10]
+ PIN din0[11]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 180.2 0.0 180.58 0.38 ;
+ END
+ END din0[11]
+ PIN din0[12]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 185.64 0.0 186.02 0.38 ;
+ END
+ END din0[12]
+ PIN din0[13]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 191.08 0.0 191.46 0.38 ;
+ END
+ END din0[13]
+ PIN din0[14]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 197.88 0.0 198.26 0.38 ;
+ END
+ END din0[14]
+ PIN din0[15]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 204.0 0.0 204.38 0.38 ;
+ END
+ END din0[15]
+ PIN din0[16]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 209.44 0.0 209.82 0.38 ;
+ END
+ END din0[16]
+ PIN din0[17]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 214.88 0.0 215.26 0.38 ;
+ END
+ END din0[17]
+ PIN din0[18]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 220.32 0.0 220.7 0.38 ;
+ END
+ END din0[18]
+ PIN din0[19]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 227.12 0.0 227.5 0.38 ;
+ END
+ END din0[19]
+ PIN din0[20]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 232.56 0.0 232.94 0.38 ;
+ END
+ END din0[20]
+ PIN din0[21]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 238.68 0.0 239.06 0.38 ;
+ END
+ END din0[21]
+ PIN din0[22]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 244.12 0.0 244.5 0.38 ;
+ END
+ END din0[22]
+ PIN din0[23]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 249.56 0.0 249.94 0.38 ;
+ END
+ END din0[23]
+ PIN din0[24]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 256.36 0.0 256.74 0.38 ;
+ END
+ END din0[24]
+ PIN din0[25]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 261.8 0.0 262.18 0.38 ;
+ END
+ END din0[25]
+ PIN din0[26]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 267.24 0.0 267.62 0.38 ;
+ END
+ END din0[26]
+ PIN din0[27]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 272.68 0.0 273.06 0.38 ;
+ END
+ END din0[27]
+ PIN din0[28]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 279.48 0.0 279.86 0.38 ;
+ END
+ END din0[28]
+ PIN din0[29]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 285.6 0.0 285.98 0.38 ;
+ END
+ END din0[29]
+ PIN din0[30]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 291.04 0.0 291.42 0.38 ;
+ END
+ END din0[30]
+ PIN din0[31]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 296.48 0.0 296.86 0.38 ;
+ END
+ END din0[31]
+ PIN addr0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 80.92 0.0 81.3 0.38 ;
+ END
+ END addr0[0]
+ PIN addr0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 86.36 0.0 86.74 0.38 ;
+ END
+ END addr0[1]
+ PIN addr0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 147.56 0.38 147.94 ;
+ END
+ END addr0[2]
+ PIN addr0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 155.72 0.38 156.1 ;
+ END
+ END addr0[3]
+ PIN addr0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 162.52 0.38 162.9 ;
+ END
+ END addr0[4]
+ PIN addr0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 171.36 0.38 171.74 ;
+ END
+ END addr0[5]
+ PIN addr0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 176.12 0.38 176.5 ;
+ END
+ END addr0[6]
+ PIN addr0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 184.28 0.38 184.66 ;
+ END
+ END addr0[7]
+ PIN addr0[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 189.72 0.38 190.1 ;
+ END
+ END addr0[8]
+ PIN addr0[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 199.24 0.38 199.62 ;
+ END
+ END addr0[9]
+ PIN addr1[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 603.84 665.72 604.22 666.1 ;
+ END
+ END addr1[0]
+ PIN addr1[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 597.72 665.72 598.1 666.1 ;
+ END
+ END addr1[1]
+ PIN addr1[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 689.52 95.2 689.9 95.58 ;
+ END
+ END addr1[2]
+ PIN addr1[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 689.52 87.04 689.9 87.42 ;
+ END
+ END addr1[3]
+ PIN addr1[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 689.52 80.92 689.9 81.3 ;
+ END
+ END addr1[4]
+ PIN addr1[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 689.52 72.08 689.9 72.46 ;
+ END
+ END addr1[5]
+ PIN addr1[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 622.2 0.0 622.58 0.38 ;
+ END
+ END addr1[6]
+ PIN addr1[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 620.16 0.0 620.54 0.38 ;
+ END
+ END addr1[7]
+ PIN addr1[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 620.84 0.0 621.22 0.38 ;
+ END
+ END addr1[8]
+ PIN addr1[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 621.52 0.0 621.9 0.38 ;
+ END
+ END addr1[9]
+ PIN csb0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 38.76 0.38 39.14 ;
+ END
+ END csb0
+ PIN csb1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 689.52 648.04 689.9 648.42 ;
+ END
+ END csb1
+ PIN web0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 47.6 0.38 47.98 ;
+ END
+ END web0
+ PIN clk0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 40.12 0.38 40.5 ;
+ END
+ END clk0
+ PIN clk1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 661.64 665.72 662.02 666.1 ;
+ END
+ END clk1
+ PIN wmask0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 91.8 0.0 92.18 0.38 ;
+ END
+ END wmask0[0]
+ PIN wmask0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 98.6 0.0 98.98 0.38 ;
+ END
+ END wmask0[1]
+ PIN wmask0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 103.36 0.0 103.74 0.38 ;
+ END
+ END wmask0[2]
+ PIN wmask0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 109.48 0.0 109.86 0.38 ;
+ END
+ END wmask0[3]
+ PIN dout0[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 142.8 0.0 143.18 0.38 ;
+ END
+ END dout0[0]
+ PIN dout0[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 157.76 0.0 158.14 0.38 ;
+ END
+ END dout0[1]
+ PIN dout0[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 170.0 0.0 170.38 0.38 ;
+ END
+ END dout0[2]
+ PIN dout0[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 182.92 0.0 183.3 0.38 ;
+ END
+ END dout0[3]
+ PIN dout0[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 195.16 0.0 195.54 0.38 ;
+ END
+ END dout0[4]
+ PIN dout0[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 206.72 0.0 207.1 0.38 ;
+ END
+ END dout0[5]
+ PIN dout0[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 218.96 0.0 219.34 0.38 ;
+ END
+ END dout0[6]
+ PIN dout0[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 230.52 0.0 230.9 0.38 ;
+ END
+ END dout0[7]
+ PIN dout0[8]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 247.52 0.0 247.9 0.38 ;
+ END
+ END dout0[8]
+ PIN dout0[9]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 257.72 0.0 258.1 0.38 ;
+ END
+ END dout0[9]
+ PIN dout0[10]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 270.64 0.0 271.02 0.38 ;
+ END
+ END dout0[10]
+ PIN dout0[11]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 282.88 0.0 283.26 0.38 ;
+ END
+ END dout0[11]
+ PIN dout0[12]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 294.44 0.0 294.82 0.38 ;
+ END
+ END dout0[12]
+ PIN dout0[13]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 307.36 0.0 307.74 0.38 ;
+ END
+ END dout0[13]
+ PIN dout0[14]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 320.28 0.0 320.66 0.38 ;
+ END
+ END dout0[14]
+ PIN dout0[15]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 332.52 0.0 332.9 0.38 ;
+ END
+ END dout0[15]
+ PIN dout0[16]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 345.44 0.0 345.82 0.38 ;
+ END
+ END dout0[16]
+ PIN dout0[17]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 357.68 0.0 358.06 0.38 ;
+ END
+ END dout0[17]
+ PIN dout0[18]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 369.92 0.0 370.3 0.38 ;
+ END
+ END dout0[18]
+ PIN dout0[19]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 382.16 0.0 382.54 0.38 ;
+ END
+ END dout0[19]
+ PIN dout0[20]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 395.08 0.0 395.46 0.38 ;
+ END
+ END dout0[20]
+ PIN dout0[21]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 407.32 0.0 407.7 0.38 ;
+ END
+ END dout0[21]
+ PIN dout0[22]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 419.56 0.0 419.94 0.38 ;
+ END
+ END dout0[22]
+ PIN dout0[23]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 432.48 0.0 432.86 0.38 ;
+ END
+ END dout0[23]
+ PIN dout0[24]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 443.36 0.0 443.74 0.38 ;
+ END
+ END dout0[24]
+ PIN dout0[25]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 457.64 0.0 458.02 0.38 ;
+ END
+ END dout0[25]
+ PIN dout0[26]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 469.88 0.0 470.26 0.38 ;
+ END
+ END dout0[26]
+ PIN dout0[27]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 482.12 0.0 482.5 0.38 ;
+ END
+ END dout0[27]
+ PIN dout0[28]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 495.04 0.0 495.42 0.38 ;
+ END
+ END dout0[28]
+ PIN dout0[29]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 507.28 0.0 507.66 0.38 ;
+ END
+ END dout0[29]
+ PIN dout0[30]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 519.52 0.0 519.9 0.38 ;
+ END
+ END dout0[30]
+ PIN dout0[31]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 532.44 0.0 532.82 0.38 ;
+ END
+ END dout0[31]
+ PIN dout1[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 146.2 665.72 146.58 666.1 ;
+ END
+ END dout1[0]
+ PIN dout1[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 157.76 665.72 158.14 666.1 ;
+ END
+ END dout1[1]
+ PIN dout1[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 170.68 665.72 171.06 666.1 ;
+ END
+ END dout1[2]
+ PIN dout1[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 182.92 665.72 183.3 666.1 ;
+ END
+ END dout1[3]
+ PIN dout1[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 195.84 665.72 196.22 666.1 ;
+ END
+ END dout1[4]
+ PIN dout1[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 208.08 665.72 208.46 666.1 ;
+ END
+ END dout1[5]
+ PIN dout1[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 221.0 665.72 221.38 666.1 ;
+ END
+ END dout1[6]
+ PIN dout1[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 233.24 665.72 233.62 666.1 ;
+ END
+ END dout1[7]
+ PIN dout1[8]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 245.48 665.72 245.86 666.1 ;
+ END
+ END dout1[8]
+ PIN dout1[9]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 257.72 665.72 258.1 666.1 ;
+ END
+ END dout1[9]
+ PIN dout1[10]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 269.96 665.72 270.34 666.1 ;
+ END
+ END dout1[10]
+ PIN dout1[11]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 282.88 665.72 283.26 666.1 ;
+ END
+ END dout1[11]
+ PIN dout1[12]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 295.8 665.72 296.18 666.1 ;
+ END
+ END dout1[12]
+ PIN dout1[13]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 308.04 665.72 308.42 666.1 ;
+ END
+ END dout1[13]
+ PIN dout1[14]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 320.96 665.72 321.34 666.1 ;
+ END
+ END dout1[14]
+ PIN dout1[15]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 333.2 665.72 333.58 666.1 ;
+ END
+ END dout1[15]
+ PIN dout1[16]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 344.76 665.72 345.14 666.1 ;
+ END
+ END dout1[16]
+ PIN dout1[17]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 358.36 665.72 358.74 666.1 ;
+ END
+ END dout1[17]
+ PIN dout1[18]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 369.92 665.72 370.3 666.1 ;
+ END
+ END dout1[18]
+ PIN dout1[19]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 382.84 665.72 383.22 666.1 ;
+ END
+ END dout1[19]
+ PIN dout1[20]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 395.08 665.72 395.46 666.1 ;
+ END
+ END dout1[20]
+ PIN dout1[21]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 408.0 665.72 408.38 666.1 ;
+ END
+ END dout1[21]
+ PIN dout1[22]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 420.24 665.72 420.62 666.1 ;
+ END
+ END dout1[22]
+ PIN dout1[23]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 433.16 665.72 433.54 666.1 ;
+ END
+ END dout1[23]
+ PIN dout1[24]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 445.4 665.72 445.78 666.1 ;
+ END
+ END dout1[24]
+ PIN dout1[25]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 457.64 665.72 458.02 666.1 ;
+ END
+ END dout1[25]
+ PIN dout1[26]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 469.88 665.72 470.26 666.1 ;
+ END
+ END dout1[26]
+ PIN dout1[27]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 482.12 665.72 482.5 666.1 ;
+ END
+ END dout1[27]
+ PIN dout1[28]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 495.04 665.72 495.42 666.1 ;
+ END
+ END dout1[28]
+ PIN dout1[29]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 507.96 665.72 508.34 666.1 ;
+ END
+ END dout1[29]
+ PIN dout1[30]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 520.2 665.72 520.58 666.1 ;
+ END
+ END dout1[30]
+ PIN dout1[31]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 533.12 665.72 533.5 666.1 ;
+ END
+ END dout1[31]
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met3 ;
+ RECT 1.36 663.0 688.54 664.74 ;
+ LAYER met4 ;
+ RECT 1.36 1.36 3.1 664.74 ;
+ LAYER met4 ;
+ RECT 686.8 1.36 688.54 664.74 ;
+ LAYER met3 ;
+ RECT 1.36 1.36 688.54 3.1 ;
+ END
+ END vccd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met4 ;
+ RECT 683.4 4.76 685.14 661.34 ;
+ LAYER met4 ;
+ RECT 4.76 4.76 6.5 661.34 ;
+ LAYER met3 ;
+ RECT 4.76 4.76 685.14 6.5 ;
+ LAYER met3 ;
+ RECT 4.76 659.6 685.14 661.34 ;
+ END
+ END vssd1
+ OBS
+ LAYER met1 ;
+ RECT 0.62 0.62 689.28 665.48 ;
+ LAYER met2 ;
+ RECT 0.62 0.62 689.28 665.48 ;
+ LAYER met3 ;
+ RECT 0.98 146.96 689.28 148.54 ;
+ RECT 0.62 148.54 0.98 155.12 ;
+ RECT 0.62 156.7 0.98 161.92 ;
+ RECT 0.62 163.5 0.98 170.76 ;
+ RECT 0.62 172.34 0.98 175.52 ;
+ RECT 0.62 177.1 0.98 183.68 ;
+ RECT 0.62 185.26 0.98 189.12 ;
+ RECT 0.62 190.7 0.98 198.64 ;
+ RECT 0.98 94.6 688.92 96.18 ;
+ RECT 0.98 96.18 688.92 146.96 ;
+ RECT 688.92 96.18 689.28 146.96 ;
+ RECT 688.92 88.02 689.28 94.6 ;
+ RECT 688.92 81.9 689.28 86.44 ;
+ RECT 688.92 73.06 689.28 80.32 ;
+ RECT 0.98 148.54 688.92 647.44 ;
+ RECT 0.98 647.44 688.92 649.02 ;
+ RECT 688.92 148.54 689.28 647.44 ;
+ RECT 0.62 48.58 0.98 146.96 ;
+ RECT 0.62 41.1 0.98 47.0 ;
+ RECT 0.62 200.22 0.76 662.4 ;
+ RECT 0.62 662.4 0.76 665.34 ;
+ RECT 0.62 665.34 0.76 665.48 ;
+ RECT 0.76 200.22 0.98 662.4 ;
+ RECT 0.76 665.34 0.98 665.48 ;
+ RECT 0.98 665.34 688.92 665.48 ;
+ RECT 688.92 649.02 689.14 662.4 ;
+ RECT 688.92 665.34 689.14 665.48 ;
+ RECT 689.14 649.02 689.28 662.4 ;
+ RECT 689.14 662.4 689.28 665.34 ;
+ RECT 689.14 665.34 689.28 665.48 ;
+ RECT 0.98 0.62 688.92 0.76 ;
+ RECT 688.92 0.62 689.14 0.76 ;
+ RECT 688.92 3.7 689.14 71.48 ;
+ RECT 689.14 0.62 689.28 0.76 ;
+ RECT 689.14 0.76 689.28 3.7 ;
+ RECT 689.14 3.7 689.28 71.48 ;
+ RECT 0.62 0.62 0.76 0.76 ;
+ RECT 0.62 0.76 0.76 3.7 ;
+ RECT 0.62 3.7 0.76 38.16 ;
+ RECT 0.76 0.62 0.98 0.76 ;
+ RECT 0.76 3.7 0.98 38.16 ;
+ RECT 0.98 3.7 4.16 4.16 ;
+ RECT 0.98 4.16 4.16 7.1 ;
+ RECT 0.98 7.1 4.16 94.6 ;
+ RECT 4.16 3.7 685.74 4.16 ;
+ RECT 4.16 7.1 685.74 94.6 ;
+ RECT 685.74 3.7 688.92 4.16 ;
+ RECT 685.74 4.16 688.92 7.1 ;
+ RECT 685.74 7.1 688.92 94.6 ;
+ RECT 0.98 649.02 4.16 659.0 ;
+ RECT 0.98 659.0 4.16 661.94 ;
+ RECT 0.98 661.94 4.16 662.4 ;
+ RECT 4.16 649.02 685.74 659.0 ;
+ RECT 4.16 661.94 685.74 662.4 ;
+ RECT 685.74 649.02 688.92 659.0 ;
+ RECT 685.74 659.0 688.92 661.94 ;
+ RECT 685.74 661.94 688.92 662.4 ;
+ LAYER met4 ;
+ RECT 115.68 0.98 117.26 665.48 ;
+ RECT 117.26 0.62 121.12 0.98 ;
+ RECT 122.7 0.62 127.24 0.98 ;
+ RECT 128.82 0.62 132.68 0.98 ;
+ RECT 134.26 0.62 138.12 0.98 ;
+ RECT 145.14 0.62 150.36 0.98 ;
+ RECT 151.94 0.62 156.48 0.98 ;
+ RECT 163.5 0.62 167.36 0.98 ;
+ RECT 174.38 0.62 179.6 0.98 ;
+ RECT 186.62 0.62 190.48 0.98 ;
+ RECT 198.86 0.62 203.4 0.98 ;
+ RECT 210.42 0.62 214.28 0.98 ;
+ RECT 221.3 0.62 226.52 0.98 ;
+ RECT 233.54 0.62 238.08 0.98 ;
+ RECT 239.66 0.62 243.52 0.98 ;
+ RECT 250.54 0.62 255.76 0.98 ;
+ RECT 262.78 0.62 266.64 0.98 ;
+ RECT 273.66 0.62 278.88 0.98 ;
+ RECT 286.58 0.62 290.44 0.98 ;
+ RECT 81.9 0.62 85.76 0.98 ;
+ RECT 117.26 0.98 603.24 665.12 ;
+ RECT 603.24 0.98 604.82 665.12 ;
+ RECT 598.7 665.12 603.24 665.48 ;
+ RECT 604.82 665.12 661.04 665.48 ;
+ RECT 87.34 0.62 91.2 0.98 ;
+ RECT 92.78 0.62 98.0 0.98 ;
+ RECT 99.58 0.62 102.76 0.98 ;
+ RECT 104.34 0.62 108.88 0.98 ;
+ RECT 110.46 0.62 115.68 0.98 ;
+ RECT 139.7 0.62 142.2 0.98 ;
+ RECT 158.74 0.62 161.92 0.98 ;
+ RECT 168.94 0.62 169.4 0.98 ;
+ RECT 170.98 0.62 172.8 0.98 ;
+ RECT 181.18 0.62 182.32 0.98 ;
+ RECT 183.9 0.62 185.04 0.98 ;
+ RECT 192.06 0.62 194.56 0.98 ;
+ RECT 196.14 0.62 197.28 0.98 ;
+ RECT 204.98 0.62 206.12 0.98 ;
+ RECT 207.7 0.62 208.84 0.98 ;
+ RECT 215.86 0.62 218.36 0.98 ;
+ RECT 228.1 0.62 229.92 0.98 ;
+ RECT 231.5 0.62 231.96 0.98 ;
+ RECT 245.1 0.62 246.92 0.98 ;
+ RECT 248.5 0.62 248.96 0.98 ;
+ RECT 258.7 0.62 261.2 0.98 ;
+ RECT 268.22 0.62 270.04 0.98 ;
+ RECT 271.62 0.62 272.08 0.98 ;
+ RECT 280.46 0.62 282.28 0.98 ;
+ RECT 283.86 0.62 285.0 0.98 ;
+ RECT 292.02 0.62 293.84 0.98 ;
+ RECT 295.42 0.62 295.88 0.98 ;
+ RECT 297.46 0.62 306.76 0.98 ;
+ RECT 308.34 0.62 319.68 0.98 ;
+ RECT 321.26 0.62 331.92 0.98 ;
+ RECT 333.5 0.62 344.84 0.98 ;
+ RECT 346.42 0.62 357.08 0.98 ;
+ RECT 358.66 0.62 369.32 0.98 ;
+ RECT 370.9 0.62 381.56 0.98 ;
+ RECT 383.14 0.62 394.48 0.98 ;
+ RECT 396.06 0.62 406.72 0.98 ;
+ RECT 408.3 0.62 418.96 0.98 ;
+ RECT 420.54 0.62 431.88 0.98 ;
+ RECT 433.46 0.62 442.76 0.98 ;
+ RECT 444.34 0.62 457.04 0.98 ;
+ RECT 458.62 0.62 469.28 0.98 ;
+ RECT 470.86 0.62 481.52 0.98 ;
+ RECT 483.1 0.62 494.44 0.98 ;
+ RECT 496.02 0.62 506.68 0.98 ;
+ RECT 508.26 0.62 518.92 0.98 ;
+ RECT 520.5 0.62 531.84 0.98 ;
+ RECT 533.42 0.62 619.56 0.98 ;
+ RECT 117.26 665.12 145.6 665.48 ;
+ RECT 147.18 665.12 157.16 665.48 ;
+ RECT 158.74 665.12 170.08 665.48 ;
+ RECT 171.66 665.12 182.32 665.48 ;
+ RECT 183.9 665.12 195.24 665.48 ;
+ RECT 196.82 665.12 207.48 665.48 ;
+ RECT 209.06 665.12 220.4 665.48 ;
+ RECT 221.98 665.12 232.64 665.48 ;
+ RECT 234.22 665.12 244.88 665.48 ;
+ RECT 246.46 665.12 257.12 665.48 ;
+ RECT 258.7 665.12 269.36 665.48 ;
+ RECT 270.94 665.12 282.28 665.48 ;
+ RECT 283.86 665.12 295.2 665.48 ;
+ RECT 296.78 665.12 307.44 665.48 ;
+ RECT 309.02 665.12 320.36 665.48 ;
+ RECT 321.94 665.12 332.6 665.48 ;
+ RECT 334.18 665.12 344.16 665.48 ;
+ RECT 345.74 665.12 357.76 665.48 ;
+ RECT 359.34 665.12 369.32 665.48 ;
+ RECT 370.9 665.12 382.24 665.48 ;
+ RECT 383.82 665.12 394.48 665.48 ;
+ RECT 396.06 665.12 407.4 665.48 ;
+ RECT 408.98 665.12 419.64 665.48 ;
+ RECT 421.22 665.12 432.56 665.48 ;
+ RECT 434.14 665.12 444.8 665.48 ;
+ RECT 446.38 665.12 457.04 665.48 ;
+ RECT 458.62 665.12 469.28 665.48 ;
+ RECT 470.86 665.12 481.52 665.48 ;
+ RECT 483.1 665.12 494.44 665.48 ;
+ RECT 496.02 665.12 507.36 665.48 ;
+ RECT 508.94 665.12 519.6 665.48 ;
+ RECT 521.18 665.12 532.52 665.48 ;
+ RECT 534.1 665.12 597.12 665.48 ;
+ RECT 0.62 0.98 0.76 665.34 ;
+ RECT 0.62 665.34 0.76 665.48 ;
+ RECT 0.76 665.34 3.7 665.48 ;
+ RECT 3.7 665.34 115.68 665.48 ;
+ RECT 0.62 0.62 0.76 0.76 ;
+ RECT 0.62 0.76 0.76 0.98 ;
+ RECT 0.76 0.62 3.7 0.76 ;
+ RECT 3.7 0.62 80.32 0.76 ;
+ RECT 3.7 0.76 80.32 0.98 ;
+ RECT 689.14 0.98 689.28 665.12 ;
+ RECT 623.18 0.62 686.2 0.76 ;
+ RECT 623.18 0.76 686.2 0.98 ;
+ RECT 686.2 0.62 689.14 0.76 ;
+ RECT 689.14 0.62 689.28 0.76 ;
+ RECT 689.14 0.76 689.28 0.98 ;
+ RECT 662.62 665.12 686.2 665.34 ;
+ RECT 662.62 665.34 686.2 665.48 ;
+ RECT 686.2 665.34 689.14 665.48 ;
+ RECT 689.14 665.12 689.28 665.34 ;
+ RECT 689.14 665.34 689.28 665.48 ;
+ RECT 604.82 0.98 682.8 4.16 ;
+ RECT 604.82 4.16 682.8 661.94 ;
+ RECT 604.82 661.94 682.8 665.12 ;
+ RECT 682.8 0.98 685.74 4.16 ;
+ RECT 682.8 661.94 685.74 665.12 ;
+ RECT 685.74 0.98 686.2 4.16 ;
+ RECT 685.74 4.16 686.2 661.94 ;
+ RECT 685.74 661.94 686.2 665.12 ;
+ RECT 3.7 0.98 4.16 4.16 ;
+ RECT 3.7 4.16 4.16 661.94 ;
+ RECT 3.7 661.94 4.16 665.34 ;
+ RECT 4.16 0.98 7.1 4.16 ;
+ RECT 4.16 661.94 7.1 665.34 ;
+ RECT 7.1 0.98 115.68 4.16 ;
+ RECT 7.1 4.16 115.68 661.94 ;
+ RECT 7.1 661.94 115.68 665.34 ;
+ END
+END sky130_sram_4kbyte_1rw1r_32x1024_8
+END LIBRARY
diff --git a/lef/sky130_sram_8kbyte_1rw1r_32x2048_8.lef b/lef/sky130_sram_8kbyte_1rw1r_32x2048_8.lef
new file mode 100644
index 0000000..6449e76
--- /dev/null
+++ b/lef/sky130_sram_8kbyte_1rw1r_32x2048_8.lef
@@ -0,0 +1,1144 @@
+VERSION 5.4 ;
+NAMESCASESENSITIVE ON ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+UNITS
+ DATABASE MICRONS 2000 ;
+END UNITS
+MACRO sky130_sram_8kbyte_1rw1r_32x2048_8
+ CLASS BLOCK ;
+ SIZE 1093.82 BY 720.5 ;
+ SYMMETRY X Y R90 ;
+ PIN din0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 123.08 0.0 123.46 0.38 ;
+ END
+ END din0[0]
+ PIN din0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 129.88 0.0 130.26 0.38 ;
+ END
+ END din0[1]
+ PIN din0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 135.32 0.0 135.7 0.38 ;
+ END
+ END din0[2]
+ PIN din0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 141.44 0.0 141.82 0.38 ;
+ END
+ END din0[3]
+ PIN din0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 146.2 0.0 146.58 0.38 ;
+ END
+ END din0[4]
+ PIN din0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 153.0 0.0 153.38 0.38 ;
+ END
+ END din0[5]
+ PIN din0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 158.44 0.0 158.82 0.38 ;
+ END
+ END din0[6]
+ PIN din0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 163.88 0.0 164.26 0.38 ;
+ END
+ END din0[7]
+ PIN din0[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 170.0 0.0 170.38 0.38 ;
+ END
+ END din0[8]
+ PIN din0[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 175.44 0.0 175.82 0.38 ;
+ END
+ END din0[9]
+ PIN din0[10]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 182.24 0.0 182.62 0.38 ;
+ END
+ END din0[10]
+ PIN din0[11]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 187.68 0.0 188.06 0.38 ;
+ END
+ END din0[11]
+ PIN din0[12]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 193.12 0.0 193.5 0.38 ;
+ END
+ END din0[12]
+ PIN din0[13]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 199.24 0.0 199.62 0.38 ;
+ END
+ END din0[13]
+ PIN din0[14]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 204.68 0.0 205.06 0.38 ;
+ END
+ END din0[14]
+ PIN din0[15]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 211.48 0.0 211.86 0.38 ;
+ END
+ END din0[15]
+ PIN din0[16]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 216.92 0.0 217.3 0.38 ;
+ END
+ END din0[16]
+ PIN din0[17]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 223.04 0.0 223.42 0.38 ;
+ END
+ END din0[17]
+ PIN din0[18]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 229.16 0.0 229.54 0.38 ;
+ END
+ END din0[18]
+ PIN din0[19]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 234.6 0.0 234.98 0.38 ;
+ END
+ END din0[19]
+ PIN din0[20]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 240.04 0.0 240.42 0.38 ;
+ END
+ END din0[20]
+ PIN din0[21]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 245.48 0.0 245.86 0.38 ;
+ END
+ END din0[21]
+ PIN din0[22]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 251.6 0.0 251.98 0.38 ;
+ END
+ END din0[22]
+ PIN din0[23]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 257.72 0.0 258.1 0.38 ;
+ END
+ END din0[23]
+ PIN din0[24]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 263.84 0.0 264.22 0.38 ;
+ END
+ END din0[24]
+ PIN din0[25]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 269.28 0.0 269.66 0.38 ;
+ END
+ END din0[25]
+ PIN din0[26]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 274.72 0.0 275.1 0.38 ;
+ END
+ END din0[26]
+ PIN din0[27]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 280.84 0.0 281.22 0.38 ;
+ END
+ END din0[27]
+ PIN din0[28]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 286.96 0.0 287.34 0.38 ;
+ END
+ END din0[28]
+ PIN din0[29]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 293.08 0.0 293.46 0.38 ;
+ END
+ END din0[29]
+ PIN din0[30]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 299.2 0.0 299.58 0.38 ;
+ END
+ END din0[30]
+ PIN din0[31]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 303.96 0.0 304.34 0.38 ;
+ END
+ END din0[31]
+ PIN addr0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 82.28 0.0 82.66 0.38 ;
+ END
+ END addr0[0]
+ PIN addr0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 88.4 0.0 88.78 0.38 ;
+ END
+ END addr0[1]
+ PIN addr0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 93.84 0.0 94.22 0.38 ;
+ END
+ END addr0[2]
+ PIN addr0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 174.08 0.38 174.46 ;
+ END
+ END addr0[3]
+ PIN addr0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 182.24 0.38 182.62 ;
+ END
+ END addr0[4]
+ PIN addr0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 189.04 0.38 189.42 ;
+ END
+ END addr0[5]
+ PIN addr0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 197.2 0.38 197.58 ;
+ END
+ END addr0[6]
+ PIN addr0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 202.64 0.38 203.02 ;
+ END
+ END addr0[7]
+ PIN addr0[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 210.8 0.38 211.18 ;
+ END
+ END addr0[8]
+ PIN addr0[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 216.24 0.38 216.62 ;
+ END
+ END addr0[9]
+ PIN addr0[10]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 225.76 0.38 226.14 ;
+ END
+ END addr0[10]
+ PIN addr1[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 1005.04 720.12 1005.42 720.5 ;
+ END
+ END addr1[0]
+ PIN addr1[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 999.6 720.12 999.98 720.5 ;
+ END
+ END addr1[1]
+ PIN addr1[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 992.8 720.12 993.18 720.5 ;
+ END
+ END addr1[2]
+ PIN addr1[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 121.04 1093.82 121.42 ;
+ END
+ END addr1[3]
+ PIN addr1[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 112.88 1093.82 113.26 ;
+ END
+ END addr1[4]
+ PIN addr1[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 107.44 1093.82 107.82 ;
+ END
+ END addr1[5]
+ PIN addr1[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 97.92 1093.82 98.3 ;
+ END
+ END addr1[6]
+ PIN addr1[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 92.48 1093.82 92.86 ;
+ END
+ END addr1[7]
+ PIN addr1[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 84.32 1093.82 84.7 ;
+ END
+ END addr1[8]
+ PIN addr1[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 78.88 1093.82 79.26 ;
+ END
+ END addr1[9]
+ PIN addr1[10]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 70.72 1093.82 71.1 ;
+ END
+ END addr1[10]
+ PIN csb0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 65.96 0.38 66.34 ;
+ END
+ END csb0
+ PIN csb1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 673.2 1093.82 673.58 ;
+ END
+ END csb1
+ PIN web0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 74.8 0.38 75.18 ;
+ END
+ END web0
+ PIN clk0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 66.64 0.38 67.02 ;
+ END
+ END clk0
+ PIN clk1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 672.52 1093.82 672.9 ;
+ END
+ END clk1
+ PIN wmask0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 99.96 0.0 100.34 0.38 ;
+ END
+ END wmask0[0]
+ PIN wmask0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 105.4 0.0 105.78 0.38 ;
+ END
+ END wmask0[1]
+ PIN wmask0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 111.52 0.0 111.9 0.38 ;
+ END
+ END wmask0[2]
+ PIN wmask0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 117.64 0.0 118.02 0.38 ;
+ END
+ END wmask0[3]
+ PIN dout0[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 144.84 0.0 145.22 0.38 ;
+ END
+ END dout0[0]
+ PIN dout0[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 172.72 0.0 173.1 0.38 ;
+ END
+ END dout0[1]
+ PIN dout0[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 197.2 0.0 197.58 0.38 ;
+ END
+ END dout0[2]
+ PIN dout0[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 221.0 0.0 221.38 0.38 ;
+ END
+ END dout0[3]
+ PIN dout0[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 247.52 0.0 247.9 0.38 ;
+ END
+ END dout0[4]
+ PIN dout0[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 272.68 0.0 273.06 0.38 ;
+ END
+ END dout0[5]
+ PIN dout0[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 296.48 0.0 296.86 0.38 ;
+ END
+ END dout0[6]
+ PIN dout0[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 322.32 0.0 322.7 0.38 ;
+ END
+ END dout0[7]
+ PIN dout0[8]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 347.48 0.0 347.86 0.38 ;
+ END
+ END dout0[8]
+ PIN dout0[9]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 371.96 0.0 372.34 0.38 ;
+ END
+ END dout0[9]
+ PIN dout0[10]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 397.12 0.0 397.5 0.38 ;
+ END
+ END dout0[10]
+ PIN dout0[11]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 421.6 0.0 421.98 0.38 ;
+ END
+ END dout0[11]
+ PIN dout0[12]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 446.76 0.0 447.14 0.38 ;
+ END
+ END dout0[12]
+ PIN dout0[13]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 471.92 0.0 472.3 0.38 ;
+ END
+ END dout0[13]
+ PIN dout0[14]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 497.08 0.0 497.46 0.38 ;
+ END
+ END dout0[14]
+ PIN dout0[15]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 521.56 0.0 521.94 0.38 ;
+ END
+ END dout0[15]
+ PIN dout0[16]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 545.36 0.0 545.74 0.38 ;
+ END
+ END dout0[16]
+ PIN dout0[17]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 571.88 0.0 572.26 0.38 ;
+ END
+ END dout0[17]
+ PIN dout0[18]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 596.36 0.0 596.74 0.38 ;
+ END
+ END dout0[18]
+ PIN dout0[19]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 621.52 0.0 621.9 0.38 ;
+ END
+ END dout0[19]
+ PIN dout0[20]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 646.68 0.0 647.06 0.38 ;
+ END
+ END dout0[20]
+ PIN dout0[21]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 671.84 0.0 672.22 0.38 ;
+ END
+ END dout0[21]
+ PIN dout0[22]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 696.32 0.0 696.7 0.38 ;
+ END
+ END dout0[22]
+ PIN dout0[23]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 721.48 0.0 721.86 0.38 ;
+ END
+ END dout0[23]
+ PIN dout0[24]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 745.28 0.0 745.66 0.38 ;
+ END
+ END dout0[24]
+ PIN dout0[25]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 771.12 0.0 771.5 0.38 ;
+ END
+ END dout0[25]
+ PIN dout0[26]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 796.28 0.0 796.66 0.38 ;
+ END
+ END dout0[26]
+ PIN dout0[27]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 821.44 0.0 821.82 0.38 ;
+ END
+ END dout0[27]
+ PIN dout0[28]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 845.92 0.0 846.3 0.38 ;
+ END
+ END dout0[28]
+ PIN dout0[29]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 871.08 0.0 871.46 0.38 ;
+ END
+ END dout0[29]
+ PIN dout0[30]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 896.24 0.0 896.62 0.38 ;
+ END
+ END dout0[30]
+ PIN dout0[31]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 921.4 0.0 921.78 0.38 ;
+ END
+ END dout0[31]
+ PIN dout1[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 147.56 720.12 147.94 720.5 ;
+ END
+ END dout1[0]
+ PIN dout1[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 172.04 720.12 172.42 720.5 ;
+ END
+ END dout1[1]
+ PIN dout1[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 197.2 720.12 197.58 720.5 ;
+ END
+ END dout1[2]
+ PIN dout1[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 222.36 720.12 222.74 720.5 ;
+ END
+ END dout1[3]
+ PIN dout1[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 247.52 720.12 247.9 720.5 ;
+ END
+ END dout1[4]
+ PIN dout1[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 272.68 720.12 273.06 720.5 ;
+ END
+ END dout1[5]
+ PIN dout1[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 297.16 720.12 297.54 720.5 ;
+ END
+ END dout1[6]
+ PIN dout1[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 322.32 720.12 322.7 720.5 ;
+ END
+ END dout1[7]
+ PIN dout1[8]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 347.48 720.12 347.86 720.5 ;
+ END
+ END dout1[8]
+ PIN dout1[9]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 372.64 720.12 373.02 720.5 ;
+ END
+ END dout1[9]
+ PIN dout1[10]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 397.8 720.12 398.18 720.5 ;
+ END
+ END dout1[10]
+ PIN dout1[11]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 421.6 720.12 421.98 720.5 ;
+ END
+ END dout1[11]
+ PIN dout1[12]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 446.76 720.12 447.14 720.5 ;
+ END
+ END dout1[12]
+ PIN dout1[13]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 472.6 720.12 472.98 720.5 ;
+ END
+ END dout1[13]
+ PIN dout1[14]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 497.08 720.12 497.46 720.5 ;
+ END
+ END dout1[14]
+ PIN dout1[15]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 521.56 720.12 521.94 720.5 ;
+ END
+ END dout1[15]
+ PIN dout1[16]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 546.72 720.12 547.1 720.5 ;
+ END
+ END dout1[16]
+ PIN dout1[17]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 571.88 720.12 572.26 720.5 ;
+ END
+ END dout1[17]
+ PIN dout1[18]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 596.36 720.12 596.74 720.5 ;
+ END
+ END dout1[18]
+ PIN dout1[19]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 621.52 720.12 621.9 720.5 ;
+ END
+ END dout1[19]
+ PIN dout1[20]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 646.68 720.12 647.06 720.5 ;
+ END
+ END dout1[20]
+ PIN dout1[21]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 671.84 720.12 672.22 720.5 ;
+ END
+ END dout1[21]
+ PIN dout1[22]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 697.0 720.12 697.38 720.5 ;
+ END
+ END dout1[22]
+ PIN dout1[23]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 721.48 720.12 721.86 720.5 ;
+ END
+ END dout1[23]
+ PIN dout1[24]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 746.64 720.12 747.02 720.5 ;
+ END
+ END dout1[24]
+ PIN dout1[25]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 771.8 720.12 772.18 720.5 ;
+ END
+ END dout1[25]
+ PIN dout1[26]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 796.96 720.12 797.34 720.5 ;
+ END
+ END dout1[26]
+ PIN dout1[27]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 822.12 720.12 822.5 720.5 ;
+ END
+ END dout1[27]
+ PIN dout1[28]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 845.92 720.12 846.3 720.5 ;
+ END
+ END dout1[28]
+ PIN dout1[29]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 871.08 720.12 871.46 720.5 ;
+ END
+ END dout1[29]
+ PIN dout1[30]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 896.92 720.12 897.3 720.5 ;
+ END
+ END dout1[30]
+ PIN dout1[31]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 921.4 720.12 921.78 720.5 ;
+ END
+ END dout1[31]
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met3 ;
+ RECT 1.36 1.36 1092.46 3.1 ;
+ LAYER met4 ;
+ RECT 1.36 1.36 3.1 719.14 ;
+ LAYER met3 ;
+ RECT 1.36 717.4 1092.46 719.14 ;
+ LAYER met4 ;
+ RECT 1090.72 1.36 1092.46 719.14 ;
+ END
+ END vccd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met3 ;
+ RECT 4.76 714.0 1089.06 715.74 ;
+ LAYER met4 ;
+ RECT 1087.32 4.76 1089.06 715.74 ;
+ LAYER met3 ;
+ RECT 4.76 4.76 1089.06 6.5 ;
+ LAYER met4 ;
+ RECT 4.76 4.76 6.5 715.74 ;
+ END
+ END vssd1
+ OBS
+ LAYER met1 ;
+ RECT 0.62 0.62 1093.2 719.88 ;
+ LAYER met2 ;
+ RECT 0.62 0.62 1093.2 719.88 ;
+ LAYER met3 ;
+ RECT 0.98 173.48 1093.2 175.06 ;
+ RECT 0.62 175.06 0.98 181.64 ;
+ RECT 0.62 183.22 0.98 188.44 ;
+ RECT 0.62 190.02 0.98 196.6 ;
+ RECT 0.62 198.18 0.98 202.04 ;
+ RECT 0.62 203.62 0.98 210.2 ;
+ RECT 0.62 211.78 0.98 215.64 ;
+ RECT 0.62 217.22 0.98 225.16 ;
+ RECT 0.98 120.44 1092.84 122.02 ;
+ RECT 0.98 122.02 1092.84 173.48 ;
+ RECT 1092.84 122.02 1093.2 173.48 ;
+ RECT 1092.84 113.86 1093.2 120.44 ;
+ RECT 1092.84 108.42 1093.2 112.28 ;
+ RECT 1092.84 98.9 1093.2 106.84 ;
+ RECT 1092.84 93.46 1093.2 97.32 ;
+ RECT 1092.84 85.3 1093.2 91.88 ;
+ RECT 1092.84 79.86 1093.2 83.72 ;
+ RECT 1092.84 71.7 1093.2 78.28 ;
+ RECT 0.98 175.06 1092.84 672.6 ;
+ RECT 0.98 672.6 1092.84 674.18 ;
+ RECT 0.62 75.78 0.98 173.48 ;
+ RECT 0.62 67.62 0.98 74.2 ;
+ RECT 1092.84 175.06 1093.2 671.92 ;
+ RECT 0.98 0.62 1092.84 0.76 ;
+ RECT 1092.84 0.62 1093.06 0.76 ;
+ RECT 1092.84 3.7 1093.06 70.12 ;
+ RECT 1093.06 0.62 1093.2 0.76 ;
+ RECT 1093.06 0.76 1093.2 3.7 ;
+ RECT 1093.06 3.7 1093.2 70.12 ;
+ RECT 0.62 0.62 0.76 0.76 ;
+ RECT 0.62 0.76 0.76 3.7 ;
+ RECT 0.62 3.7 0.76 65.36 ;
+ RECT 0.76 0.62 0.98 0.76 ;
+ RECT 0.76 3.7 0.98 65.36 ;
+ RECT 0.62 226.74 0.76 716.8 ;
+ RECT 0.62 716.8 0.76 719.74 ;
+ RECT 0.62 719.74 0.76 719.88 ;
+ RECT 0.76 226.74 0.98 716.8 ;
+ RECT 0.76 719.74 0.98 719.88 ;
+ RECT 0.98 719.74 1092.84 719.88 ;
+ RECT 1092.84 674.18 1093.06 716.8 ;
+ RECT 1092.84 719.74 1093.06 719.88 ;
+ RECT 1093.06 674.18 1093.2 716.8 ;
+ RECT 1093.06 716.8 1093.2 719.74 ;
+ RECT 1093.06 719.74 1093.2 719.88 ;
+ RECT 0.98 674.18 4.16 713.4 ;
+ RECT 0.98 713.4 4.16 716.34 ;
+ RECT 0.98 716.34 4.16 716.8 ;
+ RECT 4.16 674.18 1089.66 713.4 ;
+ RECT 4.16 716.34 1089.66 716.8 ;
+ RECT 1089.66 674.18 1092.84 713.4 ;
+ RECT 1089.66 713.4 1092.84 716.34 ;
+ RECT 1089.66 716.34 1092.84 716.8 ;
+ RECT 0.98 3.7 4.16 4.16 ;
+ RECT 0.98 4.16 4.16 7.1 ;
+ RECT 0.98 7.1 4.16 120.44 ;
+ RECT 4.16 3.7 1089.66 4.16 ;
+ RECT 4.16 7.1 1089.66 120.44 ;
+ RECT 1089.66 3.7 1092.84 4.16 ;
+ RECT 1089.66 4.16 1092.84 7.1 ;
+ RECT 1089.66 7.1 1092.84 120.44 ;
+ LAYER met4 ;
+ RECT 122.48 0.98 124.06 719.88 ;
+ RECT 124.06 0.62 129.28 0.98 ;
+ RECT 130.86 0.62 134.72 0.98 ;
+ RECT 136.3 0.62 140.84 0.98 ;
+ RECT 147.18 0.62 152.4 0.98 ;
+ RECT 153.98 0.62 157.84 0.98 ;
+ RECT 159.42 0.62 163.28 0.98 ;
+ RECT 164.86 0.62 169.4 0.98 ;
+ RECT 176.42 0.62 181.64 0.98 ;
+ RECT 183.22 0.62 187.08 0.98 ;
+ RECT 188.66 0.62 192.52 0.98 ;
+ RECT 200.22 0.62 204.08 0.98 ;
+ RECT 205.66 0.62 210.88 0.98 ;
+ RECT 212.46 0.62 216.32 0.98 ;
+ RECT 224.02 0.62 228.56 0.98 ;
+ RECT 230.14 0.62 234.0 0.98 ;
+ RECT 235.58 0.62 239.44 0.98 ;
+ RECT 241.02 0.62 244.88 0.98 ;
+ RECT 252.58 0.62 257.12 0.98 ;
+ RECT 258.7 0.62 263.24 0.98 ;
+ RECT 264.82 0.62 268.68 0.98 ;
+ RECT 275.7 0.62 280.24 0.98 ;
+ RECT 281.82 0.62 286.36 0.98 ;
+ RECT 287.94 0.62 292.48 0.98 ;
+ RECT 300.18 0.62 303.36 0.98 ;
+ RECT 83.26 0.62 87.8 0.98 ;
+ RECT 89.38 0.62 93.24 0.98 ;
+ RECT 124.06 0.98 1004.44 719.52 ;
+ RECT 1004.44 0.98 1006.02 719.52 ;
+ RECT 1000.58 719.52 1004.44 719.88 ;
+ RECT 993.78 719.52 999.0 719.88 ;
+ RECT 94.82 0.62 99.36 0.98 ;
+ RECT 100.94 0.62 104.8 0.98 ;
+ RECT 106.38 0.62 110.92 0.98 ;
+ RECT 112.5 0.62 117.04 0.98 ;
+ RECT 118.62 0.62 122.48 0.98 ;
+ RECT 142.42 0.62 144.24 0.98 ;
+ RECT 170.98 0.62 172.12 0.98 ;
+ RECT 173.7 0.62 174.84 0.98 ;
+ RECT 194.1 0.62 196.6 0.98 ;
+ RECT 198.18 0.62 198.64 0.98 ;
+ RECT 217.9 0.62 220.4 0.98 ;
+ RECT 221.98 0.62 222.44 0.98 ;
+ RECT 246.46 0.62 246.92 0.98 ;
+ RECT 248.5 0.62 251.0 0.98 ;
+ RECT 270.26 0.62 272.08 0.98 ;
+ RECT 273.66 0.62 274.12 0.98 ;
+ RECT 294.06 0.62 295.88 0.98 ;
+ RECT 297.46 0.62 298.6 0.98 ;
+ RECT 304.94 0.62 321.72 0.98 ;
+ RECT 323.3 0.62 346.88 0.98 ;
+ RECT 348.46 0.62 371.36 0.98 ;
+ RECT 372.94 0.62 396.52 0.98 ;
+ RECT 398.1 0.62 421.0 0.98 ;
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+ RECT 498.06 0.62 520.96 0.98 ;
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+ RECT 597.34 0.62 620.92 0.98 ;
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+ RECT 672.82 0.62 695.72 0.98 ;
+ RECT 697.3 0.62 720.88 0.98 ;
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+ RECT 772.1 0.62 795.68 0.98 ;
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+ RECT 846.9 0.62 870.48 0.98 ;
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+ RECT 897.22 0.62 920.8 0.98 ;
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+ RECT 148.54 719.52 171.44 719.88 ;
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+ RECT 198.18 719.52 221.76 719.88 ;
+ RECT 223.34 719.52 246.92 719.88 ;
+ RECT 248.5 719.52 272.08 719.88 ;
+ RECT 273.66 719.52 296.56 719.88 ;
+ RECT 298.14 719.52 321.72 719.88 ;
+ RECT 323.3 719.52 346.88 719.88 ;
+ RECT 348.46 719.52 372.04 719.88 ;
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+ RECT 398.78 719.52 421.0 719.88 ;
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+ RECT 473.58 719.52 496.48 719.88 ;
+ RECT 498.06 719.52 520.96 719.88 ;
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+ RECT 547.7 719.52 571.28 719.88 ;
+ RECT 572.86 719.52 595.76 719.88 ;
+ RECT 597.34 719.52 620.92 719.88 ;
+ RECT 622.5 719.52 646.08 719.88 ;
+ RECT 647.66 719.52 671.24 719.88 ;
+ RECT 672.82 719.52 696.4 719.88 ;
+ RECT 697.98 719.52 720.88 719.88 ;
+ RECT 722.46 719.52 746.04 719.88 ;
+ RECT 747.62 719.52 771.2 719.88 ;
+ RECT 772.78 719.52 796.36 719.88 ;
+ RECT 797.94 719.52 821.52 719.88 ;
+ RECT 823.1 719.52 845.32 719.88 ;
+ RECT 846.9 719.52 870.48 719.88 ;
+ RECT 872.06 719.52 896.32 719.88 ;
+ RECT 897.9 719.52 920.8 719.88 ;
+ RECT 922.38 719.52 992.2 719.88 ;
+ RECT 0.62 0.98 0.76 719.74 ;
+ RECT 0.62 719.74 0.76 719.88 ;
+ RECT 0.76 719.74 3.7 719.88 ;
+ RECT 3.7 719.74 122.48 719.88 ;
+ RECT 0.62 0.62 0.76 0.76 ;
+ RECT 0.62 0.76 0.76 0.98 ;
+ RECT 0.76 0.62 3.7 0.76 ;
+ RECT 3.7 0.62 81.68 0.76 ;
+ RECT 3.7 0.76 81.68 0.98 ;
+ RECT 1093.06 0.98 1093.2 719.52 ;
+ RECT 1006.02 719.52 1090.12 719.74 ;
+ RECT 1006.02 719.74 1090.12 719.88 ;
+ RECT 1090.12 719.74 1093.06 719.88 ;
+ RECT 1093.06 719.52 1093.2 719.74 ;
+ RECT 1093.06 719.74 1093.2 719.88 ;
+ RECT 922.38 0.62 1090.12 0.76 ;
+ RECT 922.38 0.76 1090.12 0.98 ;
+ RECT 1090.12 0.62 1093.06 0.76 ;
+ RECT 1093.06 0.62 1093.2 0.76 ;
+ RECT 1093.06 0.76 1093.2 0.98 ;
+ RECT 1006.02 0.98 1086.72 4.16 ;
+ RECT 1006.02 4.16 1086.72 716.34 ;
+ RECT 1006.02 716.34 1086.72 719.52 ;
+ RECT 1086.72 0.98 1089.66 4.16 ;
+ RECT 1086.72 716.34 1089.66 719.52 ;
+ RECT 1089.66 0.98 1090.12 4.16 ;
+ RECT 1089.66 4.16 1090.12 716.34 ;
+ RECT 1089.66 716.34 1090.12 719.52 ;
+ RECT 3.7 0.98 4.16 4.16 ;
+ RECT 3.7 4.16 4.16 716.34 ;
+ RECT 3.7 716.34 4.16 719.74 ;
+ RECT 4.16 0.98 7.1 4.16 ;
+ RECT 4.16 716.34 7.1 719.74 ;
+ RECT 7.1 0.98 122.48 4.16 ;
+ RECT 7.1 4.16 122.48 716.34 ;
+ RECT 7.1 716.34 122.48 719.74 ;
+ END
+END sky130_sram_8kbyte_1rw1r_32x2048_8
+END LIBRARY
diff --git a/verilog/rtl/sky130_sram_1kbyte_1rw1r_8x1024_8.v b/verilog/rtl/sky130_sram_1kbyte_1rw1r_8x1024_8.v
new file mode 100644
index 0000000..ee2b1d6
--- /dev/null
+++ b/verilog/rtl/sky130_sram_1kbyte_1rw1r_8x1024_8.v
@@ -0,0 +1,108 @@
+// OpenRAM SRAM model
+// Words: 1024
+// Word size: 8
+// Write size: 8
+
+module sky130_sram_1kbyte_1rw1r_8x1024_8(
+`ifdef USE_POWER_PINS
+ vccd1,
+ vssd1,
+`endif
+// Port 0: RW
+ clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+ clk1,csb1,addr1,dout1
+ );
+
+ parameter NUM_WMASKS = 1 ;
+ parameter DATA_WIDTH = 8 ;
+ parameter ADDR_WIDTH = 10 ;
+ parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+ // FIXME: This delay is arbitrary.
+ parameter DELAY = 3 ;
+ parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+ parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+ inout vccd1;
+ inout vssd1;
+`endif
+ input clk0; // clock
+ input csb0; // active low chip select
+ input web0; // active low write control
+ input [NUM_WMASKS-1:0] wmask0; // write mask
+ input [ADDR_WIDTH-1:0] addr0;
+ input [DATA_WIDTH-1:0] din0;
+ output [DATA_WIDTH-1:0] dout0;
+ input clk1; // clock
+ input csb1; // active low chip select
+ input [ADDR_WIDTH-1:0] addr1;
+ output [DATA_WIDTH-1:0] dout1;
+
+ reg csb0_reg;
+ reg web0_reg;
+ reg [NUM_WMASKS-1:0] wmask0_reg;
+ reg [ADDR_WIDTH-1:0] addr0_reg;
+ reg [DATA_WIDTH-1:0] din0_reg;
+ reg [DATA_WIDTH-1:0] dout0;
+
+ // All inputs are registers
+ always @(posedge clk0)
+ begin
+ csb0_reg = csb0;
+ web0_reg = web0;
+ wmask0_reg = wmask0;
+ addr0_reg = addr0;
+ din0_reg = din0;
+ #(T_HOLD) dout0 = 8'bx;
+ if ( !csb0_reg && web0_reg && VERBOSE )
+ $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+ if ( !csb0_reg && !web0_reg && VERBOSE )
+ $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+ end
+
+ reg csb1_reg;
+ reg [ADDR_WIDTH-1:0] addr1_reg;
+ reg [DATA_WIDTH-1:0] dout1;
+
+ // All inputs are registers
+ always @(posedge clk1)
+ begin
+ csb1_reg = csb1;
+ addr1_reg = addr1;
+ if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+ $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+ #(T_HOLD) dout1 = 8'bx;
+ if ( !csb1_reg && VERBOSE )
+ $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+ end
+
+reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
+
+ // Memory Write Block Port 0
+ // Write Operation : When web0 = 0, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_WRITE0
+ if ( !csb0_reg && !web0_reg ) begin
+ if (wmask0_reg[0])
+ mem[addr0_reg][7:0] = din0_reg[7:0];
+ end
+ end
+
+ // Memory Read Block Port 0
+ // Read Operation : When web0 = 1, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_READ0
+ if (!csb0_reg && web0_reg)
+ dout0 <= #(DELAY) mem[addr0_reg];
+ end
+
+ // Memory Read Block Port 1
+ // Read Operation : When web1 = 1, csb1 = 0
+ always @ (negedge clk1)
+ begin : MEM_READ1
+ if (!csb1_reg)
+ dout1 <= #(DELAY) mem[addr1_reg];
+ end
+
+endmodule
diff --git a/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v b/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
new file mode 100644
index 0000000..7da4327
--- /dev/null
+++ b/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
@@ -0,0 +1,114 @@
+// OpenRAM SRAM model
+// Words: 512
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_2kbyte_1rw1r_32x512_8(
+`ifdef USE_POWER_PINS
+ vccd1,
+ vssd1,
+`endif
+// Port 0: RW
+ clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+ clk1,csb1,addr1,dout1
+ );
+
+ parameter NUM_WMASKS = 4 ;
+ parameter DATA_WIDTH = 32 ;
+ parameter ADDR_WIDTH = 9 ;
+ parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+ // FIXME: This delay is arbitrary.
+ parameter DELAY = 3 ;
+ parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+ parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+ inout vccd1;
+ inout vssd1;
+`endif
+ input clk0; // clock
+ input csb0; // active low chip select
+ input web0; // active low write control
+ input [NUM_WMASKS-1:0] wmask0; // write mask
+ input [ADDR_WIDTH-1:0] addr0;
+ input [DATA_WIDTH-1:0] din0;
+ output [DATA_WIDTH-1:0] dout0;
+ input clk1; // clock
+ input csb1; // active low chip select
+ input [ADDR_WIDTH-1:0] addr1;
+ output [DATA_WIDTH-1:0] dout1;
+
+ reg csb0_reg;
+ reg web0_reg;
+ reg [NUM_WMASKS-1:0] wmask0_reg;
+ reg [ADDR_WIDTH-1:0] addr0_reg;
+ reg [DATA_WIDTH-1:0] din0_reg;
+ reg [DATA_WIDTH-1:0] dout0;
+
+ // All inputs are registers
+ always @(posedge clk0)
+ begin
+ csb0_reg = csb0;
+ web0_reg = web0;
+ wmask0_reg = wmask0;
+ addr0_reg = addr0;
+ din0_reg = din0;
+ #(T_HOLD) dout0 = 32'bx;
+ if ( !csb0_reg && web0_reg && VERBOSE )
+ $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+ if ( !csb0_reg && !web0_reg && VERBOSE )
+ $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+ end
+
+ reg csb1_reg;
+ reg [ADDR_WIDTH-1:0] addr1_reg;
+ reg [DATA_WIDTH-1:0] dout1;
+
+ // All inputs are registers
+ always @(posedge clk1)
+ begin
+ csb1_reg = csb1;
+ addr1_reg = addr1;
+ if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+ $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+ #(T_HOLD) dout1 = 32'bx;
+ if ( !csb1_reg && VERBOSE )
+ $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+ end
+
+reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
+
+ // Memory Write Block Port 0
+ // Write Operation : When web0 = 0, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_WRITE0
+ if ( !csb0_reg && !web0_reg ) begin
+ if (wmask0_reg[0])
+ mem[addr0_reg][7:0] = din0_reg[7:0];
+ if (wmask0_reg[1])
+ mem[addr0_reg][15:8] = din0_reg[15:8];
+ if (wmask0_reg[2])
+ mem[addr0_reg][23:16] = din0_reg[23:16];
+ if (wmask0_reg[3])
+ mem[addr0_reg][31:24] = din0_reg[31:24];
+ end
+ end
+
+ // Memory Read Block Port 0
+ // Read Operation : When web0 = 1, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_READ0
+ if (!csb0_reg && web0_reg)
+ dout0 <= #(DELAY) mem[addr0_reg];
+ end
+
+ // Memory Read Block Port 1
+ // Read Operation : When web1 = 1, csb1 = 0
+ always @ (negedge clk1)
+ begin : MEM_READ1
+ if (!csb1_reg)
+ dout1 <= #(DELAY) mem[addr1_reg];
+ end
+
+endmodule
diff --git a/verilog/rtl/sky130_sram_4kbyte_1rw1r_32x1024_8.v b/verilog/rtl/sky130_sram_4kbyte_1rw1r_32x1024_8.v
new file mode 100644
index 0000000..e3d3e4d
--- /dev/null
+++ b/verilog/rtl/sky130_sram_4kbyte_1rw1r_32x1024_8.v
@@ -0,0 +1,114 @@
+// OpenRAM SRAM model
+// Words: 1024
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_4kbyte_1rw1r_32x1024_8(
+`ifdef USE_POWER_PINS
+ vccd1,
+ vssd1,
+`endif
+// Port 0: RW
+ clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+ clk1,csb1,addr1,dout1
+ );
+
+ parameter NUM_WMASKS = 4 ;
+ parameter DATA_WIDTH = 32 ;
+ parameter ADDR_WIDTH = 10 ;
+ parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+ // FIXME: This delay is arbitrary.
+ parameter DELAY = 3 ;
+ parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+ parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+ inout vccd1;
+ inout vssd1;
+`endif
+ input clk0; // clock
+ input csb0; // active low chip select
+ input web0; // active low write control
+ input [NUM_WMASKS-1:0] wmask0; // write mask
+ input [ADDR_WIDTH-1:0] addr0;
+ input [DATA_WIDTH-1:0] din0;
+ output [DATA_WIDTH-1:0] dout0;
+ input clk1; // clock
+ input csb1; // active low chip select
+ input [ADDR_WIDTH-1:0] addr1;
+ output [DATA_WIDTH-1:0] dout1;
+
+ reg csb0_reg;
+ reg web0_reg;
+ reg [NUM_WMASKS-1:0] wmask0_reg;
+ reg [ADDR_WIDTH-1:0] addr0_reg;
+ reg [DATA_WIDTH-1:0] din0_reg;
+ reg [DATA_WIDTH-1:0] dout0;
+
+ // All inputs are registers
+ always @(posedge clk0)
+ begin
+ csb0_reg = csb0;
+ web0_reg = web0;
+ wmask0_reg = wmask0;
+ addr0_reg = addr0;
+ din0_reg = din0;
+ #(T_HOLD) dout0 = 32'bx;
+ if ( !csb0_reg && web0_reg && VERBOSE )
+ $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+ if ( !csb0_reg && !web0_reg && VERBOSE )
+ $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+ end
+
+ reg csb1_reg;
+ reg [ADDR_WIDTH-1:0] addr1_reg;
+ reg [DATA_WIDTH-1:0] dout1;
+
+ // All inputs are registers
+ always @(posedge clk1)
+ begin
+ csb1_reg = csb1;
+ addr1_reg = addr1;
+ if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+ $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+ #(T_HOLD) dout1 = 32'bx;
+ if ( !csb1_reg && VERBOSE )
+ $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+ end
+
+reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
+
+ // Memory Write Block Port 0
+ // Write Operation : When web0 = 0, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_WRITE0
+ if ( !csb0_reg && !web0_reg ) begin
+ if (wmask0_reg[0])
+ mem[addr0_reg][7:0] = din0_reg[7:0];
+ if (wmask0_reg[1])
+ mem[addr0_reg][15:8] = din0_reg[15:8];
+ if (wmask0_reg[2])
+ mem[addr0_reg][23:16] = din0_reg[23:16];
+ if (wmask0_reg[3])
+ mem[addr0_reg][31:24] = din0_reg[31:24];
+ end
+ end
+
+ // Memory Read Block Port 0
+ // Read Operation : When web0 = 1, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_READ0
+ if (!csb0_reg && web0_reg)
+ dout0 <= #(DELAY) mem[addr0_reg];
+ end
+
+ // Memory Read Block Port 1
+ // Read Operation : When web1 = 1, csb1 = 0
+ always @ (negedge clk1)
+ begin : MEM_READ1
+ if (!csb1_reg)
+ dout1 <= #(DELAY) mem[addr1_reg];
+ end
+
+endmodule
diff --git a/verilog/rtl/sky130_sram_8kbyte_1rw1r_32x2048_8.v b/verilog/rtl/sky130_sram_8kbyte_1rw1r_32x2048_8.v
new file mode 100644
index 0000000..2875382
--- /dev/null
+++ b/verilog/rtl/sky130_sram_8kbyte_1rw1r_32x2048_8.v
@@ -0,0 +1,114 @@
+// OpenRAM SRAM model
+// Words: 2048
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_8kbyte_1rw1r_32x2048_8(
+`ifdef USE_POWER_PINS
+ vccd1,
+ vssd1,
+`endif
+// Port 0: RW
+ clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+ clk1,csb1,addr1,dout1
+ );
+
+ parameter NUM_WMASKS = 4 ;
+ parameter DATA_WIDTH = 32 ;
+ parameter ADDR_WIDTH = 11 ;
+ parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+ // FIXME: This delay is arbitrary.
+ parameter DELAY = 3 ;
+ parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+ parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+ inout vccd1;
+ inout vssd1;
+`endif
+ input clk0; // clock
+ input csb0; // active low chip select
+ input web0; // active low write control
+ input [NUM_WMASKS-1:0] wmask0; // write mask
+ input [ADDR_WIDTH-1:0] addr0;
+ input [DATA_WIDTH-1:0] din0;
+ output [DATA_WIDTH-1:0] dout0;
+ input clk1; // clock
+ input csb1; // active low chip select
+ input [ADDR_WIDTH-1:0] addr1;
+ output [DATA_WIDTH-1:0] dout1;
+
+ reg csb0_reg;
+ reg web0_reg;
+ reg [NUM_WMASKS-1:0] wmask0_reg;
+ reg [ADDR_WIDTH-1:0] addr0_reg;
+ reg [DATA_WIDTH-1:0] din0_reg;
+ reg [DATA_WIDTH-1:0] dout0;
+
+ // All inputs are registers
+ always @(posedge clk0)
+ begin
+ csb0_reg = csb0;
+ web0_reg = web0;
+ wmask0_reg = wmask0;
+ addr0_reg = addr0;
+ din0_reg = din0;
+ #(T_HOLD) dout0 = 32'bx;
+ if ( !csb0_reg && web0_reg && VERBOSE )
+ $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+ if ( !csb0_reg && !web0_reg && VERBOSE )
+ $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+ end
+
+ reg csb1_reg;
+ reg [ADDR_WIDTH-1:0] addr1_reg;
+ reg [DATA_WIDTH-1:0] dout1;
+
+ // All inputs are registers
+ always @(posedge clk1)
+ begin
+ csb1_reg = csb1;
+ addr1_reg = addr1;
+ if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+ $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+ #(T_HOLD) dout1 = 32'bx;
+ if ( !csb1_reg && VERBOSE )
+ $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+ end
+
+reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
+
+ // Memory Write Block Port 0
+ // Write Operation : When web0 = 0, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_WRITE0
+ if ( !csb0_reg && !web0_reg ) begin
+ if (wmask0_reg[0])
+ mem[addr0_reg][7:0] = din0_reg[7:0];
+ if (wmask0_reg[1])
+ mem[addr0_reg][15:8] = din0_reg[15:8];
+ if (wmask0_reg[2])
+ mem[addr0_reg][23:16] = din0_reg[23:16];
+ if (wmask0_reg[3])
+ mem[addr0_reg][31:24] = din0_reg[31:24];
+ end
+ end
+
+ // Memory Read Block Port 0
+ // Read Operation : When web0 = 1, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_READ0
+ if (!csb0_reg && web0_reg)
+ dout0 <= #(DELAY) mem[addr0_reg];
+ end
+
+ // Memory Read Block Port 1
+ // Read Operation : When web1 = 1, csb1 = 0
+ always @ (negedge clk1)
+ begin : MEM_READ1
+ if (!csb1_reg)
+ dout1 <= #(DELAY) mem[addr1_reg];
+ end
+
+endmodule
