Fixed TOTAL_SIZE

verilog/rtl/openram_defines.v

diff --git a/verilog/rtl/openram_defines.v b/verilog/rtl/openram_defines.v
index 13e9a65..4c65502 100644
--- a/verilog/rtl/openram_defines.v
+++ b/verilog/rtl/openram_defines.v
@@ -4,4 +4,4 @@
 `define SELECT_SIZE 4
 `define MAX_CHIPS 16
 `define PORT_SIZE `ADDR_SIZE+`DATA_SIZE+`WMASK_SIZE+2
-`define TOTAL_SIZE 2*`PORT_SIZE + `SELECT_SIZE
+`define TOTAL_SIZE `PORT_SIZE+`PORT_SIZE+`SELECT_SIZE