commit 43fb1ea94a65e1ee7a820a859cbe3d25353eff1a
author AmoghLonkar <alonkar@ucsc.edu> Mon Jun 14 16:48:33 2021 -0700
committer AmoghLonkar <alonkar@ucsc.edu> Mon Jun 14 16:48:33 2021 -0700
tree 396949324f60f25a64d2b868f8afc51e13fb9533
parent 7c79b4db02f2750c23b03ee554d26c4167f4ac47

Fixed TOTAL_SIZE

verilog/rtl/openram_defines.v

diff --git a/verilog/rtl/openram_defines.v b/verilog/rtl/openram_defines.v
index 13e9a65..4c65502 100644
--- a/verilog/rtl/openram_defines.v
+++ b/verilog/rtl/openram_defines.v
@@ -4,4 +4,4 @@
 `define SELECT_SIZE 4
 `define MAX_CHIPS 16
 `define PORT_SIZE `ADDR_SIZE+`DATA_SIZE+`WMASK_SIZE+2
-`define TOTAL_SIZE 2*`PORT_SIZE + `SELECT_SIZE
+`define TOTAL_SIZE `PORT_SIZE+`PORT_SIZE+`SELECT_SIZE