Merge pull request #5 from AmoghLonkar/control_verilog
Control verilog
diff --git a/chisel/control_logic-main.zip:Zone.Identifier b/chisel/control_logic-main.zip:Zone.Identifier
deleted file mode 100644
index 3cac1a1..0000000
--- a/chisel/control_logic-main.zip:Zone.Identifier
+++ /dev/null
@@ -1,4 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
-ReferrerUrl=https://github.com/AmoghLonkar/control_logic
-HostUrl=https://codeload.github.com/AmoghLonkar/control_logic/zip/refs/heads/main
diff --git a/chisel/control_logic-main/control_logic-main/.github/workflows/test.yml b/chisel/control_logic-main/control_logic-main/.github/workflows/test.yml
deleted file mode 100644
index 75dfeef..0000000
--- a/chisel/control_logic-main/control_logic-main/.github/workflows/test.yml
+++ /dev/null
@@ -1,19 +0,0 @@
-name: Continuous Integration
-
-on: [push, pull_request]
-
-jobs:
- ci:
- name: ci
- runs-on: ubuntu-latest
- steps:
- - name: Checkout
- uses: actions/checkout@v2
- - name: Setup Scala
- uses: olafurpg/setup-scala@v10
- with:
- java-version: adopt@1.8
- - name: Cache Scala
- uses: coursier/cache-action@v5
- - name: Test
- run: sbt test
diff --git a/chisel/control_logic-main/control_logic-main/.gitignore b/chisel/control_logic-main/control_logic-main/.gitignore
deleted file mode 100644
index 12033d3..0000000
--- a/chisel/control_logic-main/control_logic-main/.gitignore
+++ /dev/null
@@ -1,341 +0,0 @@
-### Project Specific stuff
-test_run_dir/*
-### XilinxISE template
-# intermediate build files
-*.bgn
-*.bit
-*.bld
-*.cmd_log
-*.drc
-*.ll
-*.lso
-*.msd
-*.msk
-*.ncd
-*.ngc
-*.ngd
-*.ngr
-*.pad
-*.par
-*.pcf
-*.prj
-*.ptwx
-*.rbb
-*.rbd
-*.stx
-*.syr
-*.twr
-*.twx
-*.unroutes
-*.ut
-*.xpi
-*.xst
-*_bitgen.xwbt
-*_envsettings.html
-*_map.map
-*_map.mrp
-*_map.ngm
-*_map.xrpt
-*_ngdbuild.xrpt
-*_pad.csv
-*_pad.txt
-*_par.xrpt
-*_summary.html
-*_summary.xml
-*_usage.xml
-*_xst.xrpt
-
-# project-wide generated files
-*.gise
-par_usage_statistics.html
-usage_statistics_webtalk.html
-webtalk.log
-webtalk_pn.xml
-
-# generated folders
-iseconfig/
-xlnx_auto_0_xdb/
-xst/
-_ngo/
-_xmsgs/
-### Eclipse template
-*.pydevproject
-.metadata
-.gradle
-bin/
-tmp/
-*.tmp
-*.bak
-*.swp
-*~.nib
-local.properties
-.settings/
-.loadpath
-
-# Eclipse Core
-.project
-
-# External tool builders
-.externalToolBuilders/
-
-# Locally stored "Eclipse launch configurations"
-*.launch
-
-# CDT-specific
-.cproject
-
-# JDT-specific (Eclipse Java Development Tools)
-.classpath
-
-# Java annotation processor (APT)
-.factorypath
-
-# PDT-specific
-.buildpath
-
-# sbteclipse plugin
-.target
-
-# TeXlipse plugin
-.texlipse
-### C template
-# Object files
-*.o
-*.ko
-*.obj
-*.elf
-
-# Precompiled Headers
-*.gch
-*.pch
-
-# Libraries
-*.lib
-*.a
-*.la
-*.lo
-
-# Shared objects (inc. Windows DLLs)
-*.dll
-*.so
-*.so.*
-*.dylib
-
-# Executables
-*.exe
-*.out
-*.app
-*.i*86
-*.x86_64
-*.hex
-
-# Debug files
-*.dSYM/
-### SBT template
-# Simple Build Tool
-# http://www.scala-sbt.org/release/docs/Getting-Started/Directories.html#configuring-version-control
-
-target/
-lib_managed/
-src_managed/
-project/boot/
-.history
-.cache
-### Emacs template
-# -*- mode: gitignore; -*-
-*~
-\#*\#
-/.emacs.desktop
-/.emacs.desktop.lock
-*.elc
-auto-save-list
-tramp
-.\#*
-
-# Org-mode
-.org-id-locations
-*_archive
-
-# flymake-mode
-*_flymake.*
-
-# eshell files
-/eshell/history
-/eshell/lastdir
-
-# elpa packages
-/elpa/
-
-# reftex files
-*.rel
-
-# AUCTeX auto folder
-/auto/
-
-# cask packages
-.cask/
-### Vim template
-[._]*.s[a-w][a-z]
-[._]s[a-w][a-z]
-*.un~
-Session.vim
-.netrwhist
-*~
-### JetBrains template
-# Covers JetBrains IDEs: IntelliJ, RubyMine, PhpStorm, AppCode, PyCharm, CLion, Android Studio
-
-*.iml
-
-## Directory-based project format:
-.idea/
-# if you remove the above rule, at least ignore the following:
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-# User-specific stuff:
-# .idea/workspace.xml
-# .idea/tasks.xml
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-# Sensitive or high-churn files:
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-### C++ template
-# Compiled Object files
-*.slo
-*.lo
-*.o
-*.obj
-
-# Precompiled Headers
-*.gch
-*.pch
-
-# Compiled Dynamic libraries
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-*.dylib
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-# Fortran module files
-*.mod
-
-# Compiled Static libraries
-*.lai
-*.la
-*.a
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-
-# Executables
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-*.out
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-Icon
-
-# Thumbnails
-._*
-
-# Files that might appear in the root of a volume
-.DocumentRevisions-V100
-.fseventsd
-.Spotlight-V100
-.TemporaryItems
-.Trashes
-.VolumeIcon.icns
-
-# Directories potentially created on remote AFP share
-.AppleDB
-.AppleDesktop
-Network Trash Folder
-Temporary Items
-.apdisk
-### Xcode template
-# Xcode
-#
-# gitignore contributors: remember to update Global/Xcode.gitignore, Objective-C.gitignore & Swift.gitignore
-
-## Build generated
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-DerivedData
-
-## Various settings
-*.pbxuser
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-
-## Other
-*.xccheckout
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-# sbt specific
-.cache
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-
-# Scala-IDE specific
-.scala_dependencies
-.worksheet
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-# Mobile Tools for Java (J2ME)
-.mtj.tmp/
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-# Package Files #
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-# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
-hs_err_pid*
-
diff --git a/chisel/control_logic-main/control_logic-main/README.md b/chisel/control_logic-main/control_logic-main/README.md
deleted file mode 100644
index b40418d..0000000
--- a/chisel/control_logic-main/control_logic-main/README.md
+++ /dev/null
@@ -1,12 +0,0 @@
-Control Logic Generator for OpenRAM Test Chip
-=======================
-This repo contains an implementation of a hardware generator for the control logic required for the OpenRAM Test Chip.
-It is designed to receive an input packet from either the logic analyzer or GPIO pins and forward it to the desired SRAM module.
-For a read operation, the logic will read back data from the SRAM and send it to the CPU via the interface.
-
-### Steps to Run
-Once cloned and entered the top level directory, we can run the provided tests and generate synthesizable verilog.
-
-1.) To generate verilog, type and enter `sbt run` in the terminal.
-
-2.) To run the tests, type and enter `sbt test` in the terminal.
diff --git a/chisel/control_logic-main/control_logic-main/build.sbt b/chisel/control_logic-main/control_logic-main/build.sbt
deleted file mode 100644
index cf21897..0000000
--- a/chisel/control_logic-main/control_logic-main/build.sbt
+++ /dev/null
@@ -1,26 +0,0 @@
-// See README.md for license details.
-
-ThisBuild / scalaVersion := "2.12.13"
-ThisBuild / version := "0.1.0"
-ThisBuild / organization := "com.github.amoghlonkar"
-
-lazy val root = (project in file("."))
- .settings(
- name := "control_logic",
- libraryDependencies ++= Seq(
- "edu.berkeley.cs" %% "chisel3" % "3.4.3",
- "edu.berkeley.cs" %% "chiseltest" % "0.3.3" % "test"
- ),
- scalacOptions ++= Seq(
- "-Xsource:2.11",
- "-language:reflectiveCalls",
- "-deprecation",
- "-feature",
- "-Xcheckinit",
- // Enables autoclonetype2 in 3.4.x (on by default in 3.5)
- "-P:chiselplugin:useBundlePlugin"
- ),
- addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.4.3" cross CrossVersion.full),
- addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full)
- )
-
diff --git a/chisel/control_logic-main/control_logic-main/openram_testchip.v b/chisel/control_logic-main/control_logic-main/openram_testchip.v
deleted file mode 100644
index e9c7e29..0000000
--- a/chisel/control_logic-main/control_logic-main/openram_testchip.v
+++ /dev/null
@@ -1,239 +0,0 @@
-module openram_testchip(
- input clock,
- input reset,
- input [85:0] io_logical_analyzer_packet,
- input [31:0] io_gpio_packet,
- input io_in_select,
- input [31:0] io_sram0_rw_in,
- input [31:0] io_sram0_r0_in,
- input [31:0] io_sram1_rw_in,
- input [31:0] io_sram1_ro_in,
- input [31:0] io_sram2_rw_in,
- input [31:0] io_sram3_rw_in,
- input [31:0] io_sram4_rw_in,
- input [63:0] io_sram5_rw_in,
- output [54:0] io_sram0_connections,
- output [54:0] io_sram1_connections,
- output [47:0] io_sram2_connections,
- output [45:0] io_sram3_connections,
- output [46:0] io_sram4_connections,
- output [82:0] io_sram5_connections,
- output [63:0] io_la_data,
- output [31:0] io_gpio_data
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [95:0] _RAND_0;
- reg [63:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
-`endif // RANDOMIZE_REG_INIT
- reg [85:0] input_; // @[openram_testchip.scala 33:20]
- reg [63:0] output_; // @[openram_testchip.scala 34:21]
- reg in_sel; // @[openram_testchip.scala 35:25]
- reg gpio_sel; // @[openram_testchip.scala 37:27]
- reg la_sel; // @[openram_testchip.scala 38:25]
- reg SRAMDataReceived; // @[openram_testchip.scala 47:35]
- wire _T = ~gpio_sel; // @[openram_testchip.scala 48:68]
- reg [1:0] loadingCount; // @[Counter.scala 60:40]
- wire wrap_wrap = loadingCount == 2'h2; // @[Counter.scala 72:24]
- wire [1:0] _wrap_value_T_1 = loadingCount + 2'h1; // @[Counter.scala 76:24]
- wire _GEN_2 = gpio_sel & wrap_wrap; // @[Counter.scala 137:24 Counter.scala 138:12]
- reg REG; // @[openram_testchip.scala 49:67]
- reg transferCount; // @[Counter.scala 60:40]
- reg wrap; // @[openram_testchip.scala 51:23]
- reg [31:0] packetSeq_0; // @[openram_testchip.scala 52:24]
- reg [31:0] packetSeq_1; // @[openram_testchip.scala 52:24]
- reg [31:0] packetSeq_2; // @[openram_testchip.scala 52:24]
- wire [95:0] _input_T = {packetSeq_2,packetSeq_1,packetSeq_0}; // @[Cat.scala 30:58]
- wire [95:0] _GEN_9 = wrap & gpio_sel ? _input_T : {{10'd0}, io_logical_analyzer_packet}; // @[openram_testchip.scala 60:27 openram_testchip.scala 61:15 openram_testchip.scala 55:11]
- wire [95:0] _GEN_10 = _T ? {{10'd0}, input_} : _GEN_9; // @[openram_testchip.scala 64:20 openram_testchip.scala 65:15]
- wire [2:0] chip_select = input_[85:83]; // @[openram_testchip.scala 67:34]
- wire csb0 = input_[54]; // @[openram_testchip.scala 76:21]
- wire web = input_[53]; // @[openram_testchip.scala 77:20]
- wire _T_5 = _T | ~la_sel; // @[openram_testchip.scala 79:20]
- wire _T_6 = 3'h0 == chip_select; // @[Conditional.scala 37:30]
- wire _T_7 = 3'h1 == chip_select; // @[Conditional.scala 37:30]
- wire _T_8 = 3'h2 == chip_select; // @[Conditional.scala 37:30]
- wire _T_9 = 3'h3 == chip_select; // @[Conditional.scala 37:30]
- wire _T_10 = 3'h4 == chip_select; // @[Conditional.scala 37:30]
- wire _T_11 = 3'h5 == chip_select; // @[Conditional.scala 37:30]
- wire [82:0] _GEN_11 = _T_11 ? input_[82:0] : 83'h7ffffffffffffffffffff; // @[Conditional.scala 39:67 openram_testchip.scala 103:38 openram_testchip.scala 74:26]
- wire [46:0] _GEN_12 = _T_10 ? input_[46:0] : 47'h7fffffffffff; // @[Conditional.scala 39:67 openram_testchip.scala 99:38 openram_testchip.scala 73:26]
- wire [82:0] _GEN_13 = _T_10 ? 83'h7ffffffffffffffffffff : _GEN_11; // @[Conditional.scala 39:67 openram_testchip.scala 74:26]
- wire [45:0] _GEN_14 = _T_9 ? input_[45:0] : 46'h3fffffffffff; // @[Conditional.scala 39:67 openram_testchip.scala 95:38 openram_testchip.scala 72:26]
- wire [46:0] _GEN_15 = _T_9 ? 47'h7fffffffffff : _GEN_12; // @[Conditional.scala 39:67 openram_testchip.scala 73:26]
- wire [82:0] _GEN_16 = _T_9 ? 83'h7ffffffffffffffffffff : _GEN_13; // @[Conditional.scala 39:67 openram_testchip.scala 74:26]
- wire [47:0] _GEN_17 = _T_8 ? input_[47:0] : 48'hffffffffffff; // @[Conditional.scala 39:67 openram_testchip.scala 91:38 openram_testchip.scala 71:26]
- wire [45:0] _GEN_18 = _T_8 ? 46'h3fffffffffff : _GEN_14; // @[Conditional.scala 39:67 openram_testchip.scala 72:26]
- wire [46:0] _GEN_19 = _T_8 ? 47'h7fffffffffff : _GEN_15; // @[Conditional.scala 39:67 openram_testchip.scala 73:26]
- wire [82:0] _GEN_20 = _T_8 ? 83'h7ffffffffffffffffffff : _GEN_16; // @[Conditional.scala 39:67 openram_testchip.scala 74:26]
- wire [54:0] _GEN_21 = _T_7 ? input_[54:0] : 55'h7fffffffffffff; // @[Conditional.scala 39:67 openram_testchip.scala 87:38 openram_testchip.scala 70:26]
- wire [47:0] _GEN_22 = _T_7 ? 48'hffffffffffff : _GEN_17; // @[Conditional.scala 39:67 openram_testchip.scala 71:26]
- wire [45:0] _GEN_23 = _T_7 ? 46'h3fffffffffff : _GEN_18; // @[Conditional.scala 39:67 openram_testchip.scala 72:26]
- wire [46:0] _GEN_24 = _T_7 ? 47'h7fffffffffff : _GEN_19; // @[Conditional.scala 39:67 openram_testchip.scala 73:26]
- wire [82:0] _GEN_25 = _T_7 ? 83'h7ffffffffffffffffffff : _GEN_20; // @[Conditional.scala 39:67 openram_testchip.scala 74:26]
- wire [54:0] _GEN_26 = _T_6 ? input_[54:0] : 55'h7fffffffffffff; // @[Conditional.scala 40:58 openram_testchip.scala 83:38 openram_testchip.scala 69:26]
- wire [54:0] _GEN_27 = _T_6 ? 55'h7fffffffffffff : _GEN_21; // @[Conditional.scala 40:58 openram_testchip.scala 70:26]
- wire [47:0] _GEN_28 = _T_6 ? 48'hffffffffffff : _GEN_22; // @[Conditional.scala 40:58 openram_testchip.scala 71:26]
- wire [45:0] _GEN_29 = _T_6 ? 46'h3fffffffffff : _GEN_23; // @[Conditional.scala 40:58 openram_testchip.scala 72:26]
- wire [46:0] _GEN_30 = _T_6 ? 47'h7fffffffffff : _GEN_24; // @[Conditional.scala 40:58 openram_testchip.scala 73:26]
- wire [82:0] _GEN_31 = _T_6 ? 83'h7ffffffffffffffffffff : _GEN_25; // @[Conditional.scala 40:58 openram_testchip.scala 74:26]
- wire [31:0] _output_T = csb0 ? io_sram0_r0_in : io_sram0_rw_in; // @[openram_testchip.scala 114:30]
- wire [31:0] _output_T_1 = csb0 ? io_sram1_ro_in : io_sram1_rw_in; // @[openram_testchip.scala 118:31]
- wire [63:0] _GEN_38 = _T_11 ? io_sram5_rw_in : 64'h0; // @[Conditional.scala 39:67 openram_testchip.scala 134:24 openram_testchip.scala 108:12]
- wire [63:0] _GEN_39 = _T_10 ? {{32'd0}, io_sram4_rw_in} : _GEN_38; // @[Conditional.scala 39:67 openram_testchip.scala 130:24]
- wire [63:0] _GEN_40 = _T_9 ? {{32'd0}, io_sram3_rw_in} : _GEN_39; // @[Conditional.scala 39:67 openram_testchip.scala 126:24]
- wire _GEN_44 = in_sel | SRAMDataReceived; // @[openram_testchip.scala 138:29 openram_testchip.scala 139:30 openram_testchip.scala 47:35]
- wire _GEN_46 = web ? _GEN_44 : SRAMDataReceived; // @[openram_testchip.scala 110:14 openram_testchip.scala 47:35]
- wire [31:0] _GEN_47 = transferCount ? output_[63:32] : 32'h0; // @[openram_testchip.scala 148:42 openram_testchip.scala 149:26 openram_testchip.scala 144:18]
- wire [31:0] _GEN_49 = ~transferCount ? output_[31:0] : _GEN_47; // @[openram_testchip.scala 146:36 openram_testchip.scala 147:26]
- assign io_sram0_connections = _T_5 ? _GEN_26 : 55'h7fffffffffffff; // @[openram_testchip.scala 80:5 openram_testchip.scala 69:26]
- assign io_sram1_connections = _T_5 ? _GEN_27 : 55'h7fffffffffffff; // @[openram_testchip.scala 80:5 openram_testchip.scala 70:26]
- assign io_sram2_connections = _T_5 ? _GEN_28 : 48'hffffffffffff; // @[openram_testchip.scala 80:5 openram_testchip.scala 71:26]
- assign io_sram3_connections = _T_5 ? _GEN_29 : 46'h3fffffffffff; // @[openram_testchip.scala 80:5 openram_testchip.scala 72:26]
- assign io_sram4_connections = _T_5 ? _GEN_30 : 47'h7fffffffffff; // @[openram_testchip.scala 80:5 openram_testchip.scala 73:26]
- assign io_sram5_connections = _T_5 ? _GEN_31 : 83'h7ffffffffffffffffffff; // @[openram_testchip.scala 80:5 openram_testchip.scala 74:26]
- assign io_la_data = in_sel ? 64'h0 : output_; // @[openram_testchip.scala 145:25 openram_testchip.scala 143:16 openram_testchip.scala 153:20]
- assign io_gpio_data = in_sel ? _GEN_49 : 32'h0; // @[openram_testchip.scala 145:25 openram_testchip.scala 144:18]
- always @(posedge clock) begin
- input_ <= _GEN_10[85:0];
- if (web) begin // @[openram_testchip.scala 110:14]
- if (_T_6) begin // @[Conditional.scala 40:58]
- output_ <= {{32'd0}, _output_T}; // @[openram_testchip.scala 114:24]
- end else if (_T_7) begin // @[Conditional.scala 39:67]
- output_ <= {{32'd0}, _output_T_1}; // @[openram_testchip.scala 118:24]
- end else if (_T_8) begin // @[Conditional.scala 39:67]
- output_ <= {{32'd0}, io_sram2_rw_in}; // @[openram_testchip.scala 122:24]
- end else begin
- output_ <= _GEN_40;
- end
- end else begin
- output_ <= 64'h0; // @[openram_testchip.scala 108:12]
- end
- in_sel <= io_in_select; // @[openram_testchip.scala 35:25]
- gpio_sel <= reset | ~wrap & gpio_sel; // @[openram_testchip.scala 37:27 openram_testchip.scala 37:27 openram_testchip.scala 57:14]
- la_sel <= io_in_select; // @[openram_testchip.scala 38:25]
- if (reset) begin // @[openram_testchip.scala 47:35]
- SRAMDataReceived <= 1'h0; // @[openram_testchip.scala 47:35]
- end else if (in_sel) begin // @[openram_testchip.scala 145:25]
- if (~transferCount) begin // @[openram_testchip.scala 146:36]
- SRAMDataReceived <= _GEN_46;
- end else if (transferCount) begin // @[openram_testchip.scala 148:42]
- SRAMDataReceived <= 1'h0; // @[openram_testchip.scala 150:30]
- end else begin
- SRAMDataReceived <= _GEN_46;
- end
- end else begin
- SRAMDataReceived <= _GEN_46;
- end
- if (reset) begin // @[Counter.scala 60:40]
- loadingCount <= 2'h0; // @[Counter.scala 60:40]
- end else if (_T) begin // @[Counter.scala 135:17]
- loadingCount <= 2'h0; // @[Counter.scala 97:11]
- end else if (gpio_sel) begin // @[Counter.scala 137:24]
- if (wrap_wrap) begin // @[Counter.scala 86:20]
- loadingCount <= 2'h0; // @[Counter.scala 86:28]
- end else begin
- loadingCount <= _wrap_value_T_1; // @[Counter.scala 76:15]
- end
- end
- REG <= SRAMDataReceived; // @[openram_testchip.scala 49:67]
- if (reset) begin // @[Counter.scala 60:40]
- transferCount <= 1'h0; // @[Counter.scala 60:40]
- end else if (REG) begin // @[Counter.scala 137:24]
- transferCount <= transferCount + 1'h1; // @[Counter.scala 76:15]
- end
- if (_T) begin // @[Counter.scala 135:17]
- wrap <= 1'h0;
- end else begin
- wrap <= _GEN_2;
- end
- if (loadingCount == 2'h0) begin // @[openram_testchip.scala 58:49]
- packetSeq_0 <= io_gpio_packet;
- end
- if (loadingCount == 2'h1) begin // @[openram_testchip.scala 58:49]
- packetSeq_1 <= io_gpio_packet;
- end
- if (wrap_wrap) begin // @[openram_testchip.scala 58:49]
- packetSeq_2 <= io_gpio_packet;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {3{`RANDOM}};
- input_ = _RAND_0[85:0];
- _RAND_1 = {2{`RANDOM}};
- output_ = _RAND_1[63:0];
- _RAND_2 = {1{`RANDOM}};
- in_sel = _RAND_2[0:0];
- _RAND_3 = {1{`RANDOM}};
- gpio_sel = _RAND_3[0:0];
- _RAND_4 = {1{`RANDOM}};
- la_sel = _RAND_4[0:0];
- _RAND_5 = {1{`RANDOM}};
- SRAMDataReceived = _RAND_5[0:0];
- _RAND_6 = {1{`RANDOM}};
- loadingCount = _RAND_6[1:0];
- _RAND_7 = {1{`RANDOM}};
- REG = _RAND_7[0:0];
- _RAND_8 = {1{`RANDOM}};
- transferCount = _RAND_8[0:0];
- _RAND_9 = {1{`RANDOM}};
- wrap = _RAND_9[0:0];
- _RAND_10 = {1{`RANDOM}};
- packetSeq_0 = _RAND_10[31:0];
- _RAND_11 = {1{`RANDOM}};
- packetSeq_1 = _RAND_11[31:0];
- _RAND_12 = {1{`RANDOM}};
- packetSeq_2 = _RAND_12[31:0];
-`endif // RANDOMIZE_REG_INIT
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
diff --git a/chisel/control_logic-main/control_logic-main/project/build.properties b/chisel/control_logic-main/control_logic-main/project/build.properties
deleted file mode 100644
index ddffd37..0000000
--- a/chisel/control_logic-main/control_logic-main/project/build.properties
+++ /dev/null
@@ -1 +0,0 @@
-sbt.version = 1.4.9
diff --git a/chisel/control_logic-main/control_logic-main/project/plugins.sbt b/chisel/control_logic-main/control_logic-main/project/plugins.sbt
deleted file mode 100644
index 5708f81..0000000
--- a/chisel/control_logic-main/control_logic-main/project/plugins.sbt
+++ /dev/null
@@ -1 +0,0 @@
-logLevel := Level.Warn
diff --git a/chisel/control_logic-main/control_logic-main/src/main/scala/control_logic/openram_testchip.scala b/chisel/control_logic-main/control_logic-main/src/main/scala/control_logic/openram_testchip.scala
deleted file mode 100644
index 9018a72..0000000
--- a/chisel/control_logic-main/control_logic-main/src/main/scala/control_logic/openram_testchip.scala
+++ /dev/null
@@ -1,161 +0,0 @@
-// See README.md for license details.
-
-package openram_testchip
-
-import chisel3._
-import chisel3.util._
-
-import scala.collection.mutable.ArrayBuffer
-
-class openram_testchip extends Module {
- val io = IO(new Bundle{
- val logical_analyzer_packet = Input(UInt(86.W))
- val gpio_packet = Input(UInt(32.W))
- val in_select = Input(Bool())
- val sram0_rw_in = Input(UInt(32.W))
- val sram0_r0_in = Input(UInt(32.W))
- val sram1_rw_in = Input(UInt(32.W))
- val sram1_ro_in = Input(UInt(32.W))
- val sram2_rw_in = Input(UInt(32.W))
- val sram3_rw_in = Input(UInt(32.W))
- val sram4_rw_in = Input(UInt(32.W))
- val sram5_rw_in = Input(UInt(64.W))
- val sram0_connections = Output(UInt(55.W))
- val sram1_connections = Output(UInt(55.W))
- val sram2_connections = Output(UInt(48.W))
- val sram3_connections = Output(UInt(46.W))
- val sram4_connections = Output(UInt(47.W))
- val sram5_connections = Output(UInt(83.W))
- val la_data = Output(UInt(64.W))
- val gpio_data = Output(UInt(32.W))
- })
-
- val input = Reg(UInt(86.W))
- val output = Reg(UInt(64.W))
- val in_sel = RegNext(io.in_select)
-
- val gpio_sel = RegInit(true.B)
- val la_sel = RegNext(io.in_select)
- gpio_sel := io.in_select
-
- def getMask(bitWidth: Int): UInt = {
- val MOD = BigInt(1) << bitWidth
- val MASK = MOD - BigInt(1)
- MASK.U
- }
-
- val SRAMDataReceived = RegInit(false.B)
- val (loadingCount, loadingDone) = Counter(0 until 3, gpio_sel, !gpio_sel)
- val (transferCount, transferDone) = Counter(0 until 2, RegNext(SRAMDataReceived))
-
- val wrap = RegNext(loadingDone)
- val packetSeq = Reg(Vec(3, UInt(32.W)))
- packetSeq := VecInit(Seq.fill(3)(0.U))
-
- input := io.logical_analyzer_packet
-
- gpio_sel := Mux((!wrap && gpio_sel), true.B, false.B)
- (0 until 3).foreach(i => packetSeq(i) := Mux(loadingCount === i.U, io.gpio_packet, packetSeq(i)))
-
- when(wrap && gpio_sel){
- input := Cat(packetSeq(2), packetSeq(1), packetSeq(0))
- }
-
- when(!gpio_sel){
- input := input
- }
- val chip_select: UInt = input(85, 83)
-
- io.sram0_connections := getMask(55)
- io.sram1_connections := getMask(55)
- io.sram2_connections := getMask(48)
- io.sram3_connections := getMask(46)
- io.sram4_connections := getMask(47)
- io.sram5_connections := getMask(83)
-
- val csb0 = input(54)
- val web = input(53)
-
- when(!gpio_sel || !la_sel)
- {
- switch(chip_select){
- is(0.U){
- io.sram0_connections := input.tail(31)
- }
-
- is(1.U){
- io.sram1_connections := input.tail(31)
- }
-
- is(2.U){
- io.sram2_connections := input.tail(38)
- }
-
- is(3.U){
- io.sram3_connections := input.tail(40)
- }
-
- is(4.U){
- io.sram4_connections := input.tail(39)
- }
-
- is(5.U){
- io.sram5_connections := input.tail(3)
- }
- }
- }
-
- output := 0.U
- //If operation is read
- when(web){
- switch(chip_select){
-
- is(0.U){
- output := Mux(csb0, io.sram0_r0_in, io.sram0_rw_in)
- }
-
- is(1.U){
- output := Mux(csb0, io.sram1_ro_in, io.sram1_rw_in)
- }
-
- is(2.U){
- output := io.sram2_rw_in
- }
-
- is(3.U){
- output := io.sram3_rw_in
- }
-
- is(4.U){
- output := io.sram4_rw_in
- }
-
- is(5.U){
- output := io.sram5_rw_in
- }
- }
-
- when(in_sel === 1.U){
- SRAMDataReceived := true.B
- }
- }
-
- io.la_data := 0.U
- io.gpio_data := 0.U
- when(in_sel === 1.U){
- when(transferCount === 0.U){
- io.gpio_data := output(31, 0)
- }.elsewhen(transferCount === 1.U){
- io.gpio_data := output(63, 32)
- SRAMDataReceived := false.B
- }
- }.otherwise{
- io.la_data := output
- }
-}
-
-import chisel3.stage.ChiselStage
-
-object openram_testchipDriver extends App {
- (new ChiselStage).emitVerilog(new openram_testchip)
-}
\ No newline at end of file
diff --git a/chisel/control_logic-main/control_logic-main/src/test/scala/control_logic/openramTestSuite.scala b/chisel/control_logic-main/control_logic-main/src/test/scala/control_logic/openramTestSuite.scala
deleted file mode 100644
index 4213883..0000000
--- a/chisel/control_logic-main/control_logic-main/src/test/scala/control_logic/openramTestSuite.scala
+++ /dev/null
@@ -1,120 +0,0 @@
-package openram_testchip
-
-import chisel3._
-import chisel3.tester._
-import org.scalatest.FreeSpec
-
-import treadle._
-import chisel3.tester.experimental.TestOptionBuilder._
-
-class OpenramTestChipTester extends FreeSpec with ChiselScalatestTester {
-
- "OpenramTestChip should write to SRAM 0" in {
- test(new openram_testchip).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
- //Writing 1 to address 1 in SRAM 0
- val packet = BigInt("1E020000000200", 16)
- val MOD = (Seq.fill(54)(BigInt(2)).reduce(_*_) )
- val MASK = (Seq.fill(55)(BigInt(2)).reduce(_*_) - 1)
- dut.io.logical_analyzer_packet.poke(packet.U)
- dut.io.gpio_packet.poke(0.U)
- dut.io.in_select.poke(false.B)
- dut.clock.step()
- dut.io.sram0_connections.expect((packet % MOD).U)
- dut.io.sram1_connections.expect(MASK.U)
- }
- }
-
- "OpenramTestChip should accept data from GPIO" in {
- test(new openram_testchip).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
- //Writing 1 to address 1 in SRAM 0
- val packet = BigInt("1E020000000200", 16)
- val MOD = (Seq.fill(54)(BigInt(2)).reduce(_*_) )
- val MASK = (Seq.fill(55)(BigInt(2)).reduce(_*_) - 1)
- dut.io.logical_analyzer_packet.poke(0.U)
- dut.io.gpio_packet.poke(BigInt("00000200", 16).U)
- dut.io.in_select.poke(true.B)
- dut.clock.step()
- dut.io.gpio_packet.poke(BigInt("001E0200", 16).U)
- dut.clock.step()
- dut.io.gpio_packet.poke(BigInt("00000000", 16).U)
- dut.clock.step(2)
- dut.io.sram0_connections.expect((packet % MOD).U)
- dut.io.sram1_connections.expect(MASK.U)
- dut.clock.step(5)
- dut.io.sram0_connections.expect((packet % MOD).U)
- }
- }
-
- "OpenramTestChip should write to SRAM 1" in {
- test(new openram_testchip).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
- //Writing 1 to address 1 in SRAM 1
- val packet = BigInt("080000000E020000000200", 16)
- val MOD = (Seq.fill(54)(BigInt(2)).reduce(_*_) )
- val MASK = (Seq.fill(55)(BigInt(2)).reduce(_*_) - 1)
- dut.io.logical_analyzer_packet.poke(packet.U)
- dut.io.gpio_packet.poke(0.U)
- dut.io.in_select.poke(false.B)
- dut.clock.step()
- dut.io.sram0_connections.expect(MASK.U)
- dut.io.sram1_connections.expect((packet % MOD).U)
- }
- }
-
- "OpenramTestChip should read from R/W Port in SRAM 0" in {
- test(new openram_testchip).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
- //Reading from address 1 in SRAM 0
- val packet = BigInt("20020000000100", 16)
- val MOD = (Seq.fill(54)(BigInt(2)).reduce(_*_) )
- val MASK = (Seq.fill(55)(BigInt(2)).reduce(_*_) - 1)
- dut.io.logical_analyzer_packet.poke(packet.U)
- dut.io.gpio_packet.poke(0.U)
- dut.io.in_select.poke(false.B)
- dut.clock.step()
- dut.io.sram0_connections.expect((packet % MOD).U)
- dut.io.sram1_connections.expect(MASK.U)
- dut.clock.step()
- dut.io.sram0_rw_in.poke(1.U)
- dut.clock.step()
- dut.io.la_data.expect(1.U)
- }
- }
-
- "OpenramTestChip should read from R/W Port in SRAM 0 (GPIO)" in {
- test(new openram_testchip).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
- //Reading from address 1 in SRAM 0
- val packet = BigInt("20020000000100", 16)
- val MOD = (Seq.fill(54)(BigInt(2)).reduce(_*_) )
- val MASK = (Seq.fill(55)(BigInt(2)).reduce(_*_) - 1)
- dut.io.logical_analyzer_packet.poke(0.U)
- dut.io.gpio_packet.poke(BigInt("00000100", 16).U)
- dut.io.in_select.poke(true.B)
- dut.clock.step()
- dut.io.gpio_packet.poke(BigInt("00200200", 16).U)
- dut.clock.step()
- dut.io.gpio_packet.poke(BigInt("00000000", 16).U)
- dut.clock.step(2)
- dut.io.sram0_connections.expect((packet % MOD).U)
- dut.io.sram1_connections.expect(MASK.U)
- dut.clock.step()
- dut.io.sram0_rw_in.poke(1.U)
- dut.clock.step()
- dut.io.gpio_data.expect(1.U)
- dut.clock.step()
- dut.io.gpio_data.expect(0.U)
- }
- }
-
- "OpenramTestChip should write to shared R/W Port in SRAM 2" in {
- test(new openram_testchip).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
- //Writing 1 to address 1 in SRAM 1
- val packet = BigInt("100000000E020000000200", 16)
- val MOD = (Seq.fill(47)(BigInt(2)).reduce(_*_) )
- val MASK = (Seq.fill(48)(BigInt(2)).reduce(_*_) - 1)
- dut.io.logical_analyzer_packet.poke(packet.U)
- dut.io.gpio_packet.poke(0.U)
- dut.io.in_select.poke(false.B)
- dut.clock.step()
- dut.io.sram2_connections.expect((packet % MOD).U)
- }
- }
-}
diff --git a/gds/openram_testchip.gds b/gds/openram_testchip.gds
index 81f6c97..80186b1 100644
--- a/gds/openram_testchip.gds
+++ b/gds/openram_testchip.gds
Binary files differ
diff --git a/gds/sky130_sram_1kbyte_1rw1r_8x1024_8.gds b/gds/sky130_sram_1kbyte_1rw1r_8x1024_8.gds
new file mode 100644
index 0000000..24b326b
--- /dev/null
+++ b/gds/sky130_sram_1kbyte_1rw1r_8x1024_8.gds
Binary files differ
diff --git a/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds b/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds
new file mode 100644
index 0000000..281682f
--- /dev/null
+++ b/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds
Binary files differ
diff --git a/gds/sky130_sram_4kbyte_1rw1r_32x1024_8.gds b/gds/sky130_sram_4kbyte_1rw1r_32x1024_8.gds
new file mode 100644
index 0000000..51f9f25
--- /dev/null
+++ b/gds/sky130_sram_4kbyte_1rw1r_32x1024_8.gds
Binary files differ
diff --git a/gds/sky130_sram_8kbyte_1rw1r_32x2048_8.gds b/gds/sky130_sram_8kbyte_1rw1r_32x2048_8.gds
new file mode 100644
index 0000000..28394f3
--- /dev/null
+++ b/gds/sky130_sram_8kbyte_1rw1r_32x2048_8.gds
Binary files differ
diff --git a/lef/openram_testchip.lef b/lef/openram_testchip.lef
index cc41fbb..bf80c29 100644
--- a/lef/openram_testchip.lef
+++ b/lef/openram_testchip.lef
@@ -7,6654 +7,6278 @@
FOREIGN openram_testchip ;
ORIGIN 0.000 0.000 ;
SIZE 500.000 BY 800.000 ;
- PIN clock
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 280.690 796.000 280.970 800.000 ;
- END
- END clock
- PIN io_gpio_packet[0]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 329.840 500.000 330.440 ;
- END
- END io_gpio_packet[0]
- PIN io_gpio_packet[10]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 368.090 0.000 368.370 4.000 ;
- END
- END io_gpio_packet[10]
- PIN io_gpio_packet[11]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 625.640 4.000 626.240 ;
- END
- END io_gpio_packet[11]
- PIN io_gpio_packet[12]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 340.040 500.000 340.640 ;
- END
- END io_gpio_packet[12]
- PIN io_gpio_packet[13]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 423.290 0.000 423.570 4.000 ;
- END
- END io_gpio_packet[13]
- PIN io_gpio_packet[14]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 177.190 796.000 177.470 800.000 ;
- END
- END io_gpio_packet[14]
- PIN io_gpio_packet[15]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 37.440 4.000 38.040 ;
- END
- END io_gpio_packet[15]
- PIN io_gpio_packet[16]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 322.090 0.000 322.370 4.000 ;
- END
- END io_gpio_packet[16]
- PIN io_gpio_packet[17]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 255.390 0.000 255.670 4.000 ;
- END
- END io_gpio_packet[17]
- PIN io_gpio_packet[18]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 714.040 500.000 714.640 ;
- END
- END io_gpio_packet[18]
- PIN io_gpio_packet[19]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 540.640 4.000 541.240 ;
- END
- END io_gpio_packet[19]
- PIN io_gpio_packet[1]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 720.840 4.000 721.440 ;
- END
- END io_gpio_packet[1]
- PIN io_gpio_packet[20]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 280.690 0.000 280.970 4.000 ;
- END
- END io_gpio_packet[20]
- PIN io_gpio_packet[21]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 159.840 500.000 160.440 ;
- END
- END io_gpio_packet[21]
- PIN io_gpio_packet[22]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 676.640 500.000 677.240 ;
- END
- END io_gpio_packet[22]
- PIN io_gpio_packet[23]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 289.890 0.000 290.170 4.000 ;
- END
- END io_gpio_packet[23]
- PIN io_gpio_packet[24]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 615.440 500.000 616.040 ;
- END
- END io_gpio_packet[24]
- PIN io_gpio_packet[25]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 703.840 4.000 704.440 ;
- END
- END io_gpio_packet[25]
- PIN io_gpio_packet[26]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 210.840 4.000 211.440 ;
- END
- END io_gpio_packet[26]
- PIN io_gpio_packet[27]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 272.040 500.000 272.640 ;
- END
- END io_gpio_packet[27]
- PIN io_gpio_packet[28]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 85.190 796.000 85.470 800.000 ;
- END
- END io_gpio_packet[28]
- PIN io_gpio_packet[29]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 404.640 500.000 405.240 ;
- END
- END io_gpio_packet[29]
- PIN io_gpio_packet[2]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 299.090 0.000 299.370 4.000 ;
- END
- END io_gpio_packet[2]
- PIN io_gpio_packet[30]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 257.690 796.000 257.970 800.000 ;
- END
- END io_gpio_packet[30]
- PIN io_gpio_packet[31]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 135.790 0.000 136.070 4.000 ;
- END
- END io_gpio_packet[31]
- PIN io_gpio_packet[32]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 225.490 0.000 225.770 4.000 ;
- END
- END io_gpio_packet[32]
- PIN io_gpio_packet[33]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 584.840 4.000 585.440 ;
- END
- END io_gpio_packet[33]
- PIN io_gpio_packet[34]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 129.240 4.000 129.840 ;
- END
- END io_gpio_packet[34]
- PIN io_gpio_packet[35]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 427.890 0.000 428.170 4.000 ;
- END
- END io_gpio_packet[35]
- PIN io_gpio_packet[36]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 55.290 796.000 55.570 800.000 ;
- END
- END io_gpio_packet[36]
- PIN io_gpio_packet[37]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 486.240 500.000 486.840 ;
- END
- END io_gpio_packet[37]
- PIN io_gpio_packet[38]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 39.190 796.000 39.470 800.000 ;
- END
- END io_gpio_packet[38]
- PIN io_gpio_packet[39]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 432.490 796.000 432.770 800.000 ;
- END
- END io_gpio_packet[39]
- PIN io_gpio_packet[3]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 351.990 796.000 352.270 800.000 ;
- END
- END io_gpio_packet[3]
- PIN io_gpio_packet[40]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 377.290 0.000 377.570 4.000 ;
- END
- END io_gpio_packet[40]
- PIN io_gpio_packet[41]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 659.640 4.000 660.240 ;
- END
- END io_gpio_packet[41]
- PIN io_gpio_packet[42]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 244.840 500.000 245.440 ;
- END
- END io_gpio_packet[42]
- PIN io_gpio_packet[43]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 513.440 500.000 514.040 ;
- END
- END io_gpio_packet[43]
- PIN io_gpio_packet[44]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 476.190 0.000 476.470 4.000 ;
- END
- END io_gpio_packet[44]
- PIN io_gpio_packet[45]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 170.290 0.000 170.570 4.000 ;
- END
- END io_gpio_packet[45]
- PIN io_gpio_packet[46]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 266.890 0.000 267.170 4.000 ;
- END
- END io_gpio_packet[46]
- PIN io_gpio_packet[47]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 727.640 500.000 728.240 ;
- END
- END io_gpio_packet[47]
- PIN io_gpio_packet[48]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 85.040 4.000 85.640 ;
- END
- END io_gpio_packet[48]
- PIN io_gpio_packet[49]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 446.290 796.000 446.570 800.000 ;
- END
- END io_gpio_packet[49]
- PIN io_gpio_packet[4]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 147.290 796.000 147.570 800.000 ;
- END
- END io_gpio_packet[4]
- PIN io_gpio_packet[50]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 187.040 500.000 187.640 ;
- END
- END io_gpio_packet[50]
- PIN io_gpio_packet[51]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 46.090 0.000 46.370 4.000 ;
- END
- END io_gpio_packet[51]
- PIN io_gpio_packet[52]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 388.790 796.000 389.070 800.000 ;
- END
- END io_gpio_packet[52]
- PIN io_gpio_packet[53]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 391.090 796.000 391.370 800.000 ;
- END
- END io_gpio_packet[53]
- PIN io_gpio_packet[54]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 751.440 4.000 752.040 ;
- END
- END io_gpio_packet[54]
- PIN io_gpio_packet[55]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 557.640 500.000 558.240 ;
- END
- END io_gpio_packet[55]
- PIN io_gpio_packet[5]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 3.440 500.000 4.040 ;
- END
- END io_gpio_packet[5]
- PIN io_gpio_packet[6]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 489.990 0.000 490.270 4.000 ;
- END
- END io_gpio_packet[6]
- PIN io_gpio_packet[7]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 305.990 796.000 306.270 800.000 ;
- END
- END io_gpio_packet[7]
- PIN io_gpio_packet[8]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 374.040 4.000 374.640 ;
- END
- END io_gpio_packet[8]
- PIN io_gpio_packet[9]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 615.440 4.000 616.040 ;
- END
- END io_gpio_packet[9]
- PIN io_in_select
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 462.390 0.000 462.670 4.000 ;
- END
- END io_in_select
- PIN io_logical_analyzer_packet[0]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 489.990 796.000 490.270 800.000 ;
- END
- END io_logical_analyzer_packet[0]
- PIN io_logical_analyzer_packet[10]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 642.640 4.000 643.240 ;
- END
- END io_logical_analyzer_packet[10]
- PIN io_logical_analyzer_packet[11]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 144.990 0.000 145.270 4.000 ;
- END
- END io_logical_analyzer_packet[11]
- PIN io_logical_analyzer_packet[12]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 315.190 0.000 315.470 4.000 ;
- END
- END io_logical_analyzer_packet[12]
- PIN io_logical_analyzer_packet[13]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 40.840 500.000 41.440 ;
- END
- END io_logical_analyzer_packet[13]
- PIN io_logical_analyzer_packet[14]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 216.290 796.000 216.570 800.000 ;
- END
- END io_logical_analyzer_packet[14]
- PIN io_logical_analyzer_packet[15]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 257.690 0.000 257.970 4.000 ;
- END
- END io_logical_analyzer_packet[15]
- PIN io_logical_analyzer_packet[16]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 482.840 500.000 483.440 ;
- END
- END io_logical_analyzer_packet[16]
- PIN io_logical_analyzer_packet[17]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 387.640 500.000 388.240 ;
- END
- END io_logical_analyzer_packet[17]
- PIN io_logical_analyzer_packet[18]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 98.640 4.000 99.240 ;
- END
- END io_logical_analyzer_packet[18]
- PIN io_logical_analyzer_packet[19]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 437.090 0.000 437.370 4.000 ;
- END
- END io_logical_analyzer_packet[19]
- PIN io_logical_analyzer_packet[1]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 393.390 0.000 393.670 4.000 ;
- END
- END io_logical_analyzer_packet[1]
- PIN io_logical_analyzer_packet[20]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 258.440 4.000 259.040 ;
- END
- END io_logical_analyzer_packet[20]
- PIN io_logical_analyzer_packet[21]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 425.590 796.000 425.870 800.000 ;
- END
- END io_logical_analyzer_packet[21]
- PIN io_logical_analyzer_packet[22]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 234.640 500.000 235.240 ;
- END
- END io_logical_analyzer_packet[22]
- PIN io_logical_analyzer_packet[23]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 527.040 500.000 527.640 ;
- END
- END io_logical_analyzer_packet[23]
- PIN io_logical_analyzer_packet[24]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 71.440 500.000 72.040 ;
- END
- END io_logical_analyzer_packet[24]
- PIN io_logical_analyzer_packet[25]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 101.290 0.000 101.570 4.000 ;
- END
- END io_logical_analyzer_packet[25]
- PIN io_logical_analyzer_packet[26]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 183.640 4.000 184.240 ;
- END
- END io_logical_analyzer_packet[26]
- PIN io_logical_analyzer_packet[27]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 139.440 500.000 140.040 ;
- END
- END io_logical_analyzer_packet[27]
- PIN io_logical_analyzer_packet[28]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 347.390 0.000 347.670 4.000 ;
- END
- END io_logical_analyzer_packet[28]
- PIN io_logical_analyzer_packet[29]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 697.040 4.000 697.640 ;
- END
- END io_logical_analyzer_packet[29]
- PIN io_logical_analyzer_packet[2]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 308.290 796.000 308.570 800.000 ;
- END
- END io_logical_analyzer_packet[2]
- PIN io_logical_analyzer_packet[30]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 9.290 0.000 9.570 4.000 ;
- END
- END io_logical_analyzer_packet[30]
- PIN io_logical_analyzer_packet[31]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 391.040 4.000 391.640 ;
- END
- END io_logical_analyzer_packet[31]
- PIN io_logical_analyzer_packet[32]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 23.840 4.000 24.440 ;
- END
- END io_logical_analyzer_packet[32]
- PIN io_logical_analyzer_packet[33]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 550.840 4.000 551.440 ;
- END
- END io_logical_analyzer_packet[33]
- PIN io_logical_analyzer_packet[34]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 101.290 796.000 101.570 800.000 ;
- END
- END io_logical_analyzer_packet[34]
- PIN io_logical_analyzer_packet[35]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 480.790 796.000 481.070 800.000 ;
- END
- END io_logical_analyzer_packet[35]
- PIN io_logical_analyzer_packet[36]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 365.790 796.000 366.070 800.000 ;
- END
- END io_logical_analyzer_packet[36]
- PIN io_logical_analyzer_packet[37]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 16.190 796.000 16.470 800.000 ;
- END
- END io_logical_analyzer_packet[37]
- PIN io_logical_analyzer_packet[38]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 227.790 0.000 228.070 4.000 ;
- END
- END io_logical_analyzer_packet[38]
- PIN io_logical_analyzer_packet[39]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 190.990 796.000 191.270 800.000 ;
- END
- END io_logical_analyzer_packet[39]
- PIN io_logical_analyzer_packet[3]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 98.990 0.000 99.270 4.000 ;
- END
- END io_logical_analyzer_packet[3]
- PIN io_logical_analyzer_packet[40]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 73.690 0.000 73.970 4.000 ;
- END
- END io_logical_analyzer_packet[40]
- PIN io_logical_analyzer_packet[41]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 30.640 500.000 31.240 ;
- END
- END io_logical_analyzer_packet[41]
- PIN io_logical_analyzer_packet[42]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 407.190 796.000 407.470 800.000 ;
- END
- END io_logical_analyzer_packet[42]
- PIN io_logical_analyzer_packet[43]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 193.290 0.000 193.570 4.000 ;
- END
- END io_logical_analyzer_packet[43]
- PIN io_logical_analyzer_packet[44]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 785.440 4.000 786.040 ;
- END
- END io_logical_analyzer_packet[44]
- PIN io_logical_analyzer_packet[45]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 331.290 796.000 331.570 800.000 ;
- END
- END io_logical_analyzer_packet[45]
- PIN io_logical_analyzer_packet[46]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 421.640 4.000 422.240 ;
- END
- END io_logical_analyzer_packet[46]
- PIN io_logical_analyzer_packet[47]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 27.690 796.000 27.970 800.000 ;
- END
- END io_logical_analyzer_packet[47]
- PIN io_logical_analyzer_packet[48]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 618.840 4.000 619.440 ;
- END
- END io_logical_analyzer_packet[48]
- PIN io_logical_analyzer_packet[49]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 167.990 0.000 168.270 4.000 ;
- END
- END io_logical_analyzer_packet[49]
- PIN io_logical_analyzer_packet[4]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 370.390 796.000 370.670 800.000 ;
- END
- END io_logical_analyzer_packet[4]
- PIN io_logical_analyzer_packet[50]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 296.790 0.000 297.070 4.000 ;
- END
- END io_logical_analyzer_packet[50]
- PIN io_logical_analyzer_packet[51]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 336.640 4.000 337.240 ;
- END
- END io_logical_analyzer_packet[51]
- PIN io_logical_analyzer_packet[52]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 485.390 796.000 485.670 800.000 ;
- END
- END io_logical_analyzer_packet[52]
- PIN io_logical_analyzer_packet[53]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 173.440 4.000 174.040 ;
- END
- END io_logical_analyzer_packet[53]
- PIN io_logical_analyzer_packet[54]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 234.690 0.000 234.970 4.000 ;
- END
- END io_logical_analyzer_packet[54]
- PIN io_logical_analyzer_packet[55]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 51.040 4.000 51.640 ;
- END
- END io_logical_analyzer_packet[55]
- PIN io_logical_analyzer_packet[56]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 138.090 796.000 138.370 800.000 ;
- END
- END io_logical_analyzer_packet[56]
- PIN io_logical_analyzer_packet[57]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 278.390 0.000 278.670 4.000 ;
- END
- END io_logical_analyzer_packet[57]
- PIN io_logical_analyzer_packet[58]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 523.640 500.000 524.240 ;
- END
- END io_logical_analyzer_packet[58]
- PIN io_logical_analyzer_packet[59]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 418.240 500.000 418.840 ;
- END
- END io_logical_analyzer_packet[59]
- PIN io_logical_analyzer_packet[5]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 294.490 796.000 294.770 800.000 ;
- END
- END io_logical_analyzer_packet[5]
- PIN io_logical_analyzer_packet[60]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 34.040 500.000 34.640 ;
- END
- END io_logical_analyzer_packet[60]
- PIN io_logical_analyzer_packet[61]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 230.090 0.000 230.370 4.000 ;
- END
- END io_logical_analyzer_packet[61]
- PIN io_logical_analyzer_packet[62]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 225.490 796.000 225.770 800.000 ;
- END
- END io_logical_analyzer_packet[62]
- PIN io_logical_analyzer_packet[63]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 666.440 500.000 667.040 ;
- END
- END io_logical_analyzer_packet[63]
- PIN io_logical_analyzer_packet[64]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 350.240 4.000 350.840 ;
- END
- END io_logical_analyzer_packet[64]
- PIN io_logical_analyzer_packet[65]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 102.040 4.000 102.640 ;
- END
- END io_logical_analyzer_packet[65]
- PIN io_logical_analyzer_packet[66]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 73.690 796.000 73.970 800.000 ;
- END
- END io_logical_analyzer_packet[66]
- PIN io_logical_analyzer_packet[67]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 370.640 500.000 371.240 ;
- END
- END io_logical_analyzer_packet[67]
- PIN io_logical_analyzer_packet[68]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 479.440 4.000 480.040 ;
- END
- END io_logical_analyzer_packet[68]
- PIN io_logical_analyzer_packet[69]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 202.490 0.000 202.770 4.000 ;
- END
- END io_logical_analyzer_packet[69]
- PIN io_logical_analyzer_packet[6]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 469.240 4.000 469.840 ;
- END
- END io_logical_analyzer_packet[6]
- PIN io_logical_analyzer_packet[70]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 261.840 4.000 262.440 ;
- END
- END io_logical_analyzer_packet[70]
- PIN io_logical_analyzer_packet[71]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 513.440 4.000 514.040 ;
- END
- END io_logical_analyzer_packet[71]
- PIN io_logical_analyzer_packet[72]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 333.590 0.000 333.870 4.000 ;
- END
- END io_logical_analyzer_packet[72]
- PIN io_logical_analyzer_packet[73]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 434.790 796.000 435.070 800.000 ;
- END
- END io_logical_analyzer_packet[73]
- PIN io_logical_analyzer_packet[74]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 248.240 500.000 248.840 ;
- END
- END io_logical_analyzer_packet[74]
- PIN io_logical_analyzer_packet[75]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 81.640 4.000 82.240 ;
- END
- END io_logical_analyzer_packet[75]
- PIN io_logical_analyzer_packet[76]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 450.890 796.000 451.170 800.000 ;
- END
- END io_logical_analyzer_packet[76]
- PIN io_logical_analyzer_packet[77]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 278.390 796.000 278.670 800.000 ;
- END
- END io_logical_analyzer_packet[77]
- PIN io_logical_analyzer_packet[78]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 323.040 4.000 323.640 ;
- END
- END io_logical_analyzer_packet[78]
- PIN io_logical_analyzer_packet[79]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 299.090 796.000 299.370 800.000 ;
- END
- END io_logical_analyzer_packet[79]
- PIN io_logical_analyzer_packet[7]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 128.890 796.000 129.170 800.000 ;
- END
- END io_logical_analyzer_packet[7]
- PIN io_logical_analyzer_packet[80]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 459.040 500.000 459.640 ;
- END
- END io_logical_analyzer_packet[80]
- PIN io_logical_analyzer_packet[81]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 588.240 500.000 588.840 ;
- END
- END io_logical_analyzer_packet[81]
- PIN io_logical_analyzer_packet[82]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 159.840 4.000 160.440 ;
- END
- END io_logical_analyzer_packet[82]
- PIN io_logical_analyzer_packet[83]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 131.190 796.000 131.470 800.000 ;
- END
- END io_logical_analyzer_packet[83]
- PIN io_logical_analyzer_packet[84]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 520.240 500.000 520.840 ;
- END
- END io_logical_analyzer_packet[84]
- PIN io_logical_analyzer_packet[85]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 430.190 0.000 430.470 4.000 ;
- END
- END io_logical_analyzer_packet[85]
- PIN io_logical_analyzer_packet[8]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 126.590 796.000 126.870 800.000 ;
- END
- END io_logical_analyzer_packet[8]
- PIN io_logical_analyzer_packet[9]
+ PIN gpio_clk
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met2 ;
- RECT 209.390 796.000 209.670 800.000 ;
- END
- END io_logical_analyzer_packet[9]
- PIN io_sram0_connections[0]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 425.590 0.000 425.870 4.000 ;
- END
- END io_sram0_connections[0]
- PIN io_sram0_connections[10]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 25.390 796.000 25.670 800.000 ;
- END
- END io_sram0_connections[10]
- PIN io_sram0_connections[11]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 207.440 4.000 208.040 ;
- END
- END io_sram0_connections[11]
- PIN io_sram0_connections[12]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 622.240 500.000 622.840 ;
- END
- END io_sram0_connections[12]
- PIN io_sram0_connections[13]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 287.590 0.000 287.870 4.000 ;
- END
- END io_sram0_connections[13]
- PIN io_sram0_connections[14]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 172.590 796.000 172.870 800.000 ;
- END
- END io_sram0_connections[14]
- PIN io_sram0_connections[15]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 547.440 4.000 548.040 ;
- END
- END io_sram0_connections[15]
- PIN io_sram0_connections[16]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 326.440 500.000 327.040 ;
- END
- END io_sram0_connections[16]
- PIN io_sram0_connections[17]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 384.240 4.000 384.840 ;
- END
- END io_sram0_connections[17]
- PIN io_sram0_connections[18]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 110.490 0.000 110.770 4.000 ;
- END
- END io_sram0_connections[18]
- PIN io_sram0_connections[19]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 724.240 4.000 724.840 ;
- END
- END io_sram0_connections[19]
- PIN io_sram0_connections[1]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 69.090 796.000 69.370 800.000 ;
- END
- END io_sram0_connections[1]
- PIN io_sram0_connections[20]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 193.290 796.000 193.570 800.000 ;
- END
- END io_sram0_connections[20]
- PIN io_sram0_connections[21]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 510.040 4.000 510.640 ;
- END
- END io_sram0_connections[21]
- PIN io_sram0_connections[22]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 278.840 4.000 279.440 ;
- END
- END io_sram0_connections[22]
- PIN io_sram0_connections[23]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 761.640 500.000 762.240 ;
- END
- END io_sram0_connections[23]
- PIN io_sram0_connections[24]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 380.840 4.000 381.440 ;
- END
- END io_sram0_connections[24]
- PIN io_sram0_connections[25]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 261.840 500.000 262.440 ;
- END
- END io_sram0_connections[25]
- PIN io_sram0_connections[26]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 262.290 0.000 262.570 4.000 ;
- END
- END io_sram0_connections[26]
- PIN io_sram0_connections[27]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 4.690 0.000 4.970 4.000 ;
- END
- END io_sram0_connections[27]
- PIN io_sram0_connections[28]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 96.690 796.000 96.970 800.000 ;
- END
- END io_sram0_connections[28]
- PIN io_sram0_connections[29]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 149.640 500.000 150.240 ;
- END
- END io_sram0_connections[29]
- PIN io_sram0_connections[2]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 46.090 796.000 46.370 800.000 ;
- END
- END io_sram0_connections[2]
- PIN io_sram0_connections[30]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 108.190 0.000 108.470 4.000 ;
- END
- END io_sram0_connections[30]
- PIN io_sram0_connections[31]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 13.890 0.000 14.170 4.000 ;
- END
- END io_sram0_connections[31]
- PIN io_sram0_connections[32]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 340.040 4.000 340.640 ;
- END
- END io_sram0_connections[32]
- PIN io_sram0_connections[33]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 411.790 796.000 412.070 800.000 ;
- END
- END io_sram0_connections[33]
- PIN io_sram0_connections[34]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 13.640 500.000 14.240 ;
- END
- END io_sram0_connections[34]
- PIN io_sram0_connections[35]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 105.890 796.000 106.170 800.000 ;
- END
- END io_sram0_connections[35]
- PIN io_sram0_connections[36]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 319.790 796.000 320.070 800.000 ;
- END
- END io_sram0_connections[36]
- PIN io_sram0_connections[37]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 473.890 796.000 474.170 800.000 ;
- END
- END io_sram0_connections[37]
- PIN io_sram0_connections[38]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 98.990 796.000 99.270 800.000 ;
- END
- END io_sram0_connections[38]
- PIN io_sram0_connections[39]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 425.040 500.000 425.640 ;
- END
- END io_sram0_connections[39]
- PIN io_sram0_connections[3]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 55.290 0.000 55.570 4.000 ;
- END
- END io_sram0_connections[3]
- PIN io_sram0_connections[40]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
RECT 207.090 796.000 207.370 800.000 ;
END
- END io_sram0_connections[40]
- PIN io_sram0_connections[41]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 40.840 4.000 41.440 ;
- END
- END io_sram0_connections[41]
- PIN io_sram0_connections[42]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 204.790 796.000 205.070 800.000 ;
- END
- END io_sram0_connections[42]
- PIN io_sram0_connections[43]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 301.390 796.000 301.670 800.000 ;
- END
- END io_sram0_connections[43]
- PIN io_sram0_connections[44]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 163.240 500.000 163.840 ;
- END
- END io_sram0_connections[44]
- PIN io_sram0_connections[45]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 275.440 4.000 276.040 ;
- END
- END io_sram0_connections[45]
- PIN io_sram0_connections[46]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 710.640 500.000 711.240 ;
- END
- END io_sram0_connections[46]
- PIN io_sram0_connections[47]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 173.440 500.000 174.040 ;
- END
- END io_sram0_connections[47]
- PIN io_sram0_connections[48]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 397.840 500.000 398.440 ;
- END
- END io_sram0_connections[48]
- PIN io_sram0_connections[49]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 200.190 0.000 200.470 4.000 ;
- END
- END io_sram0_connections[49]
- PIN io_sram0_connections[4]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 669.840 500.000 670.440 ;
- END
- END io_sram0_connections[4]
- PIN io_sram0_connections[50]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 374.990 0.000 375.270 4.000 ;
- END
- END io_sram0_connections[50]
- PIN io_sram0_connections[51]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 346.840 4.000 347.440 ;
- END
- END io_sram0_connections[51]
- PIN io_sram0_connections[52]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 51.040 500.000 51.640 ;
- END
- END io_sram0_connections[52]
- PIN io_sram0_connections[53]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 213.990 0.000 214.270 4.000 ;
- END
- END io_sram0_connections[53]
- PIN io_sram0_connections[54]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 765.040 500.000 765.640 ;
- END
- END io_sram0_connections[54]
- PIN io_sram0_connections[5]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 122.440 500.000 123.040 ;
- END
- END io_sram0_connections[5]
- PIN io_sram0_connections[6]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 676.640 4.000 677.240 ;
- END
- END io_sram0_connections[6]
- PIN io_sram0_connections[7]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 358.890 796.000 359.170 800.000 ;
- END
- END io_sram0_connections[7]
- PIN io_sram0_connections[8]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 282.240 4.000 282.840 ;
- END
- END io_sram0_connections[8]
- PIN io_sram0_connections[9]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 404.640 4.000 405.240 ;
- END
- END io_sram0_connections[9]
- PIN io_sram0_r0_in[0]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 574.640 500.000 575.240 ;
- END
- END io_sram0_r0_in[0]
- PIN io_sram0_r0_in[10]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 57.840 500.000 58.440 ;
- END
- END io_sram0_r0_in[10]
- PIN io_sram0_r0_in[11]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 156.490 796.000 156.770 800.000 ;
- END
- END io_sram0_r0_in[11]
- PIN io_sram0_r0_in[12]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 571.240 4.000 571.840 ;
- END
- END io_sram0_r0_in[12]
- PIN io_sram0_r0_in[13]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 462.440 500.000 463.040 ;
- END
- END io_sram0_r0_in[13]
- PIN io_sram0_r0_in[14]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 81.640 500.000 82.240 ;
- END
- END io_sram0_r0_in[14]
- PIN io_sram0_r0_in[15]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 146.240 4.000 146.840 ;
- END
- END io_sram0_r0_in[15]
- PIN io_sram0_r0_in[16]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 105.890 0.000 106.170 4.000 ;
- END
- END io_sram0_r0_in[16]
- PIN io_sram0_r0_in[17]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 41.490 796.000 41.770 800.000 ;
- END
- END io_sram0_r0_in[17]
- PIN io_sram0_r0_in[18]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 416.390 796.000 416.670 800.000 ;
- END
- END io_sram0_r0_in[18]
- PIN io_sram0_r0_in[19]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 639.240 500.000 639.840 ;
- END
- END io_sram0_r0_in[19]
- PIN io_sram0_r0_in[1]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 788.840 500.000 789.440 ;
- END
- END io_sram0_r0_in[1]
- PIN io_sram0_r0_in[20]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 379.590 796.000 379.870 800.000 ;
- END
- END io_sram0_r0_in[20]
- PIN io_sram0_r0_in[21]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 347.390 796.000 347.670 800.000 ;
- END
- END io_sram0_r0_in[21]
- PIN io_sram0_r0_in[22]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 612.040 4.000 612.640 ;
- END
- END io_sram0_r0_in[22]
- PIN io_sram0_r0_in[23]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 285.290 796.000 285.570 800.000 ;
- END
- END io_sram0_r0_in[23]
- PIN io_sram0_r0_in[24]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 174.890 0.000 175.170 4.000 ;
- END
- END io_sram0_r0_in[24]
- PIN io_sram0_r0_in[25]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 115.640 4.000 116.240 ;
- END
- END io_sram0_r0_in[25]
- PIN io_sram0_r0_in[26]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 193.840 4.000 194.440 ;
- END
- END io_sram0_r0_in[26]
- PIN io_sram0_r0_in[27]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 487.690 796.000 487.970 800.000 ;
- END
- END io_sram0_r0_in[27]
- PIN io_sram0_r0_in[28]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 306.040 500.000 306.640 ;
- END
- END io_sram0_r0_in[28]
- PIN io_sram0_r0_in[29]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 374.040 500.000 374.640 ;
- END
- END io_sram0_r0_in[29]
- PIN io_sram0_r0_in[2]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 561.040 4.000 561.640 ;
- END
- END io_sram0_r0_in[2]
- PIN io_sram0_r0_in[30]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 161.090 796.000 161.370 800.000 ;
- END
- END io_sram0_r0_in[30]
- PIN io_sram0_r0_in[31]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 437.090 796.000 437.370 800.000 ;
- END
- END io_sram0_r0_in[31]
- PIN io_sram0_r0_in[3]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 446.290 0.000 446.570 4.000 ;
- END
- END io_sram0_r0_in[3]
- PIN io_sram0_r0_in[4]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 489.640 500.000 490.240 ;
- END
- END io_sram0_r0_in[4]
- PIN io_sram0_r0_in[5]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 132.640 500.000 133.240 ;
- END
- END io_sram0_r0_in[5]
- PIN io_sram0_r0_in[6]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 241.440 4.000 242.040 ;
- END
- END io_sram0_r0_in[6]
- PIN io_sram0_r0_in[7]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 792.240 500.000 792.840 ;
- END
- END io_sram0_r0_in[7]
- PIN io_sram0_r0_in[8]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 530.440 500.000 531.040 ;
- END
- END io_sram0_r0_in[8]
- PIN io_sram0_r0_in[9]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 482.840 4.000 483.440 ;
- END
- END io_sram0_r0_in[9]
- PIN io_sram0_rw_in[0]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 469.290 796.000 469.570 800.000 ;
- END
- END io_sram0_rw_in[0]
- PIN io_sram0_rw_in[10]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 782.040 500.000 782.640 ;
- END
- END io_sram0_rw_in[10]
- PIN io_sram0_rw_in[11]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 737.840 4.000 738.440 ;
- END
- END io_sram0_rw_in[11]
- PIN io_sram0_rw_in[12]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 294.490 0.000 294.770 4.000 ;
- END
- END io_sram0_rw_in[12]
- PIN io_sram0_rw_in[13]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 98.640 500.000 99.240 ;
- END
- END io_sram0_rw_in[13]
- PIN io_sram0_rw_in[14]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 394.440 4.000 395.040 ;
- END
- END io_sram0_rw_in[14]
- PIN io_sram0_rw_in[15]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 80.590 0.000 80.870 4.000 ;
- END
- END io_sram0_rw_in[15]
- PIN io_sram0_rw_in[16]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 13.890 796.000 14.170 800.000 ;
- END
- END io_sram0_rw_in[16]
- PIN io_sram0_rw_in[17]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 346.840 500.000 347.440 ;
- END
- END io_sram0_rw_in[17]
- PIN io_sram0_rw_in[18]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 520.240 4.000 520.840 ;
- END
- END io_sram0_rw_in[18]
- PIN io_sram0_rw_in[19]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 673.240 500.000 673.840 ;
- END
- END io_sram0_rw_in[19]
- PIN io_sram0_rw_in[1]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 503.240 4.000 503.840 ;
- END
- END io_sram0_rw_in[1]
- PIN io_sram0_rw_in[20]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 59.890 796.000 60.170 800.000 ;
- END
- END io_sram0_rw_in[20]
- PIN io_sram0_rw_in[21]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 308.290 0.000 308.570 4.000 ;
- END
- END io_sram0_rw_in[21]
- PIN io_sram0_rw_in[22]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 89.790 0.000 90.070 4.000 ;
- END
- END io_sram0_rw_in[22]
- PIN io_sram0_rw_in[23]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 408.040 4.000 408.640 ;
- END
- END io_sram0_rw_in[23]
- PIN io_sram0_rw_in[24]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 207.440 500.000 208.040 ;
- END
- END io_sram0_rw_in[24]
- PIN io_sram0_rw_in[25]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 112.790 796.000 113.070 800.000 ;
- END
- END io_sram0_rw_in[25]
- PIN io_sram0_rw_in[26]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 117.390 0.000 117.670 4.000 ;
- END
- END io_sram0_rw_in[26]
- PIN io_sram0_rw_in[27]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 322.090 796.000 322.370 800.000 ;
- END
- END io_sram0_rw_in[27]
- PIN io_sram0_rw_in[28]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 140.390 0.000 140.670 4.000 ;
- END
- END io_sram0_rw_in[28]
- PIN io_sram0_rw_in[29]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 272.040 4.000 272.640 ;
- END
- END io_sram0_rw_in[29]
- PIN io_sram0_rw_in[2]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 445.440 500.000 446.040 ;
- END
- END io_sram0_rw_in[2]
- PIN io_sram0_rw_in[30]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 230.090 796.000 230.370 800.000 ;
- END
- END io_sram0_rw_in[30]
- PIN io_sram0_rw_in[31]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 748.040 500.000 748.640 ;
- END
- END io_sram0_rw_in[31]
- PIN io_sram0_rw_in[3]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 151.890 796.000 152.170 800.000 ;
- END
- END io_sram0_rw_in[3]
- PIN io_sram0_rw_in[4]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 345.090 796.000 345.370 800.000 ;
- END
- END io_sram0_rw_in[4]
- PIN io_sram0_rw_in[5]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 758.240 500.000 758.840 ;
- END
- END io_sram0_rw_in[5]
- PIN io_sram0_rw_in[6]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 365.790 0.000 366.070 4.000 ;
- END
- END io_sram0_rw_in[6]
- PIN io_sram0_rw_in[7]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 537.240 4.000 537.840 ;
- END
- END io_sram0_rw_in[7]
- PIN io_sram0_rw_in[8]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 612.040 500.000 612.640 ;
- END
- END io_sram0_rw_in[8]
- PIN io_sram0_rw_in[9]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 11.590 0.000 11.870 4.000 ;
- END
- END io_sram0_rw_in[9]
- PIN io_sram1_connections[0]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 200.640 4.000 201.240 ;
- END
- END io_sram1_connections[0]
- PIN io_sram1_connections[10]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 493.040 4.000 493.640 ;
- END
- END io_sram1_connections[10]
- PIN io_sram1_connections[11]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 386.490 0.000 386.770 4.000 ;
- END
- END io_sram1_connections[11]
- PIN io_sram1_connections[12]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 652.840 4.000 653.440 ;
- END
- END io_sram1_connections[12]
- PIN io_sram1_connections[13]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 466.990 0.000 467.270 4.000 ;
- END
- END io_sram1_connections[13]
- PIN io_sram1_connections[14]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 632.440 500.000 633.040 ;
- END
- END io_sram1_connections[14]
- PIN io_sram1_connections[15]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 343.440 4.000 344.040 ;
- END
- END io_sram1_connections[15]
- PIN io_sram1_connections[16]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 547.440 500.000 548.040 ;
- END
- END io_sram1_connections[16]
- PIN io_sram1_connections[17]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 363.490 0.000 363.770 4.000 ;
- END
- END io_sram1_connections[17]
- PIN io_sram1_connections[18]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 232.390 0.000 232.670 4.000 ;
- END
- END io_sram1_connections[18]
- PIN io_sram1_connections[19]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 187.040 4.000 187.640 ;
- END
- END io_sram1_connections[19]
- PIN io_sram1_connections[1]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 367.240 4.000 367.840 ;
- END
- END io_sram1_connections[1]
- PIN io_sram1_connections[20]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 795.640 4.000 796.240 ;
- END
- END io_sram1_connections[20]
- PIN io_sram1_connections[21]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 741.240 500.000 741.840 ;
- END
- END io_sram1_connections[21]
- PIN io_sram1_connections[22]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 239.290 796.000 239.570 800.000 ;
- END
- END io_sram1_connections[22]
- PIN io_sram1_connections[23]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 328.990 0.000 329.270 4.000 ;
- END
- END io_sram1_connections[23]
- PIN io_sram1_connections[24]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 190.990 0.000 191.270 4.000 ;
- END
- END io_sram1_connections[24]
- PIN io_sram1_connections[25]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 387.640 4.000 388.240 ;
- END
- END io_sram1_connections[25]
- PIN io_sram1_connections[26]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 122.440 4.000 123.040 ;
- END
- END io_sram1_connections[26]
- PIN io_sram1_connections[27]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 409.490 796.000 409.770 800.000 ;
- END
- END io_sram1_connections[27]
- PIN io_sram1_connections[28]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 115.090 796.000 115.370 800.000 ;
- END
- END io_sram1_connections[28]
- PIN io_sram1_connections[29]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 356.590 796.000 356.870 800.000 ;
- END
- END io_sram1_connections[29]
- PIN io_sram1_connections[2]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 139.440 4.000 140.040 ;
- END
- END io_sram1_connections[2]
- PIN io_sram1_connections[30]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 578.040 500.000 578.640 ;
- END
- END io_sram1_connections[30]
- PIN io_sram1_connections[31]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 697.040 500.000 697.640 ;
- END
- END io_sram1_connections[31]
- PIN io_sram1_connections[32]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 117.390 796.000 117.670 800.000 ;
- END
- END io_sram1_connections[32]
- PIN io_sram1_connections[33]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 124.290 796.000 124.570 800.000 ;
- END
- END io_sram1_connections[33]
- PIN io_sram1_connections[34]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 395.690 796.000 395.970 800.000 ;
- END
- END io_sram1_connections[34]
- PIN io_sram1_connections[35]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 381.890 796.000 382.170 800.000 ;
- END
- END io_sram1_connections[35]
- PIN io_sram1_connections[36]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 227.840 4.000 228.440 ;
- END
- END io_sram1_connections[36]
- PIN io_sram1_connections[37]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 319.640 500.000 320.240 ;
- END
- END io_sram1_connections[37]
- PIN io_sram1_connections[38]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 476.040 4.000 476.640 ;
- END
- END io_sram1_connections[38]
- PIN io_sram1_connections[39]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 253.090 796.000 253.370 800.000 ;
- END
- END io_sram1_connections[39]
- PIN io_sram1_connections[3]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 285.640 4.000 286.240 ;
- END
- END io_sram1_connections[3]
- PIN io_sram1_connections[40]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 452.240 500.000 452.840 ;
- END
- END io_sram1_connections[40]
- PIN io_sram1_connections[41]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 455.490 0.000 455.770 4.000 ;
- END
- END io_sram1_connections[41]
- PIN io_sram1_connections[42]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 158.790 0.000 159.070 4.000 ;
- END
- END io_sram1_connections[42]
- PIN io_sram1_connections[43]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 6.990 796.000 7.270 800.000 ;
- END
- END io_sram1_connections[43]
- PIN io_sram1_connections[44]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 241.590 796.000 241.870 800.000 ;
- END
- END io_sram1_connections[44]
- PIN io_sram1_connections[45]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 693.640 4.000 694.240 ;
- END
- END io_sram1_connections[45]
- PIN io_sram1_connections[46]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 418.690 0.000 418.970 4.000 ;
- END
- END io_sram1_connections[46]
- PIN io_sram1_connections[47]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 170.040 500.000 170.640 ;
- END
- END io_sram1_connections[47]
- PIN io_sram1_connections[48]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 170.290 796.000 170.570 800.000 ;
- END
- END io_sram1_connections[48]
- PIN io_sram1_connections[49]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 30.640 4.000 31.240 ;
- END
- END io_sram1_connections[49]
- PIN io_sram1_connections[4]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 460.090 0.000 460.370 4.000 ;
- END
- END io_sram1_connections[4]
- PIN io_sram1_connections[50]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 430.190 796.000 430.470 800.000 ;
- END
- END io_sram1_connections[50]
- PIN io_sram1_connections[51]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 236.990 0.000 237.270 4.000 ;
- END
- END io_sram1_connections[51]
- PIN io_sram1_connections[52]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 197.890 0.000 198.170 4.000 ;
- END
- END io_sram1_connections[52]
- PIN io_sram1_connections[53]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 326.690 0.000 326.970 4.000 ;
- END
- END io_sram1_connections[53]
- PIN io_sram1_connections[54]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 618.840 500.000 619.440 ;
- END
- END io_sram1_connections[54]
- PIN io_sram1_connections[5]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 309.440 500.000 310.040 ;
- END
- END io_sram1_connections[5]
- PIN io_sram1_connections[6]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 299.240 4.000 299.840 ;
- END
- END io_sram1_connections[6]
- PIN io_sram1_connections[7]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 441.690 796.000 441.970 800.000 ;
- END
- END io_sram1_connections[7]
- PIN io_sram1_connections[8]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 391.040 500.000 391.640 ;
- END
- END io_sram1_connections[8]
- PIN io_sram1_connections[9]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 492.290 0.000 492.570 4.000 ;
- END
- END io_sram1_connections[9]
- PIN io_sram1_ro_in[0]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 340.490 0.000 340.770 4.000 ;
- END
- END io_sram1_ro_in[0]
- PIN io_sram1_ro_in[10]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 217.640 4.000 218.240 ;
- END
- END io_sram1_ro_in[10]
- PIN io_sram1_ro_in[11]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 223.190 0.000 223.470 4.000 ;
- END
- END io_sram1_ro_in[11]
- PIN io_sram1_ro_in[12]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 165.690 0.000 165.970 4.000 ;
- END
- END io_sram1_ro_in[12]
- PIN io_sram1_ro_in[13]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 132.640 4.000 133.240 ;
- END
- END io_sram1_ro_in[13]
- PIN io_sram1_ro_in[14]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 4.690 796.000 4.970 800.000 ;
- END
- END io_sram1_ro_in[14]
- PIN io_sram1_ro_in[15]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 11.590 796.000 11.870 800.000 ;
- END
- END io_sram1_ro_in[15]
- PIN io_sram1_ro_in[16]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 361.190 796.000 361.470 800.000 ;
- END
- END io_sram1_ro_in[16]
- PIN io_sram1_ro_in[17]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 581.440 4.000 582.040 ;
- END
- END io_sram1_ro_in[17]
- PIN io_sram1_ro_in[18]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 190.440 500.000 191.040 ;
- END
- END io_sram1_ro_in[18]
- PIN io_sram1_ro_in[19]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 683.440 4.000 684.040 ;
- END
- END io_sram1_ro_in[19]
- PIN io_sram1_ro_in[1]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 397.990 0.000 398.270 4.000 ;
- END
- END io_sram1_ro_in[1]
- PIN io_sram1_ro_in[20]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 469.240 500.000 469.840 ;
- END
- END io_sram1_ro_in[20]
- PIN io_sram1_ro_in[21]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 184.090 0.000 184.370 4.000 ;
- END
- END io_sram1_ro_in[21]
- PIN io_sram1_ro_in[22]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 218.590 796.000 218.870 800.000 ;
- END
- END io_sram1_ro_in[22]
- PIN io_sram1_ro_in[23]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 312.890 0.000 313.170 4.000 ;
- END
- END io_sram1_ro_in[23]
- PIN io_sram1_ro_in[24]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 78.290 0.000 78.570 4.000 ;
- END
- END io_sram1_ro_in[24]
- PIN io_sram1_ro_in[25]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 217.640 500.000 218.240 ;
- END
- END io_sram1_ro_in[25]
- PIN io_sram1_ro_in[26]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 601.840 4.000 602.440 ;
- END
- END io_sram1_ro_in[26]
- PIN io_sram1_ro_in[27]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 381.890 0.000 382.170 4.000 ;
- END
- END io_sram1_ro_in[27]
- PIN io_sram1_ro_in[28]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 434.790 0.000 435.070 4.000 ;
- END
- END io_sram1_ro_in[28]
- PIN io_sram1_ro_in[29]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 605.240 4.000 605.840 ;
- END
- END io_sram1_ro_in[29]
- PIN io_sram1_ro_in[2]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 27.240 500.000 27.840 ;
- END
- END io_sram1_ro_in[2]
- PIN io_sram1_ro_in[30]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 487.690 0.000 487.970 4.000 ;
- END
- END io_sram1_ro_in[30]
- PIN io_sram1_ro_in[31]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 782.040 4.000 782.640 ;
- END
- END io_sram1_ro_in[31]
- PIN io_sram1_ro_in[3]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 204.040 4.000 204.640 ;
- END
- END io_sram1_ro_in[3]
- PIN io_sram1_ro_in[4]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 52.990 796.000 53.270 800.000 ;
- END
- END io_sram1_ro_in[4]
- PIN io_sram1_ro_in[5]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 455.640 4.000 456.240 ;
- END
- END io_sram1_ro_in[5]
- PIN io_sram1_ro_in[6]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 204.040 500.000 204.640 ;
- END
- END io_sram1_ro_in[6]
- PIN io_sram1_ro_in[7]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 428.440 500.000 429.040 ;
- END
- END io_sram1_ro_in[7]
- PIN io_sram1_ro_in[8]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 438.640 500.000 439.240 ;
- END
- END io_sram1_ro_in[8]
- PIN io_sram1_ro_in[9]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 64.490 796.000 64.770 800.000 ;
- END
- END io_sram1_ro_in[9]
- PIN io_sram1_rw_in[0]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 656.240 4.000 656.840 ;
- END
- END io_sram1_rw_in[0]
- PIN io_sram1_rw_in[10]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 64.640 4.000 65.240 ;
- END
- END io_sram1_rw_in[10]
- PIN io_sram1_rw_in[11]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 471.590 796.000 471.870 800.000 ;
- END
- END io_sram1_rw_in[11]
- PIN io_sram1_rw_in[12]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 523.640 4.000 524.240 ;
- END
- END io_sram1_rw_in[12]
- PIN io_sram1_rw_in[13]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 533.840 500.000 534.440 ;
- END
- END io_sram1_rw_in[13]
- PIN io_sram1_rw_in[14]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 409.490 0.000 409.770 4.000 ;
- END
- END io_sram1_rw_in[14]
- PIN io_sram1_rw_in[15]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 36.890 0.000 37.170 4.000 ;
- END
- END io_sram1_rw_in[15]
- PIN io_sram1_rw_in[16]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 75.990 796.000 76.270 800.000 ;
- END
- END io_sram1_rw_in[16]
- PIN io_sram1_rw_in[17]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 95.240 500.000 95.840 ;
- END
- END io_sram1_rw_in[17]
- PIN io_sram1_rw_in[18]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 129.240 500.000 129.840 ;
- END
- END io_sram1_rw_in[18]
- PIN io_sram1_rw_in[19]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 37.440 500.000 38.040 ;
- END
- END io_sram1_rw_in[19]
- PIN io_sram1_rw_in[1]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 751.440 500.000 752.040 ;
- END
- END io_sram1_rw_in[1]
- PIN io_sram1_rw_in[20]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 54.440 500.000 55.040 ;
- END
- END io_sram1_rw_in[20]
- PIN io_sram1_rw_in[21]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 754.840 500.000 755.440 ;
- END
- END io_sram1_rw_in[21]
- PIN io_sram1_rw_in[22]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 115.090 0.000 115.370 4.000 ;
- END
- END io_sram1_rw_in[22]
- PIN io_sram1_rw_in[23]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 220.890 796.000 221.170 800.000 ;
- END
- END io_sram1_rw_in[23]
- PIN io_sram1_rw_in[24]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 404.890 796.000 405.170 800.000 ;
- END
- END io_sram1_rw_in[24]
- PIN io_sram1_rw_in[25]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 394.440 500.000 395.040 ;
- END
- END io_sram1_rw_in[25]
- PIN io_sram1_rw_in[26]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 442.040 4.000 442.640 ;
- END
- END io_sram1_rw_in[26]
- PIN io_sram1_rw_in[27]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 768.440 4.000 769.040 ;
- END
- END io_sram1_rw_in[27]
- PIN io_sram1_rw_in[28]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 13.640 4.000 14.240 ;
- END
- END io_sram1_rw_in[28]
- PIN io_sram1_rw_in[29]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 239.290 0.000 239.570 4.000 ;
- END
- END io_sram1_rw_in[29]
- PIN io_sram1_rw_in[2]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 156.490 0.000 156.770 4.000 ;
- END
- END io_sram1_rw_in[2]
- PIN io_sram1_rw_in[30]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 172.590 0.000 172.870 4.000 ;
- END
- END io_sram1_rw_in[30]
- PIN io_sram1_rw_in[31]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 94.390 796.000 94.670 800.000 ;
- END
- END io_sram1_rw_in[31]
- PIN io_sram1_rw_in[3]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 734.440 500.000 735.040 ;
- END
- END io_sram1_rw_in[3]
- PIN io_sram1_rw_in[4]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 455.640 500.000 456.240 ;
- END
- END io_sram1_rw_in[4]
- PIN io_sram1_rw_in[5]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 278.840 500.000 279.440 ;
- END
- END io_sram1_rw_in[5]
- PIN io_sram1_rw_in[6]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 47.640 500.000 48.240 ;
- END
- END io_sram1_rw_in[6]
- PIN io_sram1_rw_in[7]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 494.590 796.000 494.870 800.000 ;
- END
- END io_sram1_rw_in[7]
- PIN io_sram1_rw_in[8]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 43.790 796.000 44.070 800.000 ;
- END
- END io_sram1_rw_in[8]
- PIN io_sram1_rw_in[9]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 411.440 4.000 412.040 ;
- END
- END io_sram1_rw_in[9]
- PIN io_sram2_connections[0]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 388.790 0.000 389.070 4.000 ;
- END
- END io_sram2_connections[0]
- PIN io_sram2_connections[10]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 29.990 796.000 30.270 800.000 ;
- END
- END io_sram2_connections[10]
- PIN io_sram2_connections[11]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 146.240 500.000 146.840 ;
- END
- END io_sram2_connections[11]
- PIN io_sram2_connections[12]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 503.240 500.000 503.840 ;
- END
- END io_sram2_connections[12]
- PIN io_sram2_connections[13]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 165.690 796.000 165.970 800.000 ;
- END
- END io_sram2_connections[13]
- PIN io_sram2_connections[14]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 714.040 4.000 714.640 ;
- END
- END io_sram2_connections[14]
- PIN io_sram2_connections[15]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 295.840 4.000 296.440 ;
- END
- END io_sram2_connections[15]
- PIN io_sram2_connections[16]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 335.890 796.000 336.170 800.000 ;
- END
- END io_sram2_connections[16]
- PIN io_sram2_connections[17]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 656.240 500.000 656.840 ;
- END
- END io_sram2_connections[17]
- PIN io_sram2_connections[18]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 646.040 4.000 646.640 ;
- END
- END io_sram2_connections[18]
- PIN io_sram2_connections[19]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 6.990 0.000 7.270 4.000 ;
- END
- END io_sram2_connections[19]
- PIN io_sram2_connections[1]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 125.840 500.000 126.440 ;
- END
- END io_sram2_connections[1]
- PIN io_sram2_connections[20]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 418.690 796.000 418.970 800.000 ;
- END
- END io_sram2_connections[20]
- PIN io_sram2_connections[21]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 119.690 796.000 119.970 800.000 ;
- END
- END io_sram2_connections[21]
- PIN io_sram2_connections[22]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 370.640 4.000 371.240 ;
- END
- END io_sram2_connections[22]
- PIN io_sram2_connections[23]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 312.840 500.000 313.440 ;
- END
- END io_sram2_connections[23]
- PIN io_sram2_connections[24]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 59.890 0.000 60.170 4.000 ;
- END
- END io_sram2_connections[24]
- PIN io_sram2_connections[25]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 289.040 4.000 289.640 ;
- END
- END io_sram2_connections[25]
- PIN io_sram2_connections[26]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 567.840 4.000 568.440 ;
- END
- END io_sram2_connections[26]
- PIN io_sram2_connections[27]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 485.390 0.000 485.670 4.000 ;
- END
- END io_sram2_connections[27]
- PIN io_sram2_connections[28]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 384.190 796.000 384.470 800.000 ;
- END
- END io_sram2_connections[28]
- PIN io_sram2_connections[29]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 57.590 0.000 57.870 4.000 ;
- END
- END io_sram2_connections[29]
- PIN io_sram2_connections[2]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 87.490 0.000 87.770 4.000 ;
- END
- END io_sram2_connections[2]
- PIN io_sram2_connections[30]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 103.590 796.000 103.870 800.000 ;
- END
- END io_sram2_connections[30]
- PIN io_sram2_connections[31]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 734.440 4.000 735.040 ;
- END
- END io_sram2_connections[31]
- PIN io_sram2_connections[32]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 110.490 796.000 110.770 800.000 ;
- END
- END io_sram2_connections[32]
- PIN io_sram2_connections[33]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 686.840 4.000 687.440 ;
- END
- END io_sram2_connections[33]
- PIN io_sram2_connections[34]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 338.190 0.000 338.470 4.000 ;
- END
- END io_sram2_connections[34]
- PIN io_sram2_connections[35]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 402.590 796.000 402.870 800.000 ;
- END
- END io_sram2_connections[35]
- PIN io_sram2_connections[36]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 673.240 4.000 673.840 ;
- END
- END io_sram2_connections[36]
- PIN io_sram2_connections[37]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 87.490 796.000 87.770 800.000 ;
- END
- END io_sram2_connections[37]
- PIN io_sram2_connections[38]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 20.790 796.000 21.070 800.000 ;
- END
- END io_sram2_connections[38]
- PIN io_sram2_connections[39]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 379.590 0.000 379.870 4.000 ;
- END
- END io_sram2_connections[39]
- PIN io_sram2_connections[3]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 190.440 4.000 191.040 ;
- END
- END io_sram2_connections[3]
- PIN io_sram2_connections[40]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 292.440 4.000 293.040 ;
- END
- END io_sram2_connections[40]
- PIN io_sram2_connections[41]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 48.390 796.000 48.670 800.000 ;
- END
- END io_sram2_connections[41]
- PIN io_sram2_connections[42]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 414.090 796.000 414.370 800.000 ;
- END
- END io_sram2_connections[42]
- PIN io_sram2_connections[43]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 588.240 4.000 588.840 ;
- END
- END io_sram2_connections[43]
- PIN io_sram2_connections[44]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 761.640 4.000 762.240 ;
- END
- END io_sram2_connections[44]
- PIN io_sram2_connections[45]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 506.640 500.000 507.240 ;
- END
- END io_sram2_connections[45]
- PIN io_sram2_connections[46]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 395.690 0.000 395.970 4.000 ;
- END
- END io_sram2_connections[46]
- PIN io_sram2_connections[47]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 727.640 4.000 728.240 ;
- END
- END io_sram2_connections[47]
- PIN io_sram2_connections[4]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 295.840 500.000 296.440 ;
- END
- END io_sram2_connections[4]
- PIN io_sram2_connections[5]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 10.240 500.000 10.840 ;
- END
- END io_sram2_connections[5]
- PIN io_sram2_connections[6]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 276.090 0.000 276.370 4.000 ;
- END
- END io_sram2_connections[6]
- PIN io_sram2_connections[7]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 453.190 0.000 453.470 4.000 ;
- END
- END io_sram2_connections[7]
- PIN io_sram2_connections[8]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 238.040 4.000 238.640 ;
- END
- END io_sram2_connections[8]
- PIN io_sram2_connections[9]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 50.690 0.000 50.970 4.000 ;
- END
- END io_sram2_connections[9]
- PIN io_sram2_rw_in[0]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 350.240 500.000 350.840 ;
- END
- END io_sram2_rw_in[0]
- PIN io_sram2_rw_in[10]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 282.240 500.000 282.840 ;
- END
- END io_sram2_rw_in[10]
- PIN io_sram2_rw_in[11]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 567.840 500.000 568.440 ;
- END
- END io_sram2_rw_in[11]
- PIN io_sram2_rw_in[12]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 292.440 500.000 293.040 ;
- END
- END io_sram2_rw_in[12]
- PIN io_sram2_rw_in[13]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 608.640 4.000 609.240 ;
- END
- END io_sram2_rw_in[13]
- PIN io_sram2_rw_in[14]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 324.390 796.000 324.670 800.000 ;
- END
- END io_sram2_rw_in[14]
- PIN io_sram2_rw_in[15]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 265.240 500.000 265.840 ;
- END
- END io_sram2_rw_in[15]
- PIN io_sram2_rw_in[16]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 414.090 0.000 414.370 4.000 ;
- END
- END io_sram2_rw_in[16]
- PIN io_sram2_rw_in[17]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 264.590 796.000 264.870 800.000 ;
- END
- END io_sram2_rw_in[17]
- PIN io_sram2_rw_in[18]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 214.240 500.000 214.840 ;
- END
- END io_sram2_rw_in[18]
- PIN io_sram2_rw_in[19]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 564.440 4.000 565.040 ;
- END
- END io_sram2_rw_in[19]
- PIN io_sram2_rw_in[1]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 771.840 500.000 772.440 ;
- END
- END io_sram2_rw_in[1]
- PIN io_sram2_rw_in[20]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 443.990 796.000 444.270 800.000 ;
- END
- END io_sram2_rw_in[20]
- PIN io_sram2_rw_in[21]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 591.640 500.000 592.240 ;
- END
- END io_sram2_rw_in[21]
- PIN io_sram2_rw_in[22]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 292.190 0.000 292.470 4.000 ;
- END
- END io_sram2_rw_in[22]
- PIN io_sram2_rw_in[23]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 138.090 0.000 138.370 4.000 ;
- END
- END io_sram2_rw_in[23]
- PIN io_sram2_rw_in[24]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 310.590 796.000 310.870 800.000 ;
- END
- END io_sram2_rw_in[24]
- PIN io_sram2_rw_in[25]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 496.890 0.000 497.170 4.000 ;
- END
- END io_sram2_rw_in[25]
- PIN io_sram2_rw_in[26]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 351.990 0.000 352.270 4.000 ;
- END
- END io_sram2_rw_in[26]
- PIN io_sram2_rw_in[27]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 544.040 4.000 544.640 ;
- END
- END io_sram2_rw_in[27]
- PIN io_sram2_rw_in[28]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 496.440 4.000 497.040 ;
- END
- END io_sram2_rw_in[28]
- PIN io_sram2_rw_in[29]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 41.490 0.000 41.770 4.000 ;
- END
- END io_sram2_rw_in[29]
- PIN io_sram2_rw_in[2]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 156.440 500.000 157.040 ;
- END
- END io_sram2_rw_in[2]
- PIN io_sram2_rw_in[30]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 778.640 500.000 779.240 ;
- END
- END io_sram2_rw_in[30]
- PIN io_sram2_rw_in[31]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 115.640 500.000 116.240 ;
- END
- END io_sram2_rw_in[31]
- PIN io_sram2_rw_in[3]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 163.390 0.000 163.670 4.000 ;
- END
- END io_sram2_rw_in[3]
- PIN io_sram2_rw_in[4]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 557.640 4.000 558.240 ;
- END
- END io_sram2_rw_in[4]
- PIN io_sram2_rw_in[5]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 469.290 0.000 469.570 4.000 ;
- END
- END io_sram2_rw_in[5]
- PIN io_sram2_rw_in[6]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 380.840 500.000 381.440 ;
- END
- END io_sram2_rw_in[6]
- PIN io_sram2_rw_in[7]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 128.890 0.000 129.170 4.000 ;
- END
- END io_sram2_rw_in[7]
- PIN io_sram2_rw_in[8]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 197.890 796.000 198.170 800.000 ;
- END
- END io_sram2_rw_in[8]
- PIN io_sram2_rw_in[9]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 34.040 4.000 34.640 ;
- END
- END io_sram2_rw_in[9]
- PIN io_sram3_connections[0]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 554.240 4.000 554.840 ;
- END
- END io_sram3_connections[0]
- PIN io_sram3_connections[10]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 161.090 0.000 161.370 4.000 ;
- END
- END io_sram3_connections[10]
- PIN io_sram3_connections[11]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 717.440 4.000 718.040 ;
- END
- END io_sram3_connections[11]
- PIN io_sram3_connections[12]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 232.390 796.000 232.670 800.000 ;
- END
- END io_sram3_connections[12]
- PIN io_sram3_connections[13]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 384.190 0.000 384.470 4.000 ;
- END
- END io_sram3_connections[13]
- PIN io_sram3_connections[14]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 438.640 4.000 439.240 ;
- END
- END io_sram3_connections[14]
- PIN io_sram3_connections[15]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 479.440 500.000 480.040 ;
- END
- END io_sram3_connections[15]
- PIN io_sram3_connections[16]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 460.090 796.000 460.370 800.000 ;
- END
- END io_sram3_connections[16]
- PIN io_sram3_connections[17]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 18.490 0.000 18.770 4.000 ;
- END
- END io_sram3_connections[17]
- PIN io_sram3_connections[18]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 2.390 0.000 2.670 4.000 ;
- END
- END io_sram3_connections[18]
- PIN io_sram3_connections[19]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 78.290 796.000 78.570 800.000 ;
- END
- END io_sram3_connections[19]
- PIN io_sram3_connections[1]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 271.490 796.000 271.770 800.000 ;
- END
- END io_sram3_connections[1]
- PIN io_sram3_connections[20]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 61.240 500.000 61.840 ;
- END
- END io_sram3_connections[20]
- PIN io_sram3_connections[21]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 193.840 500.000 194.440 ;
- END
- END io_sram3_connections[21]
- PIN io_sram3_connections[22]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 44.240 4.000 44.840 ;
- END
- END io_sram3_connections[22]
- PIN io_sram3_connections[23]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 188.690 796.000 188.970 800.000 ;
- END
- END io_sram3_connections[23]
- PIN io_sram3_connections[24]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 499.840 4.000 500.440 ;
- END
- END io_sram3_connections[24]
- PIN io_sram3_connections[25]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 744.640 4.000 745.240 ;
- END
- END io_sram3_connections[25]
- PIN io_sram3_connections[26]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 402.590 0.000 402.870 4.000 ;
- END
- END io_sram3_connections[26]
- PIN io_sram3_connections[27]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 768.440 500.000 769.040 ;
- END
- END io_sram3_connections[27]
- PIN io_sram3_connections[28]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 663.040 500.000 663.640 ;
- END
- END io_sram3_connections[28]
- PIN io_sram3_connections[29]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 324.390 0.000 324.670 4.000 ;
- END
- END io_sram3_connections[29]
- PIN io_sram3_connections[2]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 112.240 500.000 112.840 ;
- END
- END io_sram3_connections[2]
- PIN io_sram3_connections[30]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 69.090 0.000 69.370 4.000 ;
- END
- END io_sram3_connections[30]
- PIN io_sram3_connections[31]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 414.840 4.000 415.440 ;
- END
- END io_sram3_connections[31]
- PIN io_sram3_connections[32]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 465.840 4.000 466.440 ;
- END
- END io_sram3_connections[32]
- PIN io_sram3_connections[33]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 748.040 4.000 748.640 ;
- END
- END io_sram3_connections[33]
- PIN io_sram3_connections[34]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 166.640 4.000 167.240 ;
- END
- END io_sram3_connections[34]
- PIN io_sram3_connections[35]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 214.240 4.000 214.840 ;
- END
- END io_sram3_connections[35]
- PIN io_sram3_connections[36]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 243.890 0.000 244.170 4.000 ;
- END
- END io_sram3_connections[36]
- PIN io_sram3_connections[37]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 737.840 500.000 738.440 ;
- END
- END io_sram3_connections[37]
- PIN io_sram3_connections[38]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 370.390 0.000 370.670 4.000 ;
- END
- END io_sram3_connections[38]
- PIN io_sram3_connections[39]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 635.840 500.000 636.440 ;
- END
- END io_sram3_connections[39]
- PIN io_sram3_connections[3]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 400.290 796.000 400.570 800.000 ;
- END
- END io_sram3_connections[3]
- PIN io_sram3_connections[40]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 54.440 4.000 55.040 ;
- END
- END io_sram3_connections[40]
- PIN io_sram3_connections[41]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 354.290 0.000 354.570 4.000 ;
- END
- END io_sram3_connections[41]
- PIN io_sram3_connections[42]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 478.490 796.000 478.770 800.000 ;
- END
- END io_sram3_connections[42]
- PIN io_sram3_connections[43]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 316.240 4.000 316.840 ;
- END
- END io_sram3_connections[43]
- PIN io_sram3_connections[44]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 317.490 796.000 317.770 800.000 ;
- END
- END io_sram3_connections[44]
- PIN io_sram3_connections[45]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 483.090 0.000 483.370 4.000 ;
- END
- END io_sram3_connections[45]
- PIN io_sram3_connections[4]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 262.290 796.000 262.570 800.000 ;
- END
- END io_sram3_connections[4]
- PIN io_sram3_connections[5]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 78.240 500.000 78.840 ;
- END
- END io_sram3_connections[5]
- PIN io_sram3_connections[6]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 220.890 0.000 221.170 4.000 ;
- END
- END io_sram3_connections[6]
- PIN io_sram3_connections[7]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 306.040 4.000 306.640 ;
- END
- END io_sram3_connections[7]
- PIN io_sram3_connections[8]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 608.640 500.000 609.240 ;
- END
- END io_sram3_connections[8]
- PIN io_sram3_connections[9]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 158.790 796.000 159.070 800.000 ;
- END
- END io_sram3_connections[9]
- PIN io_sram3_rw_in[0]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 356.590 0.000 356.870 4.000 ;
- END
- END io_sram3_rw_in[0]
- PIN io_sram3_rw_in[10]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 133.490 796.000 133.770 800.000 ;
- END
- END io_sram3_rw_in[10]
- PIN io_sram3_rw_in[11]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 183.640 500.000 184.240 ;
- END
- END io_sram3_rw_in[11]
- PIN io_sram3_rw_in[12]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 540.640 500.000 541.240 ;
- END
- END io_sram3_rw_in[12]
- PIN io_sram3_rw_in[13]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 353.640 4.000 354.240 ;
- END
- END io_sram3_rw_in[13]
- PIN io_sram3_rw_in[14]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 414.840 500.000 415.440 ;
- END
- END io_sram3_rw_in[14]
- PIN io_sram3_rw_in[15]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 112.240 4.000 112.840 ;
- END
- END io_sram3_rw_in[15]
- PIN io_sram3_rw_in[16]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 323.040 500.000 323.640 ;
- END
- END io_sram3_rw_in[16]
- PIN io_sram3_rw_in[17]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 218.590 0.000 218.870 4.000 ;
- END
- END io_sram3_rw_in[17]
- PIN io_sram3_rw_in[18]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 25.390 0.000 25.670 4.000 ;
- END
- END io_sram3_rw_in[18]
- PIN io_sram3_rw_in[19]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 690.240 500.000 690.840 ;
- END
- END io_sram3_rw_in[19]
- PIN io_sram3_rw_in[1]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 448.840 500.000 449.440 ;
- END
- END io_sram3_rw_in[1]
- PIN io_sram3_rw_in[20]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 792.240 4.000 792.840 ;
- END
- END io_sram3_rw_in[20]
- PIN io_sram3_rw_in[21]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 741.240 4.000 741.840 ;
- END
- END io_sram3_rw_in[21]
- PIN io_sram3_rw_in[22]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 303.690 0.000 303.970 4.000 ;
- END
- END io_sram3_rw_in[22]
- PIN io_sram3_rw_in[23]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 357.040 500.000 357.640 ;
- END
- END io_sram3_rw_in[23]
- PIN io_sram3_rw_in[24]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 785.440 500.000 786.040 ;
- END
- END io_sram3_rw_in[24]
- PIN io_sram3_rw_in[25]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 39.190 0.000 39.470 4.000 ;
- END
- END io_sram3_rw_in[25]
- PIN io_sram3_rw_in[26]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 635.840 4.000 636.440 ;
- END
- END io_sram3_rw_in[26]
- PIN io_sram3_rw_in[27]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 124.290 0.000 124.570 4.000 ;
- END
- END io_sram3_rw_in[27]
- PIN io_sram3_rw_in[28]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 338.190 796.000 338.470 800.000 ;
- END
- END io_sram3_rw_in[28]
- PIN io_sram3_rw_in[29]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 94.390 0.000 94.670 4.000 ;
- END
- END io_sram3_rw_in[29]
- PIN io_sram3_rw_in[2]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 625.640 500.000 626.240 ;
- END
- END io_sram3_rw_in[2]
- PIN io_sram3_rw_in[30]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 496.890 796.000 497.170 800.000 ;
- END
- END io_sram3_rw_in[30]
- PIN io_sram3_rw_in[31]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 397.840 4.000 398.440 ;
- END
- END io_sram3_rw_in[31]
- PIN io_sram3_rw_in[3]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 310.590 0.000 310.870 4.000 ;
- END
- END io_sram3_rw_in[3]
- PIN io_sram3_rw_in[4]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 492.290 796.000 492.570 800.000 ;
- END
- END io_sram3_rw_in[4]
- PIN io_sram3_rw_in[5]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 649.440 4.000 650.040 ;
- END
- END io_sram3_rw_in[5]
- PIN io_sram3_rw_in[6]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 464.690 0.000 464.970 4.000 ;
- END
- END io_sram3_rw_in[6]
- PIN io_sram3_rw_in[7]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 418.240 4.000 418.840 ;
- END
- END io_sram3_rw_in[7]
- PIN io_sram3_rw_in[8]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 259.990 796.000 260.270 800.000 ;
- END
- END io_sram3_rw_in[8]
- PIN io_sram3_rw_in[9]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 18.490 796.000 18.770 800.000 ;
- END
- END io_sram3_rw_in[9]
- PIN io_sram4_connections[0]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 135.790 796.000 136.070 800.000 ;
- END
- END io_sram4_connections[0]
- PIN io_sram4_connections[10]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 336.640 500.000 337.240 ;
- END
- END io_sram4_connections[10]
- PIN io_sram4_connections[11]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 765.040 4.000 765.640 ;
- END
- END io_sram4_connections[11]
- PIN io_sram4_connections[12]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 669.840 4.000 670.440 ;
- END
- END io_sram4_connections[12]
- PIN io_sram4_connections[13]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 717.440 500.000 718.040 ;
- END
- END io_sram4_connections[13]
- PIN io_sram4_connections[14]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 61.240 4.000 61.840 ;
- END
- END io_sram4_connections[14]
- PIN io_sram4_connections[15]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 36.890 796.000 37.170 800.000 ;
- END
- END io_sram4_connections[15]
- PIN io_sram4_connections[16]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 34.590 0.000 34.870 4.000 ;
- END
- END io_sram4_connections[16]
- PIN io_sram4_connections[17]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 342.790 0.000 343.070 4.000 ;
- END
- END io_sram4_connections[17]
- PIN io_sram4_connections[18]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 176.840 4.000 177.440 ;
- END
- END io_sram4_connections[18]
- PIN io_sram4_connections[19]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 10.240 4.000 10.840 ;
- END
- END io_sram4_connections[19]
- PIN io_sram4_connections[1]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 329.840 4.000 330.440 ;
- END
- END io_sram4_connections[1]
- PIN io_sram4_connections[20]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 195.590 796.000 195.870 800.000 ;
- END
- END io_sram4_connections[20]
- PIN io_sram4_connections[21]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 629.040 4.000 629.640 ;
- END
- END io_sram4_connections[21]
- PIN io_sram4_connections[22]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 292.190 796.000 292.470 800.000 ;
- END
- END io_sram4_connections[22]
- PIN io_sram4_connections[23]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 435.240 500.000 435.840 ;
- END
- END io_sram4_connections[23]
- PIN io_sram4_connections[24]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 326.690 796.000 326.970 800.000 ;
- END
- END io_sram4_connections[24]
- PIN io_sram4_connections[25]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 455.490 796.000 455.770 800.000 ;
- END
- END io_sram4_connections[25]
- PIN io_sram4_connections[26]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 64.490 0.000 64.770 4.000 ;
- END
- END io_sram4_connections[26]
- PIN io_sram4_connections[27]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 227.840 500.000 228.440 ;
- END
- END io_sram4_connections[27]
- PIN io_sram4_connections[28]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 516.840 4.000 517.440 ;
- END
- END io_sram4_connections[28]
- PIN io_sram4_connections[29]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 358.890 0.000 359.170 4.000 ;
- END
- END io_sram4_connections[29]
- PIN io_sram4_connections[2]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 195.590 0.000 195.870 4.000 ;
- END
- END io_sram4_connections[2]
- PIN io_sram4_connections[30]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 416.390 0.000 416.670 4.000 ;
- END
- END io_sram4_connections[30]
- PIN io_sram4_connections[31]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 154.190 0.000 154.470 4.000 ;
- END
- END io_sram4_connections[31]
- PIN io_sram4_connections[32]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 140.390 796.000 140.670 800.000 ;
- END
- END io_sram4_connections[32]
- PIN io_sram4_connections[33]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 795.640 500.000 796.240 ;
- END
- END io_sram4_connections[33]
- PIN io_sram4_connections[34]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 216.290 0.000 216.570 4.000 ;
- END
- END io_sram4_connections[34]
- PIN io_sram4_connections[35]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 345.090 0.000 345.370 4.000 ;
- END
- END io_sram4_connections[35]
- PIN io_sram4_connections[36]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 174.890 796.000 175.170 800.000 ;
- END
- END io_sram4_connections[36]
- PIN io_sram4_connections[37]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 170.040 4.000 170.640 ;
- END
- END io_sram4_connections[37]
- PIN io_sram4_connections[38]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 363.840 500.000 364.440 ;
- END
- END io_sram4_connections[38]
- PIN io_sram4_connections[39]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 105.440 500.000 106.040 ;
- END
- END io_sram4_connections[39]
- PIN io_sram4_connections[3]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 133.490 0.000 133.770 4.000 ;
- END
- END io_sram4_connections[3]
- PIN io_sram4_connections[40]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 71.390 796.000 71.670 800.000 ;
- END
- END io_sram4_connections[40]
- PIN io_sram4_connections[41]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 319.790 0.000 320.070 4.000 ;
- END
- END io_sram4_connections[41]
- PIN io_sram4_connections[42]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 186.390 796.000 186.670 800.000 ;
- END
- END io_sram4_connections[42]
- PIN io_sram4_connections[43]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 659.640 500.000 660.240 ;
- END
- END io_sram4_connections[43]
- PIN io_sram4_connections[44]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 89.790 796.000 90.070 800.000 ;
- END
- END io_sram4_connections[44]
- PIN io_sram4_connections[45]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 690.240 4.000 690.840 ;
- END
- END io_sram4_connections[45]
- PIN io_sram4_connections[46]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 153.040 4.000 153.640 ;
- END
- END io_sram4_connections[46]
- PIN io_sram4_connections[4]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 493.040 500.000 493.640 ;
- END
- END io_sram4_connections[4]
- PIN io_sram4_connections[5]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 335.890 0.000 336.170 4.000 ;
- END
- END io_sram4_connections[5]
- PIN io_sram4_connections[6]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 425.040 4.000 425.640 ;
- END
- END io_sram4_connections[6]
- PIN io_sram4_connections[7]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 131.190 0.000 131.470 4.000 ;
- END
- END io_sram4_connections[7]
- PIN io_sram4_connections[8]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 17.040 500.000 17.640 ;
- END
- END io_sram4_connections[8]
- PIN io_sram4_connections[9]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 119.040 500.000 119.640 ;
- END
- END io_sram4_connections[9]
- PIN io_sram4_rw_in[0]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 420.990 796.000 421.270 800.000 ;
- END
- END io_sram4_rw_in[0]
- PIN io_sram4_rw_in[10]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 80.590 796.000 80.870 800.000 ;
- END
- END io_sram4_rw_in[10]
- PIN io_sram4_rw_in[11]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 6.840 4.000 7.440 ;
- END
- END io_sram4_rw_in[11]
- PIN io_sram4_rw_in[12]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 126.590 0.000 126.870 4.000 ;
- END
- END io_sram4_rw_in[12]
- PIN io_sram4_rw_in[13]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 386.490 796.000 386.770 800.000 ;
- END
- END io_sram4_rw_in[13]
- PIN io_sram4_rw_in[14]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 680.040 500.000 680.640 ;
- END
- END io_sram4_rw_in[14]
- PIN io_sram4_rw_in[15]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 227.790 796.000 228.070 800.000 ;
- END
- END io_sram4_rw_in[15]
- PIN io_sram4_rw_in[16]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 20.790 0.000 21.070 4.000 ;
- END
- END io_sram4_rw_in[16]
- PIN io_sram4_rw_in[17]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 431.840 4.000 432.440 ;
- END
- END io_sram4_rw_in[17]
- PIN io_sram4_rw_in[18]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 112.790 0.000 113.070 4.000 ;
- END
- END io_sram4_rw_in[18]
- PIN io_sram4_rw_in[19]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 700.440 500.000 701.040 ;
- END
- END io_sram4_rw_in[19]
- PIN io_sram4_rw_in[1]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 236.990 796.000 237.270 800.000 ;
- END
- END io_sram4_rw_in[1]
- PIN io_sram4_rw_in[20]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 428.440 4.000 429.040 ;
- END
- END io_sram4_rw_in[20]
- PIN io_sram4_rw_in[21]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 343.440 500.000 344.040 ;
- END
- END io_sram4_rw_in[21]
- PIN io_sram4_rw_in[22]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 305.990 0.000 306.270 4.000 ;
- END
- END io_sram4_rw_in[22]
- PIN io_sram4_rw_in[23]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 441.690 0.000 441.970 4.000 ;
- END
- END io_sram4_rw_in[23]
- PIN io_sram4_rw_in[24]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 85.190 0.000 85.470 4.000 ;
- END
- END io_sram4_rw_in[24]
- PIN io_sram4_rw_in[25]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 181.790 796.000 182.070 800.000 ;
- END
- END io_sram4_rw_in[25]
- PIN io_sram4_rw_in[26]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 234.640 4.000 235.240 ;
- END
- END io_sram4_rw_in[26]
- PIN io_sram4_rw_in[27]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 601.840 500.000 602.440 ;
- END
- END io_sram4_rw_in[27]
- PIN io_sram4_rw_in[28]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 276.090 796.000 276.370 800.000 ;
- END
- END io_sram4_rw_in[28]
- PIN io_sram4_rw_in[29]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 200.640 500.000 201.240 ;
- END
- END io_sram4_rw_in[29]
- PIN io_sram4_rw_in[2]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 319.640 4.000 320.240 ;
- END
- END io_sram4_rw_in[2]
- PIN io_sram4_rw_in[30]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 248.490 0.000 248.770 4.000 ;
- END
- END io_sram4_rw_in[30]
- PIN io_sram4_rw_in[31]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 464.690 796.000 464.970 800.000 ;
- END
- END io_sram4_rw_in[31]
- PIN io_sram4_rw_in[3]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 374.990 796.000 375.270 800.000 ;
- END
- END io_sram4_rw_in[3]
- PIN io_sram4_rw_in[4]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 349.690 0.000 349.970 4.000 ;
- END
- END io_sram4_rw_in[4]
- PIN io_sram4_rw_in[5]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 289.890 796.000 290.170 800.000 ;
- END
- END io_sram4_rw_in[5]
- PIN io_sram4_rw_in[6]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 197.240 4.000 197.840 ;
- END
- END io_sram4_rw_in[6]
- PIN io_sram4_rw_in[7]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 275.440 500.000 276.040 ;
- END
- END io_sram4_rw_in[7]
- PIN io_sram4_rw_in[8]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 649.440 500.000 650.040 ;
- END
- END io_sram4_rw_in[8]
- PIN io_sram4_rw_in[9]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 561.040 500.000 561.640 ;
- END
- END io_sram4_rw_in[9]
- PIN io_sram5_connections[0]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 88.440 500.000 89.040 ;
- END
- END io_sram5_connections[0]
- PIN io_sram5_connections[10]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 340.490 796.000 340.770 800.000 ;
- END
- END io_sram5_connections[10]
- PIN io_sram5_connections[11]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 142.690 796.000 142.970 800.000 ;
- END
- END io_sram5_connections[11]
- PIN io_sram5_connections[12]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 125.840 4.000 126.440 ;
- END
- END io_sram5_connections[12]
- PIN io_sram5_connections[13]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 397.990 796.000 398.270 800.000 ;
- END
- END io_sram5_connections[13]
- PIN io_sram5_connections[14]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 144.990 796.000 145.270 800.000 ;
- END
- END io_sram5_connections[14]
- PIN io_sram5_connections[15]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 349.690 796.000 349.970 800.000 ;
- END
- END io_sram5_connections[15]
- PIN io_sram5_connections[16]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 720.840 500.000 721.440 ;
- END
- END io_sram5_connections[16]
- PIN io_sram5_connections[17]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 209.390 0.000 209.670 4.000 ;
- END
- END io_sram5_connections[17]
- PIN io_sram5_connections[18]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 71.390 0.000 71.670 4.000 ;
- END
- END io_sram5_connections[18]
- PIN io_sram5_connections[19]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 299.240 500.000 299.840 ;
- END
- END io_sram5_connections[19]
- PIN io_sram5_connections[1]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 302.640 500.000 303.240 ;
- END
- END io_sram5_connections[1]
- PIN io_sram5_connections[20]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 142.690 0.000 142.970 4.000 ;
- END
- END io_sram5_connections[20]
- PIN io_sram5_connections[21]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 312.890 796.000 313.170 800.000 ;
- END
- END io_sram5_connections[21]
- PIN io_sram5_connections[22]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 775.240 4.000 775.840 ;
- END
- END io_sram5_connections[22]
- PIN io_sram5_connections[23]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 632.440 4.000 633.040 ;
- END
- END io_sram5_connections[23]
- PIN io_sram5_connections[24]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 317.490 0.000 317.770 4.000 ;
- END
- END io_sram5_connections[24]
- PIN io_sram5_connections[25]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 744.640 500.000 745.240 ;
- END
- END io_sram5_connections[25]
- PIN io_sram5_connections[26]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 74.840 4.000 75.440 ;
- END
- END io_sram5_connections[26]
- PIN io_sram5_connections[27]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 652.840 500.000 653.440 ;
- END
- END io_sram5_connections[27]
- PIN io_sram5_connections[28]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 119.690 0.000 119.970 4.000 ;
- END
- END io_sram5_connections[28]
- PIN io_sram5_connections[29]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 27.690 0.000 27.970 4.000 ;
- END
- END io_sram5_connections[29]
- PIN io_sram5_connections[2]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 431.840 500.000 432.440 ;
- END
- END io_sram5_connections[2]
- PIN io_sram5_connections[30]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 251.640 500.000 252.240 ;
- END
- END io_sram5_connections[30]
- PIN io_sram5_connections[31]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 363.840 4.000 364.440 ;
- END
- END io_sram5_connections[31]
- PIN io_sram5_connections[32]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 9.290 796.000 9.570 800.000 ;
- END
- END io_sram5_connections[32]
- PIN io_sram5_connections[33]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 71.440 4.000 72.040 ;
- END
- END io_sram5_connections[33]
- PIN io_sram5_connections[34]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 457.790 0.000 458.070 4.000 ;
- END
- END io_sram5_connections[34]
- PIN io_sram5_connections[35]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 166.640 500.000 167.240 ;
- END
- END io_sram5_connections[35]
- PIN io_sram5_connections[36]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 6.840 500.000 7.440 ;
- END
- END io_sram5_connections[36]
- PIN io_sram5_connections[37]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 448.590 796.000 448.870 800.000 ;
- END
- END io_sram5_connections[37]
- PIN io_sram5_connections[38]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 494.590 0.000 494.870 4.000 ;
- END
- END io_sram5_connections[38]
- PIN io_sram5_connections[39]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 268.640 500.000 269.240 ;
- END
- END io_sram5_connections[39]
- PIN io_sram5_connections[3]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 149.590 796.000 149.870 800.000 ;
- END
- END io_sram5_connections[3]
- PIN io_sram5_connections[40]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 595.040 4.000 595.640 ;
- END
- END io_sram5_connections[40]
- PIN io_sram5_connections[41]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 48.390 0.000 48.670 4.000 ;
- END
- END io_sram5_connections[41]
- PIN io_sram5_connections[42]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 102.040 500.000 102.640 ;
- END
- END io_sram5_connections[42]
- PIN io_sram5_connections[43]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 595.040 500.000 595.640 ;
- END
- END io_sram5_connections[43]
- PIN io_sram5_connections[44]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 328.990 796.000 329.270 800.000 ;
- END
- END io_sram5_connections[44]
- PIN io_sram5_connections[45]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 289.040 500.000 289.640 ;
- END
- END io_sram5_connections[45]
- PIN io_sram5_connections[46]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 550.840 500.000 551.440 ;
- END
- END io_sram5_connections[46]
- PIN io_sram5_connections[47]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 95.240 4.000 95.840 ;
- END
- END io_sram5_connections[47]
- PIN io_sram5_connections[48]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 683.440 500.000 684.040 ;
- END
- END io_sram5_connections[48]
- PIN io_sram5_connections[49]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 472.640 4.000 473.240 ;
- END
- END io_sram5_connections[49]
- PIN io_sram5_connections[4]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 407.190 0.000 407.470 4.000 ;
- END
- END io_sram5_connections[4]
- PIN io_sram5_connections[50]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 316.240 500.000 316.840 ;
- END
- END io_sram5_connections[50]
- PIN io_sram5_connections[51]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 367.240 500.000 367.840 ;
- END
- END io_sram5_connections[51]
- PIN io_sram5_connections[52]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 188.690 0.000 188.970 4.000 ;
- END
- END io_sram5_connections[52]
- PIN io_sram5_connections[53]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 27.240 4.000 27.840 ;
- END
- END io_sram5_connections[53]
- PIN io_sram5_connections[54]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 435.240 4.000 435.840 ;
- END
- END io_sram5_connections[54]
- PIN io_sram5_connections[55]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 499.840 500.000 500.440 ;
- END
- END io_sram5_connections[55]
- PIN io_sram5_connections[56]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 400.290 0.000 400.570 4.000 ;
- END
- END io_sram5_connections[56]
- PIN io_sram5_connections[57]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 142.840 500.000 143.440 ;
- END
- END io_sram5_connections[57]
- PIN io_sram5_connections[58]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 353.640 500.000 354.240 ;
- END
- END io_sram5_connections[58]
- PIN io_sram5_connections[59]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 571.240 500.000 571.840 ;
- END
- END io_sram5_connections[59]
- PIN io_sram5_connections[5]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 82.890 0.000 83.170 4.000 ;
- END
- END io_sram5_connections[5]
- PIN io_sram5_connections[60]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 377.440 4.000 378.040 ;
- END
- END io_sram5_connections[60]
- PIN io_sram5_connections[61]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 57.590 796.000 57.870 800.000 ;
- END
- END io_sram5_connections[61]
- PIN io_sram5_connections[62]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 29.990 0.000 30.270 4.000 ;
- END
- END io_sram5_connections[62]
- PIN io_sram5_connections[63]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 149.640 4.000 150.240 ;
- END
- END io_sram5_connections[63]
- PIN io_sram5_connections[64]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 20.440 4.000 21.040 ;
- END
- END io_sram5_connections[64]
- PIN io_sram5_connections[65]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 147.290 0.000 147.570 4.000 ;
- END
- END io_sram5_connections[65]
- PIN io_sram5_connections[66]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 221.040 4.000 221.640 ;
- END
- END io_sram5_connections[66]
- PIN io_sram5_connections[67]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 250.790 796.000 251.070 800.000 ;
- END
- END io_sram5_connections[67]
- PIN io_sram5_connections[68]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 731.040 4.000 731.640 ;
- END
- END io_sram5_connections[68]
- PIN io_sram5_connections[69]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 105.440 4.000 106.040 ;
- END
- END io_sram5_connections[69]
- PIN io_sram5_connections[6]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 443.990 0.000 444.270 4.000 ;
- END
- END io_sram5_connections[6]
- PIN io_sram5_connections[70]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 663.040 4.000 663.640 ;
- END
- END io_sram5_connections[70]
- PIN io_sram5_connections[71]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 244.840 4.000 245.440 ;
- END
- END io_sram5_connections[71]
- PIN io_sram5_connections[72]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 544.040 500.000 544.640 ;
- END
- END io_sram5_connections[72]
- PIN io_sram5_connections[73]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 771.840 4.000 772.440 ;
- END
- END io_sram5_connections[73]
- PIN io_sram5_connections[74]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 384.240 500.000 384.840 ;
- END
- END io_sram5_connections[74]
- PIN io_sram5_connections[75]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 368.090 796.000 368.370 800.000 ;
- END
- END io_sram5_connections[75]
- PIN io_sram5_connections[76]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 285.290 0.000 285.570 4.000 ;
- END
- END io_sram5_connections[76]
- PIN io_sram5_connections[77]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 231.240 4.000 231.840 ;
- END
- END io_sram5_connections[77]
- PIN io_sram5_connections[78]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 476.040 500.000 476.640 ;
- END
- END io_sram5_connections[78]
- PIN io_sram5_connections[79]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 108.190 796.000 108.470 800.000 ;
- END
- END io_sram5_connections[79]
- PIN io_sram5_connections[7]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 377.290 796.000 377.570 800.000 ;
- END
- END io_sram5_connections[7]
- PIN io_sram5_connections[80]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 186.390 0.000 186.670 4.000 ;
- END
- END io_sram5_connections[80]
- PIN io_sram5_connections[81]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 246.190 796.000 246.470 800.000 ;
- END
- END io_sram5_connections[81]
- PIN io_sram5_connections[82]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 282.990 0.000 283.270 4.000 ;
- END
- END io_sram5_connections[82]
- PIN io_sram5_connections[8]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 264.590 0.000 264.870 4.000 ;
- END
- END io_sram5_connections[8]
- PIN io_sram5_connections[9]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 204.790 0.000 205.070 4.000 ;
- END
- END io_sram5_connections[9]
- PIN io_sram5_rw_in[0]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 177.190 0.000 177.470 4.000 ;
- END
- END io_sram5_rw_in[0]
- PIN io_sram5_rw_in[10]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 255.390 796.000 255.670 800.000 ;
- END
- END io_sram5_rw_in[10]
- PIN io_sram5_rw_in[11]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 142.840 4.000 143.440 ;
- END
- END io_sram5_rw_in[11]
- PIN io_sram5_rw_in[12]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 758.240 4.000 758.840 ;
- END
- END io_sram5_rw_in[12]
- PIN io_sram5_rw_in[13]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 584.840 500.000 585.440 ;
- END
- END io_sram5_rw_in[13]
- PIN io_sram5_rw_in[14]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 211.690 796.000 211.970 800.000 ;
- END
- END io_sram5_rw_in[14]
- PIN io_sram5_rw_in[15]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 156.440 4.000 157.040 ;
- END
- END io_sram5_rw_in[15]
- PIN io_sram5_rw_in[16]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 639.240 4.000 639.840 ;
- END
- END io_sram5_rw_in[16]
- PIN io_sram5_rw_in[17]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 119.040 4.000 119.640 ;
- END
- END io_sram5_rw_in[17]
- PIN io_sram5_rw_in[18]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 472.640 500.000 473.240 ;
- END
- END io_sram5_rw_in[18]
- PIN io_sram5_rw_in[19]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 591.640 4.000 592.240 ;
- END
- END io_sram5_rw_in[19]
- PIN io_sram5_rw_in[1]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 43.790 0.000 44.070 4.000 ;
- END
- END io_sram5_rw_in[1]
- PIN io_sram5_rw_in[20]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 462.440 4.000 463.040 ;
- END
- END io_sram5_rw_in[20]
- PIN io_sram5_rw_in[21]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 282.990 796.000 283.270 800.000 ;
- END
- END io_sram5_rw_in[21]
- PIN io_sram5_rw_in[22]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 315.190 796.000 315.470 800.000 ;
- END
- END io_sram5_rw_in[22]
- PIN io_sram5_rw_in[23]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 471.590 0.000 471.870 4.000 ;
- END
- END io_sram5_rw_in[23]
- PIN io_sram5_rw_in[24]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 259.990 0.000 260.270 4.000 ;
- END
- END io_sram5_rw_in[24]
- PIN io_sram5_rw_in[25]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 34.590 796.000 34.870 800.000 ;
- END
- END io_sram5_rw_in[25]
- PIN io_sram5_rw_in[26]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 360.440 4.000 361.040 ;
- END
- END io_sram5_rw_in[26]
- PIN io_sram5_rw_in[27]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 372.690 796.000 372.970 800.000 ;
- END
- END io_sram5_rw_in[27]
- PIN io_sram5_rw_in[28]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 255.040 4.000 255.640 ;
- END
- END io_sram5_rw_in[28]
- PIN io_sram5_rw_in[29]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 478.490 0.000 478.770 4.000 ;
- END
- END io_sram5_rw_in[29]
- PIN io_sram5_rw_in[2]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 700.440 4.000 701.040 ;
- END
- END io_sram5_rw_in[2]
- PIN io_sram5_rw_in[30]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 411.790 0.000 412.070 4.000 ;
- END
- END io_sram5_rw_in[30]
- PIN io_sram5_rw_in[31]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 473.890 0.000 474.170 4.000 ;
- END
- END io_sram5_rw_in[31]
- PIN io_sram5_rw_in[32]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 372.690 0.000 372.970 4.000 ;
- END
- END io_sram5_rw_in[32]
- PIN io_sram5_rw_in[33]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 74.840 500.000 75.440 ;
- END
- END io_sram5_rw_in[33]
- PIN io_sram5_rw_in[34]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 75.990 0.000 76.270 4.000 ;
- END
- END io_sram5_rw_in[34]
- PIN io_sram5_rw_in[35]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 266.890 796.000 267.170 800.000 ;
- END
- END io_sram5_rw_in[35]
- PIN io_sram5_rw_in[36]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 68.040 4.000 68.640 ;
- END
- END io_sram5_rw_in[36]
- PIN io_sram5_rw_in[37]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 452.240 4.000 452.840 ;
- END
- END io_sram5_rw_in[37]
- PIN io_sram5_rw_in[38]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 231.240 500.000 231.840 ;
- END
- END io_sram5_rw_in[38]
- PIN io_sram5_rw_in[39]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 309.440 4.000 310.040 ;
- END
- END io_sram5_rw_in[39]
- PIN io_sram5_rw_in[3]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 466.990 796.000 467.270 800.000 ;
- END
- END io_sram5_rw_in[3]
- PIN io_sram5_rw_in[40]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 476.190 796.000 476.470 800.000 ;
- END
- END io_sram5_rw_in[40]
- PIN io_sram5_rw_in[41]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 251.640 4.000 252.240 ;
- END
- END io_sram5_rw_in[41]
- PIN io_sram5_rw_in[42]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 224.440 500.000 225.040 ;
- END
- END io_sram5_rw_in[42]
- PIN io_sram5_rw_in[43]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 108.840 4.000 109.440 ;
- END
- END io_sram5_rw_in[43]
- PIN io_sram5_rw_in[44]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 149.590 0.000 149.870 4.000 ;
- END
- END io_sram5_rw_in[44]
- PIN io_sram5_rw_in[45]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 530.440 4.000 531.040 ;
- END
- END io_sram5_rw_in[45]
- PIN io_sram5_rw_in[46]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 439.390 0.000 439.670 4.000 ;
- END
- END io_sram5_rw_in[46]
- PIN io_sram5_rw_in[47]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 200.190 796.000 200.470 800.000 ;
- END
- END io_sram5_rw_in[47]
- PIN io_sram5_rw_in[48]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 176.840 500.000 177.440 ;
- END
- END io_sram5_rw_in[48]
- PIN io_sram5_rw_in[49]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 788.840 4.000 789.440 ;
- END
- END io_sram5_rw_in[49]
- PIN io_sram5_rw_in[4]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 248.490 796.000 248.770 800.000 ;
- END
- END io_sram5_rw_in[4]
- PIN io_sram5_rw_in[50]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 78.240 4.000 78.840 ;
- END
- END io_sram5_rw_in[50]
- PIN io_sram5_rw_in[51]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 360.440 500.000 361.040 ;
- END
- END io_sram5_rw_in[51]
- PIN io_sram5_rw_in[52]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 103.590 0.000 103.870 4.000 ;
- END
- END io_sram5_rw_in[52]
- PIN io_sram5_rw_in[53]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 457.790 796.000 458.070 800.000 ;
- END
- END io_sram5_rw_in[53]
- PIN io_sram5_rw_in[54]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 342.790 796.000 343.070 800.000 ;
- END
- END io_sram5_rw_in[54]
- PIN io_sram5_rw_in[55]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 302.640 4.000 303.240 ;
- END
- END io_sram5_rw_in[55]
- PIN io_sram5_rw_in[56]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 253.090 0.000 253.370 4.000 ;
- END
- END io_sram5_rw_in[56]
- PIN io_sram5_rw_in[57]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 66.790 796.000 67.070 800.000 ;
- END
- END io_sram5_rw_in[57]
- PIN io_sram5_rw_in[58]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 401.240 500.000 401.840 ;
- END
- END io_sram5_rw_in[58]
- PIN io_sram5_rw_in[59]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 88.440 4.000 89.040 ;
- END
- END io_sram5_rw_in[59]
- PIN io_sram5_rw_in[5]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 265.240 4.000 265.840 ;
- END
- END io_sram5_rw_in[5]
- PIN io_sram5_rw_in[60]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 57.840 4.000 58.440 ;
- END
- END io_sram5_rw_in[60]
- PIN io_sram5_rw_in[61]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 629.040 500.000 629.640 ;
- END
- END io_sram5_rw_in[61]
- PIN io_sram5_rw_in[62]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 404.890 0.000 405.170 4.000 ;
- END
- END io_sram5_rw_in[62]
- PIN io_sram5_rw_in[63]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 16.190 0.000 16.470 4.000 ;
- END
- END io_sram5_rw_in[63]
- PIN io_sram5_rw_in[6]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 136.040 500.000 136.640 ;
- END
- END io_sram5_rw_in[6]
- PIN io_sram5_rw_in[7]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 179.490 0.000 179.770 4.000 ;
- END
- END io_sram5_rw_in[7]
- PIN io_sram5_rw_in[8]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 23.840 500.000 24.440 ;
- END
- END io_sram5_rw_in[8]
- PIN io_sram5_rw_in[9]
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 296.790 796.000 297.070 800.000 ;
- END
- END io_sram5_rw_in[9]
- PIN io_sram_data[0]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 516.840 500.000 517.440 ;
- END
- END io_sram_data[0]
- PIN io_sram_data[10]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 287.590 796.000 287.870 800.000 ;
- END
- END io_sram_data[10]
- PIN io_sram_data[11]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 448.590 0.000 448.870 4.000 ;
- END
- END io_sram_data[11]
- PIN io_sram_data[12]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 202.490 796.000 202.770 800.000 ;
- END
- END io_sram_data[12]
- PIN io_sram_data[13]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 442.040 500.000 442.640 ;
- END
- END io_sram_data[13]
- PIN io_sram_data[14]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 703.840 500.000 704.440 ;
- END
- END io_sram_data[14]
- PIN io_sram_data[15]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 91.840 500.000 92.440 ;
- END
- END io_sram_data[15]
- PIN io_sram_data[16]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 248.240 4.000 248.840 ;
- END
- END io_sram_data[16]
- PIN io_sram_data[17]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 50.690 796.000 50.970 800.000 ;
- END
- END io_sram_data[17]
- PIN io_sram_data[18]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 85.040 500.000 85.640 ;
- END
- END io_sram_data[18]
- PIN io_sram_data[19]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 238.040 500.000 238.640 ;
- END
- END io_sram_data[19]
- PIN io_sram_data[1]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 439.390 796.000 439.670 800.000 ;
- END
- END io_sram_data[1]
- PIN io_sram_data[20]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 17.040 4.000 17.640 ;
- END
- END io_sram_data[20]
- PIN io_sram_data[21]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 234.690 796.000 234.970 800.000 ;
- END
- END io_sram_data[21]
- PIN io_sram_data[22]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 448.840 4.000 449.440 ;
- END
- END io_sram_data[22]
- PIN io_sram_data[23]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 82.890 796.000 83.170 800.000 ;
- END
- END io_sram_data[23]
- PIN io_sram_data[24]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 496.440 500.000 497.040 ;
- END
- END io_sram_data[24]
- PIN io_sram_data[25]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 462.390 796.000 462.670 800.000 ;
- END
- END io_sram_data[25]
- PIN io_sram_data[26]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 23.090 796.000 23.370 800.000 ;
- END
- END io_sram_data[26]
- PIN io_sram_data[27]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 564.440 500.000 565.040 ;
- END
- END io_sram_data[27]
- PIN io_sram_data[28]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 333.240 4.000 333.840 ;
- END
- END io_sram_data[28]
- PIN io_sram_data[29]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 68.040 500.000 68.640 ;
- END
- END io_sram_data[29]
- PIN io_sram_data[2]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 506.640 4.000 507.240 ;
- END
- END io_sram_data[2]
- PIN io_sram_data[30]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 646.040 500.000 646.640 ;
- END
- END io_sram_data[30]
- PIN io_sram_data[31]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 574.640 4.000 575.240 ;
- END
- END io_sram_data[31]
- PIN io_sram_data[32]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 223.190 796.000 223.470 800.000 ;
- END
- END io_sram_data[32]
- PIN io_sram_data[33]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 527.040 4.000 527.640 ;
- END
- END io_sram_data[33]
- PIN io_sram_data[34]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 598.440 4.000 599.040 ;
- END
- END io_sram_data[34]
- PIN io_sram_data[35]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 273.790 0.000 274.070 4.000 ;
- END
- END io_sram_data[35]
- PIN io_sram_data[36]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 180.240 500.000 180.840 ;
- END
- END io_sram_data[36]
- PIN io_sram_data[37]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 210.840 500.000 211.440 ;
- END
- END io_sram_data[37]
- PIN io_sram_data[38]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 605.240 500.000 605.840 ;
- END
- END io_sram_data[38]
- PIN io_sram_data[39]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 459.040 4.000 459.640 ;
- END
- END io_sram_data[39]
- PIN io_sram_data[3]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 411.440 500.000 412.040 ;
- END
- END io_sram_data[3]
- PIN io_sram_data[40]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 258.440 500.000 259.040 ;
- END
- END io_sram_data[40]
- PIN io_sram_data[41]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 707.240 4.000 707.840 ;
- END
- END io_sram_data[41]
- PIN io_sram_data[42]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 581.440 500.000 582.040 ;
- END
- END io_sram_data[42]
- PIN io_sram_data[43]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 221.040 500.000 221.640 ;
- END
- END io_sram_data[43]
- PIN io_sram_data[44]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 179.490 796.000 179.770 800.000 ;
- END
- END io_sram_data[44]
- PIN io_sram_data[45]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 486.240 4.000 486.840 ;
- END
- END io_sram_data[45]
- PIN io_sram_data[46]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 354.290 796.000 354.570 800.000 ;
- END
- END io_sram_data[46]
- PIN io_sram_data[47]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 432.490 0.000 432.770 4.000 ;
- END
- END io_sram_data[47]
- PIN io_sram_data[48]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 707.240 500.000 707.840 ;
- END
- END io_sram_data[48]
- PIN io_sram_data[49]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 326.440 4.000 327.040 ;
- END
- END io_sram_data[49]
- PIN io_sram_data[4]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 246.190 0.000 246.470 4.000 ;
- END
- END io_sram_data[4]
- PIN io_sram_data[50]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 680.040 4.000 680.640 ;
- END
- END io_sram_data[50]
- PIN io_sram_data[51]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 724.240 500.000 724.840 ;
- END
- END io_sram_data[51]
- PIN io_sram_data[52]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 269.190 0.000 269.470 4.000 ;
- END
- END io_sram_data[52]
- PIN io_sram_data[53]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 207.090 0.000 207.370 4.000 ;
- END
- END io_sram_data[53]
- PIN io_sram_data[54]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 66.790 0.000 67.070 4.000 ;
- END
- END io_sram_data[54]
- PIN io_sram_data[55]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 537.240 500.000 537.840 ;
- END
- END io_sram_data[55]
- PIN io_sram_data[56]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 0.000 778.640 4.000 779.240 ;
- END
- END io_sram_data[56]
- PIN io_sram_data[57]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met3 ;
- RECT 496.000 255.040 500.000 255.640 ;
- END
- END io_sram_data[57]
- PIN io_sram_data[58]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 250.790 0.000 251.070 4.000 ;
- END
- END io_sram_data[58]
- PIN io_sram_data[59]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 269.190 796.000 269.470 800.000 ;
- END
- END io_sram_data[59]
- PIN io_sram_data[5]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 23.090 0.000 23.370 4.000 ;
- END
- END io_sram_data[5]
- PIN io_sram_data[60]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 167.990 796.000 168.270 800.000 ;
- END
- END io_sram_data[60]
- PIN io_sram_data[61]
- DIRECTION OUTPUT TRISTATE ;
- USE SIGNAL ;
- PORT
- LAYER met2 ;
- RECT 52.990 0.000 53.270 4.000 ;
- END
- END io_sram_data[61]
- PIN io_sram_data[62]
+ END gpio_clk
+ PIN gpio_data
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 0.000 163.240 4.000 163.840 ;
END
- END io_sram_data[62]
- PIN io_sram_data[63]
+ END gpio_data
+ PIN gpio_packet
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 469.290 796.000 469.570 800.000 ;
+ END
+ END gpio_packet
+ PIN in_select
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 272.040 4.000 272.640 ;
+ END
+ END in_select
+ PIN la_clk
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 397.840 500.000 398.440 ;
+ END
+ END la_clk
+ PIN la_data[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 443.990 0.000 444.270 4.000 ;
+ END
+ END la_data[0]
+ PIN la_data[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 299.090 796.000 299.370 800.000 ;
+ END
+ END la_data[10]
+ PIN la_data[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 98.990 0.000 99.270 4.000 ;
+ END
+ END la_data[11]
+ PIN la_data[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 338.190 0.000 338.470 4.000 ;
+ END
+ END la_data[12]
+ PIN la_data[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 66.790 796.000 67.070 800.000 ;
+ END
+ END la_data[13]
+ PIN la_data[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 173.440 500.000 174.040 ;
+ END
+ END la_data[14]
+ PIN la_data[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 391.040 4.000 391.640 ;
+ END
+ END la_data[15]
+ PIN la_data[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 476.190 796.000 476.470 800.000 ;
+ END
+ END la_data[16]
+ PIN la_data[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 140.390 0.000 140.670 4.000 ;
+ END
+ END la_data[17]
+ PIN la_data[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 391.090 0.000 391.370 4.000 ;
+ END
+ END la_data[18]
+ PIN la_data[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 758.240 500.000 758.840 ;
+ END
+ END la_data[19]
+ PIN la_data[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 416.390 0.000 416.670 4.000 ;
+ END
+ END la_data[1]
+ PIN la_data[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 441.690 796.000 441.970 800.000 ;
+ END
+ END la_data[20]
+ PIN la_data[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 748.040 500.000 748.640 ;
+ END
+ END la_data[21]
+ PIN la_data[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 744.640 4.000 745.240 ;
+ END
+ END la_data[22]
+ PIN la_data[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 329.840 500.000 330.440 ;
+ END
+ END la_data[23]
+ PIN la_data[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2.390 796.000 2.670 800.000 ;
+ END
+ END la_data[24]
+ PIN la_data[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 469.240 500.000 469.840 ;
+ END
+ END la_data[25]
+ PIN la_data[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 257.690 0.000 257.970 4.000 ;
+ END
+ END la_data[26]
+ PIN la_data[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 669.840 4.000 670.440 ;
+ END
+ END la_data[27]
+ PIN la_data[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 482.840 500.000 483.440 ;
+ END
+ END la_data[28]
+ PIN la_data[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 418.240 4.000 418.840 ;
+ END
+ END la_data[29]
+ PIN la_data[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 438.640 4.000 439.240 ;
+ END
+ END la_data[2]
+ PIN la_data[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 496.440 500.000 497.040 ;
+ END
+ END la_data[30]
+ PIN la_data[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 450.890 0.000 451.170 4.000 ;
+ END
+ END la_data[31]
+ PIN la_data[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 751.440 4.000 752.040 ;
+ END
+ END la_data[32]
+ PIN la_data[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 554.240 500.000 554.840 ;
+ END
+ END la_data[33]
+ PIN la_data[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 471.590 0.000 471.870 4.000 ;
+ END
+ END la_data[34]
+ PIN la_data[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 381.890 796.000 382.170 800.000 ;
+ END
+ END la_data[35]
+ PIN la_data[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 167.990 796.000 168.270 800.000 ;
+ END
+ END la_data[36]
+ PIN la_data[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 131.190 796.000 131.470 800.000 ;
+ END
+ END la_data[37]
+ PIN la_data[38]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 71.390 796.000 71.670 800.000 ;
+ END
+ END la_data[38]
+ PIN la_data[39]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 299.240 500.000 299.840 ;
+ END
+ END la_data[39]
+ PIN la_data[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 165.690 0.000 165.970 4.000 ;
+ END
+ END la_data[3]
+ PIN la_data[40]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 10.240 500.000 10.840 ;
+ END
+ END la_data[40]
+ PIN la_data[41]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 335.890 796.000 336.170 800.000 ;
+ END
+ END la_data[41]
+ PIN la_data[42]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 368.090 0.000 368.370 4.000 ;
+ END
+ END la_data[42]
+ PIN la_data[43]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 487.690 796.000 487.970 800.000 ;
+ END
+ END la_data[43]
+ PIN la_data[44]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 788.840 500.000 789.440 ;
+ END
+ END la_data[44]
+ PIN la_data[45]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 319.640 500.000 320.240 ;
+ END
+ END la_data[45]
+ PIN la_data[46]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 466.990 0.000 467.270 4.000 ;
+ END
+ END la_data[46]
+ PIN la_data[47]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 496.000 44.240 500.000 44.840 ;
END
- END io_sram_data[63]
- PIN io_sram_data[6]
+ END la_data[47]
+ PIN la_data[48]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 133.490 0.000 133.770 4.000 ;
+ END
+ END la_data[48]
+ PIN la_data[49]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 324.390 796.000 324.670 800.000 ;
+ END
+ END la_data[49]
+ PIN la_data[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 761.640 4.000 762.240 ;
+ END
+ END la_data[4]
+ PIN la_data[50]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 605.240 4.000 605.840 ;
+ END
+ END la_data[50]
+ PIN la_data[51]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 272.040 500.000 272.640 ;
+ END
+ END la_data[51]
+ PIN la_data[52]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 754.840 500.000 755.440 ;
+ END
+ END la_data[52]
+ PIN la_data[53]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 301.390 0.000 301.670 4.000 ;
+ END
+ END la_data[53]
+ PIN la_data[54]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 234.690 796.000 234.970 800.000 ;
+ END
+ END la_data[54]
+ PIN la_data[55]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 567.840 500.000 568.440 ;
+ END
+ END la_data[55]
+ PIN la_data[56]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 377.440 500.000 378.040 ;
+ END
+ END la_data[56]
+ PIN la_data[57]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 278.840 500.000 279.440 ;
+ END
+ END la_data[57]
+ PIN la_data[58]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 259.990 796.000 260.270 800.000 ;
+ END
+ END la_data[58]
+ PIN la_data[59]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 499.840 4.000 500.440 ;
+ END
+ END la_data[59]
+ PIN la_data[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 400.290 796.000 400.570 800.000 ;
+ END
+ END la_data[5]
+ PIN la_data[60]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 170.040 4.000 170.640 ;
+ END
+ END la_data[60]
+ PIN la_data[61]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 319.790 0.000 320.070 4.000 ;
+ END
+ END la_data[61]
+ PIN la_data[62]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 105.440 4.000 106.040 ;
+ END
+ END la_data[62]
+ PIN la_data[63]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 85.190 0.000 85.470 4.000 ;
+ END
+ END la_data[63]
+ PIN la_data[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 255.040 500.000 255.640 ;
+ END
+ END la_data[6]
+ PIN la_data[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 622.240 4.000 622.840 ;
+ END
+ END la_data[7]
+ PIN la_data[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 336.640 4.000 337.240 ;
+ END
+ END la_data[8]
+ PIN la_data[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 302.640 4.000 303.240 ;
+ END
+ END la_data[9]
+ PIN la_packet[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 248.240 500.000 248.840 ;
+ END
+ END la_packet[0]
+ PIN la_packet[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 95.240 4.000 95.840 ;
+ END
+ END la_packet[10]
+ PIN la_packet[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 361.190 796.000 361.470 800.000 ;
+ END
+ END la_packet[11]
+ PIN la_packet[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 459.040 500.000 459.640 ;
+ END
+ END la_packet[12]
+ PIN la_packet[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 317.490 0.000 317.770 4.000 ;
+ END
+ END la_packet[13]
+ PIN la_packet[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 81.640 500.000 82.240 ;
+ END
+ END la_packet[14]
+ PIN la_packet[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 574.640 500.000 575.240 ;
+ END
+ END la_packet[15]
+ PIN la_packet[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 462.390 0.000 462.670 4.000 ;
+ END
+ END la_packet[16]
+ PIN la_packet[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 187.040 500.000 187.640 ;
+ END
+ END la_packet[17]
+ PIN la_packet[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 365.790 0.000 366.070 4.000 ;
+ END
+ END la_packet[18]
+ PIN la_packet[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 306.040 500.000 306.640 ;
+ END
+ END la_packet[19]
+ PIN la_packet[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 483.090 796.000 483.370 800.000 ;
+ END
+ END la_packet[1]
+ PIN la_packet[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 434.790 0.000 435.070 4.000 ;
+ END
+ END la_packet[20]
+ PIN la_packet[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 234.640 4.000 235.240 ;
+ END
+ END la_packet[21]
+ PIN la_packet[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 88.440 500.000 89.040 ;
+ END
+ END la_packet[22]
+ PIN la_packet[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 174.890 796.000 175.170 800.000 ;
+ END
+ END la_packet[23]
+ PIN la_packet[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 183.640 4.000 184.240 ;
+ END
+ END la_packet[24]
+ PIN la_packet[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 13.890 0.000 14.170 4.000 ;
+ END
+ END la_packet[25]
+ PIN la_packet[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 296.790 796.000 297.070 800.000 ;
+ END
+ END la_packet[26]
+ PIN la_packet[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 690.240 4.000 690.840 ;
+ END
+ END la_packet[27]
+ PIN la_packet[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 13.890 796.000 14.170 800.000 ;
+ END
+ END la_packet[28]
+ PIN la_packet[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 112.790 796.000 113.070 800.000 ;
+ END
+ END la_packet[29]
+ PIN la_packet[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 302.640 500.000 303.240 ;
+ END
+ END la_packet[2]
+ PIN la_packet[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 285.640 4.000 286.240 ;
+ END
+ END la_packet[30]
+ PIN la_packet[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 204.040 500.000 204.640 ;
+ END
+ END la_packet[31]
+ PIN la_packet[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 494.590 0.000 494.870 4.000 ;
+ END
+ END la_packet[32]
+ PIN la_packet[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 149.590 0.000 149.870 4.000 ;
+ END
+ END la_packet[33]
+ PIN la_packet[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 632.440 500.000 633.040 ;
+ END
+ END la_packet[34]
+ PIN la_packet[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 482.840 4.000 483.440 ;
+ END
+ END la_packet[35]
+ PIN la_packet[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 268.640 4.000 269.240 ;
+ END
+ END la_packet[36]
+ PIN la_packet[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 479.440 4.000 480.040 ;
+ END
+ END la_packet[37]
+ PIN la_packet[38]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 20.440 500.000 21.040 ;
+ END
+ END la_packet[38]
+ PIN la_packet[39]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 216.290 796.000 216.570 800.000 ;
+ END
+ END la_packet[39]
+ PIN la_packet[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 489.640 4.000 490.240 ;
+ END
+ END la_packet[3]
+ PIN la_packet[40]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 163.390 796.000 163.670 800.000 ;
+ END
+ END la_packet[40]
+ PIN la_packet[41]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 423.290 796.000 423.570 800.000 ;
+ END
+ END la_packet[41]
+ PIN la_packet[42]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 17.040 500.000 17.640 ;
+ END
+ END la_packet[42]
+ PIN la_packet[43]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 174.890 0.000 175.170 4.000 ;
+ END
+ END la_packet[43]
+ PIN la_packet[44]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 299.090 0.000 299.370 4.000 ;
+ END
+ END la_packet[44]
+ PIN la_packet[45]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 547.440 500.000 548.040 ;
+ END
+ END la_packet[45]
+ PIN la_packet[46]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 292.190 0.000 292.470 4.000 ;
+ END
+ END la_packet[46]
+ PIN la_packet[47]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 595.040 500.000 595.640 ;
+ END
+ END la_packet[47]
+ PIN la_packet[48]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 527.040 4.000 527.640 ;
+ END
+ END la_packet[48]
+ PIN la_packet[49]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 486.240 500.000 486.840 ;
+ END
+ END la_packet[49]
+ PIN la_packet[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 223.190 796.000 223.470 800.000 ;
+ END
+ END la_packet[4]
+ PIN la_packet[50]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 217.640 4.000 218.240 ;
+ END
+ END la_packet[50]
+ PIN la_packet[51]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 4.690 0.000 4.970 4.000 ;
+ END
+ END la_packet[51]
+ PIN la_packet[52]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 149.590 796.000 149.870 800.000 ;
+ END
+ END la_packet[52]
+ PIN la_packet[53]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 172.590 0.000 172.870 4.000 ;
+ END
+ END la_packet[53]
+ PIN la_packet[54]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 200.640 4.000 201.240 ;
+ END
+ END la_packet[54]
+ PIN la_packet[55]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 476.190 0.000 476.470 4.000 ;
+ END
+ END la_packet[55]
+ PIN la_packet[56]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 166.640 500.000 167.240 ;
+ END
+ END la_packet[56]
+ PIN la_packet[57]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 75.990 0.000 76.270 4.000 ;
+ END
+ END la_packet[57]
+ PIN la_packet[58]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 329.840 4.000 330.440 ;
+ END
+ END la_packet[58]
+ PIN la_packet[59]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 785.440 500.000 786.040 ;
+ END
+ END la_packet[59]
+ PIN la_packet[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 455.640 4.000 456.240 ;
+ END
+ END la_packet[5]
+ PIN la_packet[60]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 176.840 500.000 177.440 ;
+ END
+ END la_packet[60]
+ PIN la_packet[61]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 232.390 796.000 232.670 800.000 ;
+ END
+ END la_packet[61]
+ PIN la_packet[62]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 236.990 796.000 237.270 800.000 ;
+ END
+ END la_packet[62]
+ PIN la_packet[63]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 455.490 796.000 455.770 800.000 ;
+ END
+ END la_packet[63]
+ PIN la_packet[64]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 693.640 4.000 694.240 ;
+ END
+ END la_packet[64]
+ PIN la_packet[65]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 166.640 4.000 167.240 ;
+ END
+ END la_packet[65]
+ PIN la_packet[66]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 204.790 796.000 205.070 800.000 ;
+ END
+ END la_packet[66]
+ PIN la_packet[67]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 361.190 0.000 361.470 4.000 ;
+ END
+ END la_packet[67]
+ PIN la_packet[68]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 227.840 500.000 228.440 ;
+ END
+ END la_packet[68]
+ PIN la_packet[69]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 227.790 796.000 228.070 800.000 ;
+ END
+ END la_packet[69]
+ PIN la_packet[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 724.240 500.000 724.840 ;
+ END
+ END la_packet[6]
+ PIN la_packet[70]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 167.990 0.000 168.270 4.000 ;
+ END
+ END la_packet[70]
+ PIN la_packet[71]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 567.840 4.000 568.440 ;
+ END
+ END la_packet[71]
+ PIN la_packet[72]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 48.390 796.000 48.670 800.000 ;
+ END
+ END la_packet[72]
+ PIN la_packet[73]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 439.390 0.000 439.670 4.000 ;
+ END
+ END la_packet[73]
+ PIN la_packet[74]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 295.840 4.000 296.440 ;
+ END
+ END la_packet[74]
+ PIN la_packet[75]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 59.890 796.000 60.170 800.000 ;
+ END
+ END la_packet[75]
+ PIN la_packet[76]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 43.790 796.000 44.070 800.000 ;
+ END
+ END la_packet[76]
+ PIN la_packet[77]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 133.490 796.000 133.770 800.000 ;
+ END
+ END la_packet[77]
+ PIN la_packet[78]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 703.840 4.000 704.440 ;
+ END
+ END la_packet[78]
+ PIN la_packet[79]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 316.240 4.000 316.840 ;
+ END
+ END la_packet[79]
+ PIN la_packet[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 40.840 4.000 41.440 ;
+ END
+ END la_packet[7]
+ PIN la_packet[80]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 241.440 500.000 242.040 ;
+ END
+ END la_packet[80]
+ PIN la_packet[81]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 41.490 796.000 41.770 800.000 ;
+ END
+ END la_packet[81]
+ PIN la_packet[82]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 683.440 4.000 684.040 ;
+ END
+ END la_packet[82]
+ PIN la_packet[83]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 401.240 4.000 401.840 ;
+ END
+ END la_packet[83]
+ PIN la_packet[84]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 227.840 4.000 228.440 ;
+ END
+ END la_packet[84]
+ PIN la_packet[85]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2.390 0.000 2.670 4.000 ;
+ END
+ END la_packet[85]
+ PIN la_packet[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 588.240 4.000 588.840 ;
+ END
+ END la_packet[8]
+ PIN la_packet[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 62.190 0.000 62.470 4.000 ;
+ END
+ END la_packet[9]
+ PIN reset
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 788.840 4.000 789.440 ;
+ END
+ END reset
+ PIN sram0_connections[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 360.440 4.000 361.040 ;
+ END
+ END sram0_connections[0]
+ PIN sram0_connections[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 629.040 4.000 629.640 ;
+ END
+ END sram0_connections[10]
+ PIN sram0_connections[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 64.640 500.000 65.240 ;
+ END
+ END sram0_connections[11]
+ PIN sram0_connections[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 119.040 500.000 119.640 ;
+ END
+ END sram0_connections[12]
+ PIN sram0_connections[13]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 427.890 796.000 428.170 800.000 ;
END
- END io_sram_data[6]
- PIN io_sram_data[7]
+ END sram0_connections[13]
+ PIN sram0_connections[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 404.890 0.000 405.170 4.000 ;
+ END
+ END sram0_connections[14]
+ PIN sram0_connections[15]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
- RECT 496.000 693.640 500.000 694.240 ;
+ RECT 496.000 207.440 500.000 208.040 ;
END
- END io_sram_data[7]
- PIN io_sram_data[8]
+ END sram0_connections[15]
+ PIN sram0_connections[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 333.240 4.000 333.840 ;
+ END
+ END sram0_connections[16]
+ PIN sram0_connections[17]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
- RECT 163.390 796.000 163.670 800.000 ;
+ RECT 11.590 796.000 11.870 800.000 ;
END
- END io_sram_data[8]
- PIN io_sram_data[9]
+ END sram0_connections[17]
+ PIN sram0_connections[18]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
- RECT 96.690 0.000 96.970 4.000 ;
+ RECT 289.890 0.000 290.170 4.000 ;
END
- END io_sram_data[9]
- PIN reset
+ END sram0_connections[18]
+ PIN sram0_connections[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 734.440 4.000 735.040 ;
+ END
+ END sram0_connections[19]
+ PIN sram0_connections[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 384.190 0.000 384.470 4.000 ;
+ END
+ END sram0_connections[1]
+ PIN sram0_connections[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 180.240 4.000 180.840 ;
+ END
+ END sram0_connections[20]
+ PIN sram0_connections[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 326.440 4.000 327.040 ;
+ END
+ END sram0_connections[21]
+ PIN sram0_connections[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 669.840 500.000 670.440 ;
+ END
+ END sram0_connections[22]
+ PIN sram0_connections[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 98.640 4.000 99.240 ;
+ END
+ END sram0_connections[23]
+ PIN sram0_connections[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 598.440 4.000 599.040 ;
+ END
+ END sram0_connections[24]
+ PIN sram0_connections[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 250.790 796.000 251.070 800.000 ;
+ END
+ END sram0_connections[25]
+ PIN sram0_connections[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 68.040 4.000 68.640 ;
+ END
+ END sram0_connections[26]
+ PIN sram0_connections[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 771.840 4.000 772.440 ;
+ END
+ END sram0_connections[27]
+ PIN sram0_connections[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 213.990 0.000 214.270 4.000 ;
+ END
+ END sram0_connections[28]
+ PIN sram0_connections[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 411.790 796.000 412.070 800.000 ;
+ END
+ END sram0_connections[29]
+ PIN sram0_connections[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 197.890 796.000 198.170 800.000 ;
+ END
+ END sram0_connections[2]
+ PIN sram0_connections[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 128.890 796.000 129.170 800.000 ;
+ END
+ END sram0_connections[30]
+ PIN sram0_connections[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 193.290 0.000 193.570 4.000 ;
+ END
+ END sram0_connections[31]
+ PIN sram0_connections[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 380.840 500.000 381.440 ;
+ END
+ END sram0_connections[32]
+ PIN sram0_connections[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 305.990 0.000 306.270 4.000 ;
+ END
+ END sram0_connections[33]
+ PIN sram0_connections[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 112.240 4.000 112.840 ;
+ END
+ END sram0_connections[34]
+ PIN sram0_connections[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 333.590 0.000 333.870 4.000 ;
+ END
+ END sram0_connections[35]
+ PIN sram0_connections[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 68.040 500.000 68.640 ;
+ END
+ END sram0_connections[36]
+ PIN sram0_connections[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 262.290 796.000 262.570 800.000 ;
+ END
+ END sram0_connections[37]
+ PIN sram0_connections[38]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 537.240 500.000 537.840 ;
+ END
+ END sram0_connections[38]
+ PIN sram0_connections[39]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 537.240 4.000 537.840 ;
+ END
+ END sram0_connections[39]
+ PIN sram0_connections[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 377.290 0.000 377.570 4.000 ;
+ END
+ END sram0_connections[3]
+ PIN sram0_connections[40]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 190.440 4.000 191.040 ;
+ END
+ END sram0_connections[40]
+ PIN sram0_connections[41]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 448.590 0.000 448.870 4.000 ;
+ END
+ END sram0_connections[41]
+ PIN sram0_connections[42]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 432.490 796.000 432.770 800.000 ;
+ END
+ END sram0_connections[42]
+ PIN sram0_connections[43]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 460.090 796.000 460.370 800.000 ;
+ END
+ END sram0_connections[43]
+ PIN sram0_connections[44]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 322.090 796.000 322.370 800.000 ;
+ END
+ END sram0_connections[44]
+ PIN sram0_connections[45]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 457.790 796.000 458.070 800.000 ;
+ END
+ END sram0_connections[45]
+ PIN sram0_connections[46]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 119.040 4.000 119.640 ;
+ END
+ END sram0_connections[46]
+ PIN sram0_connections[47]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 395.690 0.000 395.970 4.000 ;
+ END
+ END sram0_connections[47]
+ PIN sram0_connections[48]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 246.190 0.000 246.470 4.000 ;
+ END
+ END sram0_connections[48]
+ PIN sram0_connections[49]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 639.240 4.000 639.840 ;
+ END
+ END sram0_connections[49]
+ PIN sram0_connections[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 20.440 4.000 21.040 ;
+ END
+ END sram0_connections[4]
+ PIN sram0_connections[50]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 231.240 4.000 231.840 ;
+ END
+ END sram0_connections[50]
+ PIN sram0_connections[51]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 37.440 4.000 38.040 ;
+ END
+ END sram0_connections[51]
+ PIN sram0_connections[52]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 347.390 796.000 347.670 800.000 ;
+ END
+ END sram0_connections[52]
+ PIN sram0_connections[53]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 700.440 500.000 701.040 ;
+ END
+ END sram0_connections[53]
+ PIN sram0_connections[54]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 9.290 796.000 9.570 800.000 ;
+ END
+ END sram0_connections[54]
+ PIN sram0_connections[55]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 727.640 4.000 728.240 ;
+ END
+ END sram0_connections[55]
+ PIN sram0_connections[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 435.240 500.000 435.840 ;
+ END
+ END sram0_connections[5]
+ PIN sram0_connections[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 659.640 500.000 660.240 ;
+ END
+ END sram0_connections[6]
+ PIN sram0_connections[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 448.590 796.000 448.870 800.000 ;
+ END
+ END sram0_connections[7]
+ PIN sram0_connections[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 496.440 4.000 497.040 ;
+ END
+ END sram0_connections[8]
+ PIN sram0_connections[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 312.890 796.000 313.170 800.000 ;
+ END
+ END sram0_connections[9]
+ PIN sram0_ro_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 431.840 500.000 432.440 ;
+ END
+ END sram0_ro_in[0]
+ PIN sram0_ro_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 469.240 4.000 469.840 ;
+ END
+ END sram0_ro_in[10]
+ PIN sram0_ro_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 731.040 4.000 731.640 ;
+ END
+ END sram0_ro_in[11]
+ PIN sram0_ro_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 489.990 796.000 490.270 800.000 ;
+ END
+ END sram0_ro_in[12]
+ PIN sram0_ro_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 39.190 0.000 39.470 4.000 ;
+ END
+ END sram0_ro_in[13]
+ PIN sram0_ro_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 23.840 4.000 24.440 ;
+ END
+ END sram0_ro_in[14]
+ PIN sram0_ro_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 135.790 796.000 136.070 800.000 ;
+ END
+ END sram0_ro_in[15]
+ PIN sram0_ro_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 404.890 796.000 405.170 800.000 ;
+ END
+ END sram0_ro_in[16]
+ PIN sram0_ro_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 465.840 4.000 466.440 ;
+ END
+ END sram0_ro_in[17]
+ PIN sram0_ro_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 414.840 4.000 415.440 ;
+ END
+ END sram0_ro_in[18]
+ PIN sram0_ro_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 80.590 796.000 80.870 800.000 ;
+ END
+ END sram0_ro_in[19]
+ PIN sram0_ro_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 411.440 4.000 412.040 ;
+ END
+ END sram0_ro_in[1]
+ PIN sram0_ro_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 423.290 0.000 423.570 4.000 ;
+ END
+ END sram0_ro_in[20]
+ PIN sram0_ro_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 350.240 4.000 350.840 ;
+ END
+ END sram0_ro_in[21]
+ PIN sram0_ro_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 588.240 500.000 588.840 ;
+ END
+ END sram0_ro_in[22]
+ PIN sram0_ro_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 177.190 0.000 177.470 4.000 ;
+ END
+ END sram0_ro_in[23]
+ PIN sram0_ro_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 601.840 500.000 602.440 ;
+ END
+ END sram0_ro_in[24]
+ PIN sram0_ro_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 119.690 0.000 119.970 4.000 ;
+ END
+ END sram0_ro_in[25]
+ PIN sram0_ro_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 407.190 796.000 407.470 800.000 ;
+ END
+ END sram0_ro_in[26]
+ PIN sram0_ro_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 450.890 796.000 451.170 800.000 ;
+ END
+ END sram0_ro_in[27]
+ PIN sram0_ro_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 503.240 500.000 503.840 ;
+ END
+ END sram0_ro_in[28]
+ PIN sram0_ro_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 601.840 4.000 602.440 ;
+ END
+ END sram0_ro_in[29]
+ PIN sram0_ro_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 151.890 0.000 152.170 4.000 ;
+ END
+ END sram0_ro_in[2]
+ PIN sram0_ro_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 564.440 4.000 565.040 ;
+ END
+ END sram0_ro_in[30]
+ PIN sram0_ro_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 294.490 796.000 294.770 800.000 ;
+ END
+ END sram0_ro_in[31]
+ PIN sram0_ro_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 441.690 0.000 441.970 4.000 ;
+ END
+ END sram0_ro_in[3]
+ PIN sram0_ro_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 496.000 408.040 500.000 408.640 ;
END
- END reset
+ END sram0_ro_in[4]
+ PIN sram0_ro_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 445.440 500.000 446.040 ;
+ END
+ END sram0_ro_in[5]
+ PIN sram0_ro_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 663.040 4.000 663.640 ;
+ END
+ END sram0_ro_in[6]
+ PIN sram0_ro_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 115.640 500.000 116.240 ;
+ END
+ END sram0_ro_in[7]
+ PIN sram0_ro_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 353.640 4.000 354.240 ;
+ END
+ END sram0_ro_in[8]
+ PIN sram0_ro_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 147.290 0.000 147.570 4.000 ;
+ END
+ END sram0_ro_in[9]
+ PIN sram0_rw_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 296.790 0.000 297.070 4.000 ;
+ END
+ END sram0_rw_in[0]
+ PIN sram0_rw_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 251.640 4.000 252.240 ;
+ END
+ END sram0_rw_in[10]
+ PIN sram0_rw_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 258.440 500.000 259.040 ;
+ END
+ END sram0_rw_in[11]
+ PIN sram0_rw_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 615.440 500.000 616.040 ;
+ END
+ END sram0_rw_in[12]
+ PIN sram0_rw_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 57.590 0.000 57.870 4.000 ;
+ END
+ END sram0_rw_in[13]
+ PIN sram0_rw_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 387.640 4.000 388.240 ;
+ END
+ END sram0_rw_in[14]
+ PIN sram0_rw_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 241.590 796.000 241.870 800.000 ;
+ END
+ END sram0_rw_in[15]
+ PIN sram0_rw_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 795.640 4.000 796.240 ;
+ END
+ END sram0_rw_in[16]
+ PIN sram0_rw_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 96.690 0.000 96.970 4.000 ;
+ END
+ END sram0_rw_in[17]
+ PIN sram0_rw_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 154.190 796.000 154.470 800.000 ;
+ END
+ END sram0_rw_in[18]
+ PIN sram0_rw_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 335.890 0.000 336.170 4.000 ;
+ END
+ END sram0_rw_in[19]
+ PIN sram0_rw_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 363.840 4.000 364.440 ;
+ END
+ END sram0_rw_in[1]
+ PIN sram0_rw_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 170.040 500.000 170.640 ;
+ END
+ END sram0_rw_in[20]
+ PIN sram0_rw_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 276.090 796.000 276.370 800.000 ;
+ END
+ END sram0_rw_in[21]
+ PIN sram0_rw_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 351.990 796.000 352.270 800.000 ;
+ END
+ END sram0_rw_in[22]
+ PIN sram0_rw_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 523.640 4.000 524.240 ;
+ END
+ END sram0_rw_in[23]
+ PIN sram0_rw_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 686.840 500.000 687.440 ;
+ END
+ END sram0_rw_in[24]
+ PIN sram0_rw_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 676.640 4.000 677.240 ;
+ END
+ END sram0_rw_in[25]
+ PIN sram0_rw_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 377.290 796.000 377.570 800.000 ;
+ END
+ END sram0_rw_in[26]
+ PIN sram0_rw_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 34.040 4.000 34.640 ;
+ END
+ END sram0_rw_in[27]
+ PIN sram0_rw_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 170.290 796.000 170.570 800.000 ;
+ END
+ END sram0_rw_in[28]
+ PIN sram0_rw_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 80.590 0.000 80.870 4.000 ;
+ END
+ END sram0_rw_in[29]
+ PIN sram0_rw_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 437.090 796.000 437.370 800.000 ;
+ END
+ END sram0_rw_in[2]
+ PIN sram0_rw_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 710.640 500.000 711.240 ;
+ END
+ END sram0_rw_in[30]
+ PIN sram0_rw_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 342.790 0.000 343.070 4.000 ;
+ END
+ END sram0_rw_in[31]
+ PIN sram0_rw_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 591.640 4.000 592.240 ;
+ END
+ END sram0_rw_in[3]
+ PIN sram0_rw_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 707.240 500.000 707.840 ;
+ END
+ END sram0_rw_in[4]
+ PIN sram0_rw_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 316.240 500.000 316.840 ;
+ END
+ END sram0_rw_in[5]
+ PIN sram0_rw_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 17.040 4.000 17.640 ;
+ END
+ END sram0_rw_in[6]
+ PIN sram0_rw_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 411.440 500.000 412.040 ;
+ END
+ END sram0_rw_in[7]
+ PIN sram0_rw_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 299.240 4.000 299.840 ;
+ END
+ END sram0_rw_in[8]
+ PIN sram0_rw_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 666.440 4.000 667.040 ;
+ END
+ END sram0_rw_in[9]
+ PIN sram1_connections[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 124.290 0.000 124.570 4.000 ;
+ END
+ END sram1_connections[0]
+ PIN sram1_connections[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 165.690 796.000 165.970 800.000 ;
+ END
+ END sram1_connections[10]
+ PIN sram1_connections[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 224.440 500.000 225.040 ;
+ END
+ END sram1_connections[11]
+ PIN sram1_connections[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 425.040 500.000 425.640 ;
+ END
+ END sram1_connections[12]
+ PIN sram1_connections[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 379.590 796.000 379.870 800.000 ;
+ END
+ END sram1_connections[13]
+ PIN sram1_connections[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 306.040 4.000 306.640 ;
+ END
+ END sram1_connections[14]
+ PIN sram1_connections[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 32.290 796.000 32.570 800.000 ;
+ END
+ END sram1_connections[15]
+ PIN sram1_connections[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 259.990 0.000 260.270 4.000 ;
+ END
+ END sram1_connections[16]
+ PIN sram1_connections[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 78.290 796.000 78.570 800.000 ;
+ END
+ END sram1_connections[17]
+ PIN sram1_connections[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 550.840 500.000 551.440 ;
+ END
+ END sram1_connections[18]
+ PIN sram1_connections[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 326.690 0.000 326.970 4.000 ;
+ END
+ END sram1_connections[19]
+ PIN sram1_connections[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 128.890 0.000 129.170 4.000 ;
+ END
+ END sram1_connections[1]
+ PIN sram1_connections[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 439.390 796.000 439.670 800.000 ;
+ END
+ END sram1_connections[20]
+ PIN sram1_connections[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 428.440 4.000 429.040 ;
+ END
+ END sram1_connections[21]
+ PIN sram1_connections[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 734.440 500.000 735.040 ;
+ END
+ END sram1_connections[22]
+ PIN sram1_connections[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 179.490 796.000 179.770 800.000 ;
+ END
+ END sram1_connections[23]
+ PIN sram1_connections[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 453.190 0.000 453.470 4.000 ;
+ END
+ END sram1_connections[24]
+ PIN sram1_connections[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 343.440 500.000 344.040 ;
+ END
+ END sram1_connections[25]
+ PIN sram1_connections[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 154.190 0.000 154.470 4.000 ;
+ END
+ END sram1_connections[26]
+ PIN sram1_connections[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 13.640 500.000 14.240 ;
+ END
+ END sram1_connections[27]
+ PIN sram1_connections[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 394.440 4.000 395.040 ;
+ END
+ END sram1_connections[28]
+ PIN sram1_connections[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 151.890 796.000 152.170 800.000 ;
+ END
+ END sram1_connections[29]
+ PIN sram1_connections[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 435.240 4.000 435.840 ;
+ END
+ END sram1_connections[2]
+ PIN sram1_connections[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 183.640 500.000 184.240 ;
+ END
+ END sram1_connections[30]
+ PIN sram1_connections[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 673.240 4.000 673.840 ;
+ END
+ END sram1_connections[31]
+ PIN sram1_connections[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 195.590 0.000 195.870 4.000 ;
+ END
+ END sram1_connections[32]
+ PIN sram1_connections[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 557.640 4.000 558.240 ;
+ END
+ END sram1_connections[33]
+ PIN sram1_connections[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 598.440 500.000 599.040 ;
+ END
+ END sram1_connections[34]
+ PIN sram1_connections[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 464.690 796.000 464.970 800.000 ;
+ END
+ END sram1_connections[35]
+ PIN sram1_connections[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 92.090 796.000 92.370 800.000 ;
+ END
+ END sram1_connections[36]
+ PIN sram1_connections[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 264.590 0.000 264.870 4.000 ;
+ END
+ END sram1_connections[37]
+ PIN sram1_connections[38]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 404.640 4.000 405.240 ;
+ END
+ END sram1_connections[38]
+ PIN sram1_connections[39]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 248.490 0.000 248.770 4.000 ;
+ END
+ END sram1_connections[39]
+ PIN sram1_connections[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 74.840 500.000 75.440 ;
+ END
+ END sram1_connections[3]
+ PIN sram1_connections[40]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 345.090 0.000 345.370 4.000 ;
+ END
+ END sram1_connections[40]
+ PIN sram1_connections[41]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 697.040 500.000 697.640 ;
+ END
+ END sram1_connections[41]
+ PIN sram1_connections[42]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 153.040 500.000 153.640 ;
+ END
+ END sram1_connections[42]
+ PIN sram1_connections[43]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 74.840 4.000 75.440 ;
+ END
+ END sram1_connections[43]
+ PIN sram1_connections[44]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 146.240 500.000 146.840 ;
+ END
+ END sram1_connections[44]
+ PIN sram1_connections[45]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 404.640 500.000 405.240 ;
+ END
+ END sram1_connections[45]
+ PIN sram1_connections[46]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 785.440 4.000 786.040 ;
+ END
+ END sram1_connections[46]
+ PIN sram1_connections[47]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 253.090 0.000 253.370 4.000 ;
+ END
+ END sram1_connections[47]
+ PIN sram1_connections[48]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 544.040 500.000 544.640 ;
+ END
+ END sram1_connections[48]
+ PIN sram1_connections[49]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 147.290 796.000 147.570 800.000 ;
+ END
+ END sram1_connections[49]
+ PIN sram1_connections[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 193.840 4.000 194.440 ;
+ END
+ END sram1_connections[4]
+ PIN sram1_connections[50]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 142.840 500.000 143.440 ;
+ END
+ END sram1_connections[50]
+ PIN sram1_connections[51]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 227.790 0.000 228.070 4.000 ;
+ END
+ END sram1_connections[51]
+ PIN sram1_connections[52]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 218.590 796.000 218.870 800.000 ;
+ END
+ END sram1_connections[52]
+ PIN sram1_connections[53]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 680.040 4.000 680.640 ;
+ END
+ END sram1_connections[53]
+ PIN sram1_connections[54]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 202.490 0.000 202.770 4.000 ;
+ END
+ END sram1_connections[54]
+ PIN sram1_connections[55]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 214.240 500.000 214.840 ;
+ END
+ END sram1_connections[55]
+ PIN sram1_connections[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 309.440 500.000 310.040 ;
+ END
+ END sram1_connections[5]
+ PIN sram1_connections[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 119.690 796.000 119.970 800.000 ;
+ END
+ END sram1_connections[6]
+ PIN sram1_connections[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 6.840 4.000 7.440 ;
+ END
+ END sram1_connections[7]
+ PIN sram1_connections[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 190.990 0.000 191.270 4.000 ;
+ END
+ END sram1_connections[8]
+ PIN sram1_connections[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 44.240 4.000 44.840 ;
+ END
+ END sram1_connections[9]
+ PIN sram1_ro_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 358.890 796.000 359.170 800.000 ;
+ END
+ END sram1_ro_in[0]
+ PIN sram1_ro_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 3.440 500.000 4.040 ;
+ END
+ END sram1_ro_in[10]
+ PIN sram1_ro_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 489.990 0.000 490.270 4.000 ;
+ END
+ END sram1_ro_in[11]
+ PIN sram1_ro_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 231.240 500.000 231.840 ;
+ END
+ END sram1_ro_in[12]
+ PIN sram1_ro_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 305.990 796.000 306.270 800.000 ;
+ END
+ END sram1_ro_in[13]
+ PIN sram1_ro_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 156.440 500.000 157.040 ;
+ END
+ END sram1_ro_in[14]
+ PIN sram1_ro_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 462.440 4.000 463.040 ;
+ END
+ END sram1_ro_in[15]
+ PIN sram1_ro_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 414.090 0.000 414.370 4.000 ;
+ END
+ END sram1_ro_in[16]
+ PIN sram1_ro_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 23.840 500.000 24.440 ;
+ END
+ END sram1_ro_in[17]
+ PIN sram1_ro_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 149.640 500.000 150.240 ;
+ END
+ END sram1_ro_in[18]
+ PIN sram1_ro_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 649.440 4.000 650.040 ;
+ END
+ END sram1_ro_in[19]
+ PIN sram1_ro_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 200.190 0.000 200.470 4.000 ;
+ END
+ END sram1_ro_in[1]
+ PIN sram1_ro_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 591.640 500.000 592.240 ;
+ END
+ END sram1_ro_in[20]
+ PIN sram1_ro_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 368.090 796.000 368.370 800.000 ;
+ END
+ END sram1_ro_in[21]
+ PIN sram1_ro_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 493.040 500.000 493.640 ;
+ END
+ END sram1_ro_in[22]
+ PIN sram1_ro_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 489.640 500.000 490.240 ;
+ END
+ END sram1_ro_in[23]
+ PIN sram1_ro_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 273.790 0.000 274.070 4.000 ;
+ END
+ END sram1_ro_in[24]
+ PIN sram1_ro_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 516.840 4.000 517.440 ;
+ END
+ END sram1_ro_in[25]
+ PIN sram1_ro_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 363.490 796.000 363.770 800.000 ;
+ END
+ END sram1_ro_in[26]
+ PIN sram1_ro_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 225.490 796.000 225.770 800.000 ;
+ END
+ END sram1_ro_in[27]
+ PIN sram1_ro_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 377.440 4.000 378.040 ;
+ END
+ END sram1_ro_in[28]
+ PIN sram1_ro_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 221.040 500.000 221.640 ;
+ END
+ END sram1_ro_in[29]
+ PIN sram1_ro_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 102.040 500.000 102.640 ;
+ END
+ END sram1_ro_in[2]
+ PIN sram1_ro_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 61.240 4.000 61.840 ;
+ END
+ END sram1_ro_in[30]
+ PIN sram1_ro_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 782.040 4.000 782.640 ;
+ END
+ END sram1_ro_in[31]
+ PIN sram1_ro_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 209.390 0.000 209.670 4.000 ;
+ END
+ END sram1_ro_in[3]
+ PIN sram1_ro_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 30.640 4.000 31.240 ;
+ END
+ END sram1_ro_in[4]
+ PIN sram1_ro_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 54.440 500.000 55.040 ;
+ END
+ END sram1_ro_in[5]
+ PIN sram1_ro_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 778.640 4.000 779.240 ;
+ END
+ END sram1_ro_in[6]
+ PIN sram1_ro_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 471.590 796.000 471.870 800.000 ;
+ END
+ END sram1_ro_in[7]
+ PIN sram1_ro_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 271.490 0.000 271.770 4.000 ;
+ END
+ END sram1_ro_in[8]
+ PIN sram1_ro_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 91.840 500.000 92.440 ;
+ END
+ END sram1_ro_in[9]
+ PIN sram1_rw_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 144.990 796.000 145.270 800.000 ;
+ END
+ END sram1_rw_in[0]
+ PIN sram1_rw_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 163.390 0.000 163.670 4.000 ;
+ END
+ END sram1_rw_in[10]
+ PIN sram1_rw_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 340.490 796.000 340.770 800.000 ;
+ END
+ END sram1_rw_in[11]
+ PIN sram1_rw_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 241.590 0.000 241.870 4.000 ;
+ END
+ END sram1_rw_in[12]
+ PIN sram1_rw_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 289.040 4.000 289.640 ;
+ END
+ END sram1_rw_in[13]
+ PIN sram1_rw_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 632.440 4.000 633.040 ;
+ END
+ END sram1_rw_in[14]
+ PIN sram1_rw_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 87.490 0.000 87.770 4.000 ;
+ END
+ END sram1_rw_in[15]
+ PIN sram1_rw_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 409.490 0.000 409.770 4.000 ;
+ END
+ END sram1_rw_in[16]
+ PIN sram1_rw_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 421.640 500.000 422.240 ;
+ END
+ END sram1_rw_in[17]
+ PIN sram1_rw_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 308.290 796.000 308.570 800.000 ;
+ END
+ END sram1_rw_in[18]
+ PIN sram1_rw_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 239.290 0.000 239.570 4.000 ;
+ END
+ END sram1_rw_in[19]
+ PIN sram1_rw_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 462.440 500.000 463.040 ;
+ END
+ END sram1_rw_in[1]
+ PIN sram1_rw_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 336.640 500.000 337.240 ;
+ END
+ END sram1_rw_in[20]
+ PIN sram1_rw_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 310.590 0.000 310.870 4.000 ;
+ END
+ END sram1_rw_in[21]
+ PIN sram1_rw_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 434.790 796.000 435.070 800.000 ;
+ END
+ END sram1_rw_in[22]
+ PIN sram1_rw_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 115.090 0.000 115.370 4.000 ;
+ END
+ END sram1_rw_in[23]
+ PIN sram1_rw_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 184.090 796.000 184.370 800.000 ;
+ END
+ END sram1_rw_in[24]
+ PIN sram1_rw_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 82.890 0.000 83.170 4.000 ;
+ END
+ END sram1_rw_in[25]
+ PIN sram1_rw_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 710.640 4.000 711.240 ;
+ END
+ END sram1_rw_in[26]
+ PIN sram1_rw_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 110.490 796.000 110.770 800.000 ;
+ END
+ END sram1_rw_in[27]
+ PIN sram1_rw_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 197.240 500.000 197.840 ;
+ END
+ END sram1_rw_in[28]
+ PIN sram1_rw_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 85.190 796.000 85.470 800.000 ;
+ END
+ END sram1_rw_in[29]
+ PIN sram1_rw_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 193.290 796.000 193.570 800.000 ;
+ END
+ END sram1_rw_in[2]
+ PIN sram1_rw_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 136.040 4.000 136.640 ;
+ END
+ END sram1_rw_in[30]
+ PIN sram1_rw_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 264.590 796.000 264.870 800.000 ;
+ END
+ END sram1_rw_in[31]
+ PIN sram1_rw_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 693.640 500.000 694.240 ;
+ END
+ END sram1_rw_in[3]
+ PIN sram1_rw_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 494.590 796.000 494.870 800.000 ;
+ END
+ END sram1_rw_in[4]
+ PIN sram1_rw_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 32.290 0.000 32.570 4.000 ;
+ END
+ END sram1_rw_in[5]
+ PIN sram1_rw_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 465.840 500.000 466.440 ;
+ END
+ END sram1_rw_in[6]
+ PIN sram1_rw_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 356.590 796.000 356.870 800.000 ;
+ END
+ END sram1_rw_in[7]
+ PIN sram1_rw_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 39.190 796.000 39.470 800.000 ;
+ END
+ END sram1_rw_in[8]
+ PIN sram1_rw_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 210.840 4.000 211.440 ;
+ END
+ END sram1_rw_in[9]
+ PIN sram2_connections[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 737.840 4.000 738.440 ;
+ END
+ END sram2_connections[0]
+ PIN sram2_connections[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 425.590 0.000 425.870 4.000 ;
+ END
+ END sram2_connections[10]
+ PIN sram2_connections[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 125.840 4.000 126.440 ;
+ END
+ END sram2_connections[11]
+ PIN sram2_connections[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 418.240 500.000 418.840 ;
+ END
+ END sram2_connections[12]
+ PIN sram2_connections[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 421.640 4.000 422.240 ;
+ END
+ END sram2_connections[13]
+ PIN sram2_connections[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 317.490 796.000 317.770 800.000 ;
+ END
+ END sram2_connections[14]
+ PIN sram2_connections[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 622.240 500.000 622.840 ;
+ END
+ END sram2_connections[15]
+ PIN sram2_connections[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 420.990 796.000 421.270 800.000 ;
+ END
+ END sram2_connections[16]
+ PIN sram2_connections[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 388.790 0.000 389.070 4.000 ;
+ END
+ END sram2_connections[17]
+ PIN sram2_connections[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 25.390 796.000 25.670 800.000 ;
+ END
+ END sram2_connections[18]
+ PIN sram2_connections[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 27.690 796.000 27.970 800.000 ;
+ END
+ END sram2_connections[19]
+ PIN sram2_connections[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 547.440 4.000 548.040 ;
+ END
+ END sram2_connections[1]
+ PIN sram2_connections[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 98.640 500.000 99.240 ;
+ END
+ END sram2_connections[20]
+ PIN sram2_connections[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 94.390 796.000 94.670 800.000 ;
+ END
+ END sram2_connections[21]
+ PIN sram2_connections[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 241.440 4.000 242.040 ;
+ END
+ END sram2_connections[22]
+ PIN sram2_connections[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 533.840 4.000 534.440 ;
+ END
+ END sram2_connections[23]
+ PIN sram2_connections[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 172.590 796.000 172.870 800.000 ;
+ END
+ END sram2_connections[24]
+ PIN sram2_connections[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 697.040 4.000 697.640 ;
+ END
+ END sram2_connections[25]
+ PIN sram2_connections[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 4.690 796.000 4.970 800.000 ;
+ END
+ END sram2_connections[26]
+ PIN sram2_connections[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 142.840 4.000 143.440 ;
+ END
+ END sram2_connections[27]
+ PIN sram2_connections[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 347.390 0.000 347.670 4.000 ;
+ END
+ END sram2_connections[28]
+ PIN sram2_connections[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 380.840 4.000 381.440 ;
+ END
+ END sram2_connections[29]
+ PIN sram2_connections[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 414.840 500.000 415.440 ;
+ END
+ END sram2_connections[2]
+ PIN sram2_connections[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 280.690 796.000 280.970 800.000 ;
+ END
+ END sram2_connections[30]
+ PIN sram2_connections[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 625.640 4.000 626.240 ;
+ END
+ END sram2_connections[31]
+ PIN sram2_connections[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 386.490 0.000 386.770 4.000 ;
+ END
+ END sram2_connections[32]
+ PIN sram2_connections[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 724.240 4.000 724.840 ;
+ END
+ END sram2_connections[33]
+ PIN sram2_connections[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 714.040 500.000 714.640 ;
+ END
+ END sram2_connections[34]
+ PIN sram2_connections[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 6.990 0.000 7.270 4.000 ;
+ END
+ END sram2_connections[35]
+ PIN sram2_connections[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 20.790 0.000 21.070 4.000 ;
+ END
+ END sram2_connections[36]
+ PIN sram2_connections[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 225.490 0.000 225.770 4.000 ;
+ END
+ END sram2_connections[37]
+ PIN sram2_connections[38]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 438.640 500.000 439.240 ;
+ END
+ END sram2_connections[38]
+ PIN sram2_connections[39]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 71.440 4.000 72.040 ;
+ END
+ END sram2_connections[39]
+ PIN sram2_connections[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 122.440 500.000 123.040 ;
+ END
+ END sram2_connections[3]
+ PIN sram2_connections[40]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 652.840 500.000 653.440 ;
+ END
+ END sram2_connections[40]
+ PIN sram2_connections[41]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 180.240 500.000 180.840 ;
+ END
+ END sram2_connections[41]
+ PIN sram2_connections[42]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 768.440 500.000 769.040 ;
+ END
+ END sram2_connections[42]
+ PIN sram2_connections[43]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 98.990 796.000 99.270 800.000 ;
+ END
+ END sram2_connections[43]
+ PIN sram2_connections[44]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 255.390 796.000 255.670 800.000 ;
+ END
+ END sram2_connections[44]
+ PIN sram2_connections[45]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 646.040 500.000 646.640 ;
+ END
+ END sram2_connections[45]
+ PIN sram2_connections[46]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 218.590 0.000 218.870 4.000 ;
+ END
+ END sram2_connections[46]
+ PIN sram2_connections[47]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 703.840 500.000 704.440 ;
+ END
+ END sram2_connections[47]
+ PIN sram2_connections[48]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 615.440 4.000 616.040 ;
+ END
+ END sram2_connections[48]
+ PIN sram2_connections[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 41.490 0.000 41.770 4.000 ;
+ END
+ END sram2_connections[4]
+ PIN sram2_connections[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 261.840 4.000 262.440 ;
+ END
+ END sram2_connections[5]
+ PIN sram2_connections[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 112.790 0.000 113.070 4.000 ;
+ END
+ END sram2_connections[6]
+ PIN sram2_connections[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 50.690 0.000 50.970 4.000 ;
+ END
+ END sram2_connections[7]
+ PIN sram2_connections[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 333.240 500.000 333.840 ;
+ END
+ END sram2_connections[8]
+ PIN sram2_connections[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 181.790 0.000 182.070 4.000 ;
+ END
+ END sram2_connections[9]
+ PIN sram2_rw_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 239.290 796.000 239.570 800.000 ;
+ END
+ END sram2_rw_in[0]
+ PIN sram2_rw_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 673.240 500.000 673.840 ;
+ END
+ END sram2_rw_in[10]
+ PIN sram2_rw_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 455.490 0.000 455.770 4.000 ;
+ END
+ END sram2_rw_in[11]
+ PIN sram2_rw_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 557.640 500.000 558.240 ;
+ END
+ END sram2_rw_in[12]
+ PIN sram2_rw_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 346.840 4.000 347.440 ;
+ END
+ END sram2_rw_in[13]
+ PIN sram2_rw_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 236.990 0.000 237.270 4.000 ;
+ END
+ END sram2_rw_in[14]
+ PIN sram2_rw_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 407.190 0.000 407.470 4.000 ;
+ END
+ END sram2_rw_in[15]
+ PIN sram2_rw_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 101.290 0.000 101.570 4.000 ;
+ END
+ END sram2_rw_in[16]
+ PIN sram2_rw_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 363.490 0.000 363.770 4.000 ;
+ END
+ END sram2_rw_in[17]
+ PIN sram2_rw_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 66.790 0.000 67.070 4.000 ;
+ END
+ END sram2_rw_in[18]
+ PIN sram2_rw_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 453.190 796.000 453.470 800.000 ;
+ END
+ END sram2_rw_in[19]
+ PIN sram2_rw_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 379.590 0.000 379.870 4.000 ;
+ END
+ END sram2_rw_in[1]
+ PIN sram2_rw_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 370.640 500.000 371.240 ;
+ END
+ END sram2_rw_in[20]
+ PIN sram2_rw_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 51.040 4.000 51.640 ;
+ END
+ END sram2_rw_in[21]
+ PIN sram2_rw_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 47.640 500.000 48.240 ;
+ END
+ END sram2_rw_in[22]
+ PIN sram2_rw_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 372.690 0.000 372.970 4.000 ;
+ END
+ END sram2_rw_in[23]
+ PIN sram2_rw_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 408.040 4.000 408.640 ;
+ END
+ END sram2_rw_in[24]
+ PIN sram2_rw_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 492.290 0.000 492.570 4.000 ;
+ END
+ END sram2_rw_in[25]
+ PIN sram2_rw_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 578.040 4.000 578.640 ;
+ END
+ END sram2_rw_in[26]
+ PIN sram2_rw_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 234.690 0.000 234.970 4.000 ;
+ END
+ END sram2_rw_in[27]
+ PIN sram2_rw_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 103.590 796.000 103.870 800.000 ;
+ END
+ END sram2_rw_in[28]
+ PIN sram2_rw_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 445.440 4.000 446.040 ;
+ END
+ END sram2_rw_in[29]
+ PIN sram2_rw_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 40.840 500.000 41.440 ;
+ END
+ END sram2_rw_in[2]
+ PIN sram2_rw_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 397.990 796.000 398.270 800.000 ;
+ END
+ END sram2_rw_in[30]
+ PIN sram2_rw_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 257.690 796.000 257.970 800.000 ;
+ END
+ END sram2_rw_in[31]
+ PIN sram2_rw_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 78.240 500.000 78.840 ;
+ END
+ END sram2_rw_in[3]
+ PIN sram2_rw_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 131.190 0.000 131.470 4.000 ;
+ END
+ END sram2_rw_in[4]
+ PIN sram2_rw_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 110.490 0.000 110.770 4.000 ;
+ END
+ END sram2_rw_in[5]
+ PIN sram2_rw_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 25.390 0.000 25.670 4.000 ;
+ END
+ END sram2_rw_in[6]
+ PIN sram2_rw_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 170.290 0.000 170.570 4.000 ;
+ END
+ END sram2_rw_in[7]
+ PIN sram2_rw_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 523.640 500.000 524.240 ;
+ END
+ END sram2_rw_in[8]
+ PIN sram2_rw_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 466.990 796.000 467.270 800.000 ;
+ END
+ END sram2_rw_in[9]
+ PIN sram3_connections[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 370.390 796.000 370.670 800.000 ;
+ END
+ END sram3_connections[0]
+ PIN sram3_connections[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 292.440 500.000 293.040 ;
+ END
+ END sram3_connections[10]
+ PIN sram3_connections[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 612.040 4.000 612.640 ;
+ END
+ END sram3_connections[11]
+ PIN sram3_connections[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 478.490 0.000 478.770 4.000 ;
+ END
+ END sram3_connections[12]
+ PIN sram3_connections[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 761.640 500.000 762.240 ;
+ END
+ END sram3_connections[13]
+ PIN sram3_connections[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 430.190 796.000 430.470 800.000 ;
+ END
+ END sram3_connections[14]
+ PIN sram3_connections[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 121.990 0.000 122.270 4.000 ;
+ END
+ END sram3_connections[15]
+ PIN sram3_connections[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 132.640 500.000 133.240 ;
+ END
+ END sram3_connections[16]
+ PIN sram3_connections[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 258.440 4.000 259.040 ;
+ END
+ END sram3_connections[17]
+ PIN sram3_connections[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 142.690 796.000 142.970 800.000 ;
+ END
+ END sram3_connections[18]
+ PIN sram3_connections[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 312.840 4.000 313.440 ;
+ END
+ END sram3_connections[19]
+ PIN sram3_connections[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 384.240 4.000 384.840 ;
+ END
+ END sram3_connections[1]
+ PIN sram3_connections[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 47.640 4.000 48.240 ;
+ END
+ END sram3_connections[20]
+ PIN sram3_connections[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 328.990 0.000 329.270 4.000 ;
+ END
+ END sram3_connections[21]
+ PIN sram3_connections[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 273.790 796.000 274.070 800.000 ;
+ END
+ END sram3_connections[22]
+ PIN sram3_connections[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 561.040 4.000 561.640 ;
+ END
+ END sram3_connections[23]
+ PIN sram3_connections[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 349.690 0.000 349.970 4.000 ;
+ END
+ END sram3_connections[24]
+ PIN sram3_connections[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 209.390 796.000 209.670 800.000 ;
+ END
+ END sram3_connections[25]
+ PIN sram3_connections[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 315.190 796.000 315.470 800.000 ;
+ END
+ END sram3_connections[26]
+ PIN sram3_connections[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 370.390 0.000 370.670 4.000 ;
+ END
+ END sram3_connections[27]
+ PIN sram3_connections[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 255.390 0.000 255.670 4.000 ;
+ END
+ END sram3_connections[28]
+ PIN sram3_connections[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 584.840 4.000 585.440 ;
+ END
+ END sram3_connections[29]
+ PIN sram3_connections[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 34.590 0.000 34.870 4.000 ;
+ END
+ END sram3_connections[2]
+ PIN sram3_connections[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 326.690 796.000 326.970 800.000 ;
+ END
+ END sram3_connections[30]
+ PIN sram3_connections[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 333.590 796.000 333.870 800.000 ;
+ END
+ END sram3_connections[31]
+ PIN sram3_connections[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 363.840 500.000 364.440 ;
+ END
+ END sram3_connections[32]
+ PIN sram3_connections[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 400.290 0.000 400.570 4.000 ;
+ END
+ END sram3_connections[33]
+ PIN sram3_connections[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 23.090 0.000 23.370 4.000 ;
+ END
+ END sram3_connections[34]
+ PIN sram3_connections[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 105.440 500.000 106.040 ;
+ END
+ END sram3_connections[35]
+ PIN sram3_connections[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 117.390 796.000 117.670 800.000 ;
+ END
+ END sram3_connections[36]
+ PIN sram3_connections[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 126.590 796.000 126.870 800.000 ;
+ END
+ END sram3_connections[37]
+ PIN sram3_connections[38]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 265.240 500.000 265.840 ;
+ END
+ END sram3_connections[38]
+ PIN sram3_connections[39]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 11.590 0.000 11.870 4.000 ;
+ END
+ END sram3_connections[39]
+ PIN sram3_connections[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 243.890 796.000 244.170 800.000 ;
+ END
+ END sram3_connections[3]
+ PIN sram3_connections[40]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 197.240 4.000 197.840 ;
+ END
+ END sram3_connections[40]
+ PIN sram3_connections[41]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 78.290 0.000 78.570 4.000 ;
+ END
+ END sram3_connections[41]
+ PIN sram3_connections[42]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 571.240 4.000 571.840 ;
+ END
+ END sram3_connections[42]
+ PIN sram3_connections[43]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 384.240 500.000 384.840 ;
+ END
+ END sram3_connections[43]
+ PIN sram3_connections[44]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 324.390 0.000 324.670 4.000 ;
+ END
+ END sram3_connections[44]
+ PIN sram3_connections[45]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 342.790 796.000 343.070 800.000 ;
+ END
+ END sram3_connections[45]
+ PIN sram3_connections[46]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 397.990 0.000 398.270 4.000 ;
+ END
+ END sram3_connections[46]
+ PIN sram3_connections[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 516.840 500.000 517.440 ;
+ END
+ END sram3_connections[4]
+ PIN sram3_connections[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 71.390 0.000 71.670 4.000 ;
+ END
+ END sram3_connections[5]
+ PIN sram3_connections[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 360.440 500.000 361.040 ;
+ END
+ END sram3_connections[6]
+ PIN sram3_connections[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 186.390 0.000 186.670 4.000 ;
+ END
+ END sram3_connections[7]
+ PIN sram3_connections[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 246.190 796.000 246.470 800.000 ;
+ END
+ END sram3_connections[8]
+ PIN sram3_connections[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 452.240 4.000 452.840 ;
+ END
+ END sram3_connections[9]
+ PIN sram3_rw_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 437.090 0.000 437.370 4.000 ;
+ END
+ END sram3_rw_in[0]
+ PIN sram3_rw_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 282.990 0.000 283.270 4.000 ;
+ END
+ END sram3_rw_in[10]
+ PIN sram3_rw_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 493.040 4.000 493.640 ;
+ END
+ END sram3_rw_in[11]
+ PIN sram3_rw_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 492.290 796.000 492.570 800.000 ;
+ END
+ END sram3_rw_in[12]
+ PIN sram3_rw_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 82.890 796.000 83.170 800.000 ;
+ END
+ END sram3_rw_in[13]
+ PIN sram3_rw_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 312.890 0.000 313.170 4.000 ;
+ END
+ END sram3_rw_in[14]
+ PIN sram3_rw_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 469.290 0.000 469.570 4.000 ;
+ END
+ END sram3_rw_in[15]
+ PIN sram3_rw_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 244.840 4.000 245.440 ;
+ END
+ END sram3_rw_in[16]
+ PIN sram3_rw_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 51.040 500.000 51.640 ;
+ END
+ END sram3_rw_in[17]
+ PIN sram3_rw_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 37.440 500.000 38.040 ;
+ END
+ END sram3_rw_in[18]
+ PIN sram3_rw_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 510.040 4.000 510.640 ;
+ END
+ END sram3_rw_in[19]
+ PIN sram3_rw_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 418.690 0.000 418.970 4.000 ;
+ END
+ END sram3_rw_in[1]
+ PIN sram3_rw_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 85.040 4.000 85.640 ;
+ END
+ END sram3_rw_in[20]
+ PIN sram3_rw_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 95.240 500.000 95.840 ;
+ END
+ END sram3_rw_in[21]
+ PIN sram3_rw_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 50.690 796.000 50.970 800.000 ;
+ END
+ END sram3_rw_in[22]
+ PIN sram3_rw_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 29.990 796.000 30.270 800.000 ;
+ END
+ END sram3_rw_in[23]
+ PIN sram3_rw_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 269.190 796.000 269.470 800.000 ;
+ END
+ END sram3_rw_in[24]
+ PIN sram3_rw_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 64.490 796.000 64.770 800.000 ;
+ END
+ END sram3_rw_in[25]
+ PIN sram3_rw_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 353.640 500.000 354.240 ;
+ END
+ END sram3_rw_in[26]
+ PIN sram3_rw_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 266.890 0.000 267.170 4.000 ;
+ END
+ END sram3_rw_in[27]
+ PIN sram3_rw_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 473.890 0.000 474.170 4.000 ;
+ END
+ END sram3_rw_in[28]
+ PIN sram3_rw_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 720.840 4.000 721.440 ;
+ END
+ END sram3_rw_in[29]
+ PIN sram3_rw_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 289.040 500.000 289.640 ;
+ END
+ END sram3_rw_in[2]
+ PIN sram3_rw_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 27.690 0.000 27.970 4.000 ;
+ END
+ END sram3_rw_in[30]
+ PIN sram3_rw_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 10.240 4.000 10.840 ;
+ END
+ END sram3_rw_in[31]
+ PIN sram3_rw_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 676.640 500.000 677.240 ;
+ END
+ END sram3_rw_in[3]
+ PIN sram3_rw_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 625.640 500.000 626.240 ;
+ END
+ END sram3_rw_in[4]
+ PIN sram3_rw_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 416.390 796.000 416.670 800.000 ;
+ END
+ END sram3_rw_in[5]
+ PIN sram3_rw_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 486.240 4.000 486.840 ;
+ END
+ END sram3_rw_in[6]
+ PIN sram3_rw_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 200.190 796.000 200.470 800.000 ;
+ END
+ END sram3_rw_in[7]
+ PIN sram3_rw_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 499.840 500.000 500.440 ;
+ END
+ END sram3_rw_in[8]
+ PIN sram3_rw_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 146.240 4.000 146.840 ;
+ END
+ END sram3_rw_in[9]
+ PIN sram4_connections[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 754.840 4.000 755.440 ;
+ END
+ END sram4_connections[0]
+ PIN sram4_connections[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 310.590 796.000 310.870 800.000 ;
+ END
+ END sram4_connections[10]
+ PIN sram4_connections[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 282.240 500.000 282.840 ;
+ END
+ END sram4_connections[11]
+ PIN sram4_connections[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 367.240 4.000 367.840 ;
+ END
+ END sram4_connections[12]
+ PIN sram4_connections[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 731.040 500.000 731.640 ;
+ END
+ END sram4_connections[13]
+ PIN sram4_connections[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 251.640 500.000 252.240 ;
+ END
+ END sram4_connections[14]
+ PIN sram4_connections[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 544.040 4.000 544.640 ;
+ END
+ END sram4_connections[15]
+ PIN sram4_connections[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 513.440 4.000 514.040 ;
+ END
+ END sram4_connections[16]
+ PIN sram4_connections[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 605.240 500.000 605.840 ;
+ END
+ END sram4_connections[17]
+ PIN sram4_connections[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 184.090 0.000 184.370 4.000 ;
+ END
+ END sram4_connections[18]
+ PIN sram4_connections[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 105.890 0.000 106.170 4.000 ;
+ END
+ END sram4_connections[19]
+ PIN sram4_connections[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 94.390 0.000 94.670 4.000 ;
+ END
+ END sram4_connections[1]
+ PIN sram4_connections[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 96.690 796.000 96.970 800.000 ;
+ END
+ END sram4_connections[20]
+ PIN sram4_connections[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 55.290 796.000 55.570 800.000 ;
+ END
+ END sram4_connections[21]
+ PIN sram4_connections[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 188.690 0.000 188.970 4.000 ;
+ END
+ END sram4_connections[22]
+ PIN sram4_connections[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 700.440 4.000 701.040 ;
+ END
+ END sram4_connections[23]
+ PIN sram4_connections[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 394.440 500.000 395.040 ;
+ END
+ END sram4_connections[24]
+ PIN sram4_connections[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 775.240 4.000 775.840 ;
+ END
+ END sram4_connections[25]
+ PIN sram4_connections[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 289.890 796.000 290.170 800.000 ;
+ END
+ END sram4_connections[26]
+ PIN sram4_connections[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 238.040 500.000 238.640 ;
+ END
+ END sram4_connections[27]
+ PIN sram4_connections[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 135.790 0.000 136.070 4.000 ;
+ END
+ END sram4_connections[28]
+ PIN sram4_connections[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 6.990 796.000 7.270 800.000 ;
+ END
+ END sram4_connections[29]
+ PIN sram4_connections[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 618.840 500.000 619.440 ;
+ END
+ END sram4_connections[2]
+ PIN sram4_connections[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 431.840 4.000 432.440 ;
+ END
+ END sram4_connections[30]
+ PIN sram4_connections[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 374.040 4.000 374.640 ;
+ END
+ END sram4_connections[31]
+ PIN sram4_connections[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 608.640 500.000 609.240 ;
+ END
+ END sram4_connections[32]
+ PIN sram4_connections[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 186.390 796.000 186.670 800.000 ;
+ END
+ END sram4_connections[33]
+ PIN sram4_connections[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 357.040 500.000 357.640 ;
+ END
+ END sram4_connections[34]
+ PIN sram4_connections[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 13.640 4.000 14.240 ;
+ END
+ END sram4_connections[35]
+ PIN sram4_connections[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 117.390 0.000 117.670 4.000 ;
+ END
+ END sram4_connections[36]
+ PIN sram4_connections[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 331.290 796.000 331.570 800.000 ;
+ END
+ END sram4_connections[37]
+ PIN sram4_connections[38]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 62.190 796.000 62.470 800.000 ;
+ END
+ END sram4_connections[38]
+ PIN sram4_connections[39]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 64.490 0.000 64.770 4.000 ;
+ END
+ END sram4_connections[39]
+ PIN sram4_connections[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 211.690 0.000 211.970 4.000 ;
+ END
+ END sram4_connections[3]
+ PIN sram4_connections[40]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 473.890 796.000 474.170 800.000 ;
+ END
+ END sram4_connections[40]
+ PIN sram4_connections[41]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 402.590 0.000 402.870 4.000 ;
+ END
+ END sram4_connections[41]
+ PIN sram4_connections[42]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 388.790 796.000 389.070 800.000 ;
+ END
+ END sram4_connections[42]
+ PIN sram4_connections[43]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 642.640 500.000 643.240 ;
+ END
+ END sram4_connections[43]
+ PIN sram4_connections[44]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 520.240 500.000 520.840 ;
+ END
+ END sram4_connections[44]
+ PIN sram4_connections[45]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 485.390 0.000 485.670 4.000 ;
+ END
+ END sram4_connections[45]
+ PIN sram4_connections[46]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 782.040 500.000 782.640 ;
+ END
+ END sram4_connections[46]
+ PIN sram4_connections[47]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 326.440 500.000 327.040 ;
+ END
+ END sram4_connections[47]
+ PIN sram4_connections[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 234.640 500.000 235.240 ;
+ END
+ END sram4_connections[4]
+ PIN sram4_connections[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 275.440 4.000 276.040 ;
+ END
+ END sram4_connections[5]
+ PIN sram4_connections[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 442.040 4.000 442.640 ;
+ END
+ END sram4_connections[6]
+ PIN sram4_connections[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 34.040 500.000 34.640 ;
+ END
+ END sram4_connections[7]
+ PIN sram4_connections[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 294.490 0.000 294.770 4.000 ;
+ END
+ END sram4_connections[8]
+ PIN sram4_connections[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 420.990 0.000 421.270 4.000 ;
+ END
+ END sram4_connections[9]
+ PIN sram4_rw_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 220.890 796.000 221.170 800.000 ;
+ END
+ END sram4_rw_in[0]
+ PIN sram4_rw_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 207.440 4.000 208.040 ;
+ END
+ END sram4_rw_in[10]
+ PIN sram4_rw_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 202.490 796.000 202.770 800.000 ;
+ END
+ END sram4_rw_in[11]
+ PIN sram4_rw_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 448.840 500.000 449.440 ;
+ END
+ END sram4_rw_in[12]
+ PIN sram4_rw_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 156.440 4.000 157.040 ;
+ END
+ END sram4_rw_in[13]
+ PIN sram4_rw_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 204.790 0.000 205.070 4.000 ;
+ END
+ END sram4_rw_in[14]
+ PIN sram4_rw_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 402.590 796.000 402.870 800.000 ;
+ END
+ END sram4_rw_in[15]
+ PIN sram4_rw_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 308.290 0.000 308.570 4.000 ;
+ END
+ END sram4_rw_in[16]
+ PIN sram4_rw_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 138.090 0.000 138.370 4.000 ;
+ END
+ END sram4_rw_in[17]
+ PIN sram4_rw_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 193.840 500.000 194.440 ;
+ END
+ END sram4_rw_in[18]
+ PIN sram4_rw_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 775.240 500.000 775.840 ;
+ END
+ END sram4_rw_in[19]
+ PIN sram4_rw_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 255.040 4.000 255.640 ;
+ END
+ END sram4_rw_in[1]
+ PIN sram4_rw_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 727.640 500.000 728.240 ;
+ END
+ END sram4_rw_in[20]
+ PIN sram4_rw_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 101.290 796.000 101.570 800.000 ;
+ END
+ END sram4_rw_in[21]
+ PIN sram4_rw_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 381.890 0.000 382.170 4.000 ;
+ END
+ END sram4_rw_in[22]
+ PIN sram4_rw_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 29.990 0.000 30.270 4.000 ;
+ END
+ END sram4_rw_in[23]
+ PIN sram4_rw_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 635.840 500.000 636.440 ;
+ END
+ END sram4_rw_in[24]
+ PIN sram4_rw_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 649.440 500.000 650.040 ;
+ END
+ END sram4_rw_in[25]
+ PIN sram4_rw_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 581.440 500.000 582.040 ;
+ END
+ END sram4_rw_in[26]
+ PIN sram4_rw_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 275.440 500.000 276.040 ;
+ END
+ END sram4_rw_in[27]
+ PIN sram4_rw_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 578.040 500.000 578.640 ;
+ END
+ END sram4_rw_in[28]
+ PIN sram4_rw_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 384.190 796.000 384.470 800.000 ;
+ END
+ END sram4_rw_in[29]
+ PIN sram4_rw_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 73.690 796.000 73.970 800.000 ;
+ END
+ END sram4_rw_in[2]
+ PIN sram4_rw_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 190.990 796.000 191.270 800.000 ;
+ END
+ END sram4_rw_in[30]
+ PIN sram4_rw_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 414.090 796.000 414.370 800.000 ;
+ END
+ END sram4_rw_in[31]
+ PIN sram4_rw_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 618.840 4.000 619.440 ;
+ END
+ END sram4_rw_in[3]
+ PIN sram4_rw_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 315.190 0.000 315.470 4.000 ;
+ END
+ END sram4_rw_in[4]
+ PIN sram4_rw_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 23.090 796.000 23.370 800.000 ;
+ END
+ END sram4_rw_in[5]
+ PIN sram4_rw_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 642.640 4.000 643.240 ;
+ END
+ END sram4_rw_in[6]
+ PIN sram4_rw_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 46.090 0.000 46.370 4.000 ;
+ END
+ END sram4_rw_in[7]
+ PIN sram4_rw_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 646.040 4.000 646.640 ;
+ END
+ END sram4_rw_in[8]
+ PIN sram4_rw_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 136.040 500.000 136.640 ;
+ END
+ END sram4_rw_in[9]
+ PIN sram5_connections[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 540.640 4.000 541.240 ;
+ END
+ END sram5_connections[0]
+ PIN sram5_connections[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 480.790 0.000 481.070 4.000 ;
+ END
+ END sram5_connections[10]
+ PIN sram5_connections[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 510.040 500.000 510.640 ;
+ END
+ END sram5_connections[11]
+ PIN sram5_connections[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 663.040 500.000 663.640 ;
+ END
+ END sram5_connections[12]
+ PIN sram5_connections[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 20.790 796.000 21.070 800.000 ;
+ END
+ END sram5_connections[13]
+ PIN sram5_connections[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 457.790 0.000 458.070 4.000 ;
+ END
+ END sram5_connections[14]
+ PIN sram5_connections[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 159.840 500.000 160.440 ;
+ END
+ END sram5_connections[15]
+ PIN sram5_connections[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 204.040 4.000 204.640 ;
+ END
+ END sram5_connections[16]
+ PIN sram5_connections[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 478.490 796.000 478.770 800.000 ;
+ END
+ END sram5_connections[17]
+ PIN sram5_connections[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 574.640 4.000 575.240 ;
+ END
+ END sram5_connections[18]
+ PIN sram5_connections[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 43.790 0.000 44.070 4.000 ;
+ END
+ END sram5_connections[19]
+ PIN sram5_connections[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 751.440 500.000 752.040 ;
+ END
+ END sram5_connections[1]
+ PIN sram5_connections[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 720.840 500.000 721.440 ;
+ END
+ END sram5_connections[20]
+ PIN sram5_connections[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 367.240 500.000 367.840 ;
+ END
+ END sram5_connections[21]
+ PIN sram5_connections[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 550.840 4.000 551.440 ;
+ END
+ END sram5_connections[22]
+ PIN sram5_connections[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 200.640 500.000 201.240 ;
+ END
+ END sram5_connections[23]
+ PIN sram5_connections[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 122.440 4.000 123.040 ;
+ END
+ END sram5_connections[24]
+ PIN sram5_connections[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 91.840 4.000 92.440 ;
+ END
+ END sram5_connections[25]
+ PIN sram5_connections[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 442.040 500.000 442.640 ;
+ END
+ END sram5_connections[26]
+ PIN sram5_connections[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 57.590 796.000 57.870 800.000 ;
+ END
+ END sram5_connections[27]
+ PIN sram5_connections[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 188.690 796.000 188.970 800.000 ;
+ END
+ END sram5_connections[28]
+ PIN sram5_connections[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 446.290 796.000 446.570 800.000 ;
+ END
+ END sram5_connections[29]
+ PIN sram5_connections[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 506.640 4.000 507.240 ;
+ END
+ END sram5_connections[2]
+ PIN sram5_connections[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 303.690 796.000 303.970 800.000 ;
+ END
+ END sram5_connections[30]
+ PIN sram5_connections[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 459.040 4.000 459.640 ;
+ END
+ END sram5_connections[31]
+ PIN sram5_connections[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 323.040 4.000 323.640 ;
+ END
+ END sram5_connections[32]
+ PIN sram5_connections[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 139.440 4.000 140.040 ;
+ END
+ END sram5_connections[33]
+ PIN sram5_connections[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 71.440 500.000 72.040 ;
+ END
+ END sram5_connections[34]
+ PIN sram5_connections[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 213.990 796.000 214.270 800.000 ;
+ END
+ END sram5_connections[35]
+ PIN sram5_connections[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 230.090 0.000 230.370 4.000 ;
+ END
+ END sram5_connections[36]
+ PIN sram5_connections[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 108.840 500.000 109.440 ;
+ END
+ END sram5_connections[37]
+ PIN sram5_connections[38]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 282.240 4.000 282.840 ;
+ END
+ END sram5_connections[38]
+ PIN sram5_connections[39]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 571.240 500.000 571.840 ;
+ END
+ END sram5_connections[39]
+ PIN sram5_connections[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 248.240 4.000 248.840 ;
+ END
+ END sram5_connections[3]
+ PIN sram5_connections[40]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 346.840 500.000 347.440 ;
+ END
+ END sram5_connections[40]
+ PIN sram5_connections[41]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 357.040 4.000 357.640 ;
+ END
+ END sram5_connections[41]
+ PIN sram5_connections[42]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 351.990 0.000 352.270 4.000 ;
+ END
+ END sram5_connections[42]
+ PIN sram5_connections[43]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 278.840 4.000 279.440 ;
+ END
+ END sram5_connections[43]
+ PIN sram5_connections[44]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 221.040 4.000 221.640 ;
+ END
+ END sram5_connections[44]
+ PIN sram5_connections[45]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 153.040 4.000 153.640 ;
+ END
+ END sram5_connections[45]
+ PIN sram5_connections[46]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 69.090 0.000 69.370 4.000 ;
+ END
+ END sram5_connections[46]
+ PIN sram5_connections[47]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 356.590 0.000 356.870 4.000 ;
+ END
+ END sram5_connections[47]
+ PIN sram5_connections[48]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 176.840 4.000 177.440 ;
+ END
+ END sram5_connections[48]
+ PIN sram5_connections[49]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 59.890 0.000 60.170 4.000 ;
+ END
+ END sram5_connections[49]
+ PIN sram5_connections[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 57.840 4.000 58.440 ;
+ END
+ END sram5_connections[4]
+ PIN sram5_connections[50]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 365.790 796.000 366.070 800.000 ;
+ END
+ END sram5_connections[50]
+ PIN sram5_connections[51]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 595.040 4.000 595.640 ;
+ END
+ END sram5_connections[51]
+ PIN sram5_connections[52]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 765.040 4.000 765.640 ;
+ END
+ END sram5_connections[52]
+ PIN sram5_connections[53]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 778.640 500.000 779.240 ;
+ END
+ END sram5_connections[53]
+ PIN sram5_connections[54]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 156.490 796.000 156.770 800.000 ;
+ END
+ END sram5_connections[54]
+ PIN sram5_connections[55]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 78.240 4.000 78.840 ;
+ END
+ END sram5_connections[55]
+ PIN sram5_connections[56]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 349.690 796.000 349.970 800.000 ;
+ END
+ END sram5_connections[56]
+ PIN sram5_connections[57]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 680.040 500.000 680.640 ;
+ END
+ END sram5_connections[57]
+ PIN sram5_connections[58]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 564.440 500.000 565.040 ;
+ END
+ END sram5_connections[58]
+ PIN sram5_connections[59]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 46.090 796.000 46.370 800.000 ;
+ END
+ END sram5_connections[59]
+ PIN sram5_connections[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 418.690 796.000 418.970 800.000 ;
+ END
+ END sram5_connections[5]
+ PIN sram5_connections[60]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 64.640 4.000 65.240 ;
+ END
+ END sram5_connections[60]
+ PIN sram5_connections[61]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 452.240 500.000 452.840 ;
+ END
+ END sram5_connections[61]
+ PIN sram5_connections[62]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 758.240 4.000 758.840 ;
+ END
+ END sram5_connections[62]
+ PIN sram5_connections[63]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 395.690 796.000 395.970 800.000 ;
+ END
+ END sram5_connections[63]
+ PIN sram5_connections[64]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 125.840 500.000 126.440 ;
+ END
+ END sram5_connections[64]
+ PIN sram5_connections[65]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 331.290 0.000 331.570 4.000 ;
+ END
+ END sram5_connections[65]
+ PIN sram5_connections[66]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 387.640 500.000 388.240 ;
+ END
+ END sram5_connections[66]
+ PIN sram5_connections[67]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 129.240 500.000 129.840 ;
+ END
+ END sram5_connections[67]
+ PIN sram5_connections[68]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 103.590 0.000 103.870 4.000 ;
+ END
+ END sram5_connections[68]
+ PIN sram5_connections[69]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 280.690 0.000 280.970 4.000 ;
+ END
+ END sram5_connections[69]
+ PIN sram5_connections[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 741.240 500.000 741.840 ;
+ END
+ END sram5_connections[6]
+ PIN sram5_connections[70]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 16.190 0.000 16.470 4.000 ;
+ END
+ END sram5_connections[70]
+ PIN sram5_connections[71]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 52.990 0.000 53.270 4.000 ;
+ END
+ END sram5_connections[71]
+ PIN sram5_connections[72]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 340.040 500.000 340.640 ;
+ END
+ END sram5_connections[72]
+ PIN sram5_connections[73]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 345.090 796.000 345.370 800.000 ;
+ END
+ END sram5_connections[73]
+ PIN sram5_connections[74]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 460.090 0.000 460.370 4.000 ;
+ END
+ END sram5_connections[74]
+ PIN sram5_connections[75]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 278.390 796.000 278.670 800.000 ;
+ END
+ END sram5_connections[75]
+ PIN sram5_connections[76]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 792.240 500.000 792.840 ;
+ END
+ END sram5_connections[76]
+ PIN sram5_connections[77]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 513.440 500.000 514.040 ;
+ END
+ END sram5_connections[77]
+ PIN sram5_connections[78]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 285.290 796.000 285.570 800.000 ;
+ END
+ END sram5_connections[78]
+ PIN sram5_connections[79]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 765.040 500.000 765.640 ;
+ END
+ END sram5_connections[79]
+ PIN sram5_connections[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 253.090 796.000 253.370 800.000 ;
+ END
+ END sram5_connections[7]
+ PIN sram5_connections[80]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 115.640 4.000 116.240 ;
+ END
+ END sram5_connections[80]
+ PIN sram5_connections[81]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 181.790 796.000 182.070 800.000 ;
+ END
+ END sram5_connections[81]
+ PIN sram5_connections[82]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 496.890 0.000 497.170 4.000 ;
+ END
+ END sram5_connections[82]
+ PIN sram5_connections[83]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 354.290 0.000 354.570 4.000 ;
+ END
+ END sram5_connections[83]
+ PIN sram5_connections[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 340.040 4.000 340.640 ;
+ END
+ END sram5_connections[8]
+ PIN sram5_connections[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 472.640 4.000 473.240 ;
+ END
+ END sram5_connections[9]
+ PIN sram5_rw_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 278.390 0.000 278.670 4.000 ;
+ END
+ END sram5_rw_in[0]
+ PIN sram5_rw_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 717.440 4.000 718.040 ;
+ END
+ END sram5_rw_in[10]
+ PIN sram5_rw_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 261.840 500.000 262.440 ;
+ END
+ END sram5_rw_in[11]
+ PIN sram5_rw_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 386.490 796.000 386.770 800.000 ;
+ END
+ END sram5_rw_in[12]
+ PIN sram5_rw_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 309.440 4.000 310.040 ;
+ END
+ END sram5_rw_in[13]
+ PIN sram5_rw_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 224.440 4.000 225.040 ;
+ END
+ END sram5_rw_in[14]
+ PIN sram5_rw_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 262.290 0.000 262.570 4.000 ;
+ END
+ END sram5_rw_in[15]
+ PIN sram5_rw_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 75.990 796.000 76.270 800.000 ;
+ END
+ END sram5_rw_in[16]
+ PIN sram5_rw_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 476.040 500.000 476.640 ;
+ END
+ END sram5_rw_in[17]
+ PIN sram5_rw_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 9.290 0.000 9.570 4.000 ;
+ END
+ END sram5_rw_in[18]
+ PIN sram5_rw_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 312.840 500.000 313.440 ;
+ END
+ END sram5_rw_in[19]
+ PIN sram5_rw_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 276.090 0.000 276.370 4.000 ;
+ END
+ END sram5_rw_in[1]
+ PIN sram5_rw_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 487.690 0.000 487.970 4.000 ;
+ END
+ END sram5_rw_in[20]
+ PIN sram5_rw_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 149.640 4.000 150.240 ;
+ END
+ END sram5_rw_in[21]
+ PIN sram5_rw_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 48.390 0.000 48.670 4.000 ;
+ END
+ END sram5_rw_in[22]
+ PIN sram5_rw_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 707.240 4.000 707.840 ;
+ END
+ END sram5_rw_in[23]
+ PIN sram5_rw_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 88.440 4.000 89.040 ;
+ END
+ END sram5_rw_in[24]
+ PIN sram5_rw_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 18.490 796.000 18.770 800.000 ;
+ END
+ END sram5_rw_in[25]
+ PIN sram5_rw_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 656.240 500.000 656.840 ;
+ END
+ END sram5_rw_in[26]
+ PIN sram5_rw_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 142.690 0.000 142.970 4.000 ;
+ END
+ END sram5_rw_in[27]
+ PIN sram5_rw_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 737.840 500.000 738.440 ;
+ END
+ END sram5_rw_in[28]
+ PIN sram5_rw_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 158.790 0.000 159.070 4.000 ;
+ END
+ END sram5_rw_in[29]
+ PIN sram5_rw_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 121.990 796.000 122.270 800.000 ;
+ END
+ END sram5_rw_in[2]
+ PIN sram5_rw_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 391.040 500.000 391.640 ;
+ END
+ END sram5_rw_in[30]
+ PIN sram5_rw_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 656.240 4.000 656.840 ;
+ END
+ END sram5_rw_in[31]
+ PIN sram5_rw_in[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 328.990 796.000 329.270 800.000 ;
+ END
+ END sram5_rw_in[32]
+ PIN sram5_rw_in[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 652.840 4.000 653.440 ;
+ END
+ END sram5_rw_in[33]
+ PIN sram5_rw_in[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 496.890 796.000 497.170 800.000 ;
+ END
+ END sram5_rw_in[34]
+ PIN sram5_rw_in[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 683.440 500.000 684.040 ;
+ END
+ END sram5_rw_in[35]
+ PIN sram5_rw_in[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 129.240 4.000 129.840 ;
+ END
+ END sram5_rw_in[36]
+ PIN sram5_rw_in[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 223.190 0.000 223.470 4.000 ;
+ END
+ END sram5_rw_in[37]
+ PIN sram5_rw_in[38]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 393.390 796.000 393.670 800.000 ;
+ END
+ END sram5_rw_in[38]
+ PIN sram5_rw_in[39]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 374.990 796.000 375.270 800.000 ;
+ END
+ END sram5_rw_in[39]
+ PIN sram5_rw_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 156.490 0.000 156.770 4.000 ;
+ END
+ END sram5_rw_in[3]
+ PIN sram5_rw_in[40]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 292.190 796.000 292.470 800.000 ;
+ END
+ END sram5_rw_in[40]
+ PIN sram5_rw_in[41]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 287.590 796.000 287.870 800.000 ;
+ END
+ END sram5_rw_in[41]
+ PIN sram5_rw_in[42]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 102.040 4.000 102.640 ;
+ END
+ END sram5_rw_in[42]
+ PIN sram5_rw_in[43]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 138.090 796.000 138.370 800.000 ;
+ END
+ END sram5_rw_in[43]
+ PIN sram5_rw_in[44]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 527.040 500.000 527.640 ;
+ END
+ END sram5_rw_in[44]
+ PIN sram5_rw_in[45]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 220.890 0.000 221.170 4.000 ;
+ END
+ END sram5_rw_in[45]
+ PIN sram5_rw_in[46]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 432.490 0.000 432.770 4.000 ;
+ END
+ END sram5_rw_in[46]
+ PIN sram5_rw_in[47]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 207.090 0.000 207.370 4.000 ;
+ END
+ END sram5_rw_in[47]
+ PIN sram5_rw_in[48]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 115.090 796.000 115.370 800.000 ;
+ END
+ END sram5_rw_in[48]
+ PIN sram5_rw_in[49]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 629.040 500.000 629.640 ;
+ END
+ END sram5_rw_in[49]
+ PIN sram5_rw_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 271.490 796.000 271.770 800.000 ;
+ END
+ END sram5_rw_in[4]
+ PIN sram5_rw_in[50]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 748.040 4.000 748.640 ;
+ END
+ END sram5_rw_in[50]
+ PIN sram5_rw_in[51]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 520.240 4.000 520.840 ;
+ END
+ END sram5_rw_in[51]
+ PIN sram5_rw_in[52]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 108.190 796.000 108.470 800.000 ;
+ END
+ END sram5_rw_in[52]
+ PIN sram5_rw_in[53]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 89.790 796.000 90.070 800.000 ;
+ END
+ END sram5_rw_in[53]
+ PIN sram5_rw_in[54]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 92.090 0.000 92.370 4.000 ;
+ END
+ END sram5_rw_in[54]
+ PIN sram5_rw_in[55]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 243.890 0.000 244.170 4.000 ;
+ END
+ END sram5_rw_in[55]
+ PIN sram5_rw_in[56]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 36.890 796.000 37.170 800.000 ;
+ END
+ END sram5_rw_in[56]
+ PIN sram5_rw_in[57]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 173.440 4.000 174.040 ;
+ END
+ END sram5_rw_in[57]
+ PIN sram5_rw_in[58]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 485.390 796.000 485.670 800.000 ;
+ END
+ END sram5_rw_in[58]
+ PIN sram5_rw_in[59]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 540.640 500.000 541.240 ;
+ END
+ END sram5_rw_in[59]
+ PIN sram5_rw_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 530.440 500.000 531.040 ;
+ END
+ END sram5_rw_in[5]
+ PIN sram5_rw_in[60]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 285.290 0.000 285.570 4.000 ;
+ END
+ END sram5_rw_in[60]
+ PIN sram5_rw_in[61]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 27.240 500.000 27.840 ;
+ END
+ END sram5_rw_in[61]
+ PIN sram5_rw_in[62]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 161.090 796.000 161.370 800.000 ;
+ END
+ END sram5_rw_in[62]
+ PIN sram5_rw_in[63]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 61.240 500.000 61.840 ;
+ END
+ END sram5_rw_in[63]
+ PIN sram5_rw_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 472.640 500.000 473.240 ;
+ END
+ END sram5_rw_in[6]
+ PIN sram5_rw_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 285.640 500.000 286.240 ;
+ END
+ END sram5_rw_in[7]
+ PIN sram5_rw_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 427.890 0.000 428.170 4.000 ;
+ END
+ END sram5_rw_in[8]
+ PIN sram5_rw_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 496.000 210.840 500.000 211.440 ;
+ END
+ END sram5_rw_in[9]
PIN vccd1
DIRECTION INOUT ;
USE POWER ;
@@ -6873,204 +6497,193 @@
END vssa2
OBS
LAYER li1 ;
- RECT 5.520 10.795 494.040 788.885 ;
+ RECT 5.520 8.585 494.040 792.455 ;
LAYER met1 ;
- RECT 2.370 7.860 497.190 790.800 ;
+ RECT 2.370 8.200 497.190 792.500 ;
LAYER met2 ;
- RECT 2.400 795.720 4.410 796.125 ;
+ RECT 2.950 795.720 4.410 796.125 ;
RECT 5.250 795.720 6.710 796.125 ;
RECT 7.550 795.720 9.010 796.125 ;
RECT 9.850 795.720 11.310 796.125 ;
RECT 12.150 795.720 13.610 796.125 ;
- RECT 14.450 795.720 15.910 796.125 ;
- RECT 16.750 795.720 18.210 796.125 ;
+ RECT 14.450 795.720 18.210 796.125 ;
RECT 19.050 795.720 20.510 796.125 ;
RECT 21.350 795.720 22.810 796.125 ;
RECT 23.650 795.720 25.110 796.125 ;
RECT 25.950 795.720 27.410 796.125 ;
RECT 28.250 795.720 29.710 796.125 ;
- RECT 30.550 795.720 34.310 796.125 ;
- RECT 35.150 795.720 36.610 796.125 ;
+ RECT 30.550 795.720 32.010 796.125 ;
+ RECT 32.850 795.720 36.610 796.125 ;
RECT 37.450 795.720 38.910 796.125 ;
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- RECT 51.250 795.720 52.710 796.125 ;
- RECT 53.550 795.720 55.010 796.125 ;
+ RECT 51.250 795.720 55.010 796.125 ;
RECT 55.850 795.720 57.310 796.125 ;
RECT 58.150 795.720 59.610 796.125 ;
- RECT 60.450 795.720 64.210 796.125 ;
+ RECT 60.450 795.720 61.910 796.125 ;
+ RECT 62.750 795.720 64.210 796.125 ;
RECT 65.050 795.720 66.510 796.125 ;
- RECT 67.350 795.720 68.810 796.125 ;
- RECT 69.650 795.720 71.110 796.125 ;
+ RECT 67.350 795.720 71.110 796.125 ;
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- RECT 85.750 795.720 87.210 796.125 ;
- RECT 88.050 795.720 89.510 796.125 ;
- RECT 90.350 795.720 94.110 796.125 ;
+ RECT 85.750 795.720 89.510 796.125 ;
+ RECT 90.350 795.720 91.810 796.125 ;
+ RECT 92.650 795.720 94.110 796.125 ;
RECT 94.950 795.720 96.410 796.125 ;
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- RECT 104.150 795.720 105.610 796.125 ;
- RECT 106.450 795.720 107.910 796.125 ;
+ RECT 104.150 795.720 107.910 796.125 ;
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RECT 117.950 795.720 119.410 796.125 ;
- RECT 120.250 795.720 124.010 796.125 ;
- RECT 124.850 795.720 126.310 796.125 ;
+ RECT 120.250 795.720 121.710 796.125 ;
+ RECT 122.550 795.720 126.310 796.125 ;
RECT 127.150 795.720 128.610 796.125 ;
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RECT 136.350 795.720 137.810 796.125 ;
- RECT 138.650 795.720 140.110 796.125 ;
- RECT 140.950 795.720 142.410 796.125 ;
+ RECT 138.650 795.720 142.410 796.125 ;
RECT 143.250 795.720 144.710 796.125 ;
RECT 145.550 795.720 147.010 796.125 ;
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RECT 150.150 795.720 151.610 796.125 ;
- RECT 152.450 795.720 156.210 796.125 ;
- RECT 157.050 795.720 158.510 796.125 ;
- RECT 159.350 795.720 160.810 796.125 ;
+ RECT 152.450 795.720 153.910 796.125 ;
+ RECT 154.750 795.720 156.210 796.125 ;
+ RECT 157.050 795.720 160.810 796.125 ;
RECT 161.650 795.720 163.110 796.125 ;
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- RECT 175.450 795.720 176.910 796.125 ;
- RECT 177.750 795.720 179.210 796.125 ;
+ RECT 175.450 795.720 179.210 796.125 ;
RECT 180.050 795.720 181.510 796.125 ;
- RECT 182.350 795.720 186.110 796.125 ;
+ RECT 182.350 795.720 183.810 796.125 ;
+ RECT 184.650 795.720 186.110 796.125 ;
RECT 186.950 795.720 188.410 796.125 ;
RECT 189.250 795.720 190.710 796.125 ;
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- RECT 193.850 795.720 195.310 796.125 ;
- RECT 196.150 795.720 197.610 796.125 ;
+ RECT 193.850 795.720 197.610 796.125 ;
RECT 198.450 795.720 199.910 796.125 ;
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RECT 207.650 795.720 209.110 796.125 ;
- RECT 209.950 795.720 211.410 796.125 ;
- RECT 212.250 795.720 216.010 796.125 ;
+ RECT 209.950 795.720 213.710 796.125 ;
+ RECT 214.550 795.720 216.010 796.125 ;
RECT 216.850 795.720 218.310 796.125 ;
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- RECT 228.350 795.720 229.810 796.125 ;
- RECT 230.650 795.720 232.110 796.125 ;
+ RECT 228.350 795.720 232.110 796.125 ;
RECT 232.950 795.720 234.410 796.125 ;
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- RECT 242.150 795.720 245.910 796.125 ;
- RECT 246.750 795.720 248.210 796.125 ;
- RECT 249.050 795.720 250.510 796.125 ;
+ RECT 242.150 795.720 243.610 796.125 ;
+ RECT 244.450 795.720 245.910 796.125 ;
+ RECT 246.750 795.720 250.510 796.125 ;
RECT 251.350 795.720 252.810 796.125 ;
RECT 253.650 795.720 255.110 796.125 ;
RECT 255.950 795.720 257.410 796.125 ;
RECT 258.250 795.720 259.710 796.125 ;
RECT 260.550 795.720 262.010 796.125 ;
RECT 262.850 795.720 264.310 796.125 ;
- RECT 265.150 795.720 266.610 796.125 ;
- RECT 267.450 795.720 268.910 796.125 ;
+ RECT 265.150 795.720 268.910 796.125 ;
RECT 269.750 795.720 271.210 796.125 ;
- RECT 272.050 795.720 275.810 796.125 ;
+ RECT 272.050 795.720 273.510 796.125 ;
+ RECT 274.350 795.720 275.810 796.125 ;
RECT 276.650 795.720 278.110 796.125 ;
RECT 278.950 795.720 280.410 796.125 ;
- RECT 281.250 795.720 282.710 796.125 ;
- RECT 283.550 795.720 285.010 796.125 ;
+ RECT 281.250 795.720 285.010 796.125 ;
RECT 285.850 795.720 287.310 796.125 ;
RECT 288.150 795.720 289.610 796.125 ;
RECT 290.450 795.720 291.910 796.125 ;
RECT 292.750 795.720 294.210 796.125 ;
RECT 295.050 795.720 296.510 796.125 ;
RECT 297.350 795.720 298.810 796.125 ;
- RECT 299.650 795.720 301.110 796.125 ;
- RECT 301.950 795.720 305.710 796.125 ;
+ RECT 299.650 795.720 303.410 796.125 ;
+ RECT 304.250 795.720 305.710 796.125 ;
RECT 306.550 795.720 308.010 796.125 ;
RECT 308.850 795.720 310.310 796.125 ;
RECT 311.150 795.720 312.610 796.125 ;
RECT 313.450 795.720 314.910 796.125 ;
RECT 315.750 795.720 317.210 796.125 ;
- RECT 318.050 795.720 319.510 796.125 ;
- RECT 320.350 795.720 321.810 796.125 ;
+ RECT 318.050 795.720 321.810 796.125 ;
RECT 322.650 795.720 324.110 796.125 ;
RECT 324.950 795.720 326.410 796.125 ;
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RECT 329.550 795.720 331.010 796.125 ;
- RECT 331.850 795.720 335.610 796.125 ;
- RECT 336.450 795.720 337.910 796.125 ;
- RECT 338.750 795.720 340.210 796.125 ;
+ RECT 331.850 795.720 333.310 796.125 ;
+ RECT 334.150 795.720 335.610 796.125 ;
+ RECT 336.450 795.720 340.210 796.125 ;
RECT 341.050 795.720 342.510 796.125 ;
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RECT 350.250 795.720 351.710 796.125 ;
- RECT 352.550 795.720 354.010 796.125 ;
- RECT 354.850 795.720 356.310 796.125 ;
+ RECT 352.550 795.720 356.310 796.125 ;
RECT 357.150 795.720 358.610 796.125 ;
RECT 359.450 795.720 360.910 796.125 ;
- RECT 361.750 795.720 365.510 796.125 ;
+ RECT 361.750 795.720 363.210 796.125 ;
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RECT 366.350 795.720 367.810 796.125 ;
RECT 368.650 795.720 370.110 796.125 ;
- RECT 370.950 795.720 372.410 796.125 ;
- RECT 373.250 795.720 374.710 796.125 ;
+ RECT 370.950 795.720 374.710 796.125 ;
RECT 375.550 795.720 377.010 796.125 ;
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RECT 380.150 795.720 381.610 796.125 ;
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- RECT 389.350 795.720 390.810 796.125 ;
- RECT 391.650 795.720 395.410 796.125 ;
+ RECT 389.350 795.720 393.110 796.125 ;
+ RECT 393.950 795.720 395.410 796.125 ;
RECT 396.250 795.720 397.710 796.125 ;
RECT 398.550 795.720 400.010 796.125 ;
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- RECT 407.750 795.720 409.210 796.125 ;
- RECT 410.050 795.720 411.510 796.125 ;
+ RECT 407.750 795.720 411.510 796.125 ;
RECT 412.350 795.720 413.810 796.125 ;
RECT 414.650 795.720 416.110 796.125 ;
RECT 416.950 795.720 418.410 796.125 ;
RECT 419.250 795.720 420.710 796.125 ;
- RECT 421.550 795.720 425.310 796.125 ;
- RECT 426.150 795.720 427.610 796.125 ;
+ RECT 421.550 795.720 423.010 796.125 ;
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RECT 428.450 795.720 429.910 796.125 ;
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RECT 435.350 795.720 436.810 796.125 ;
RECT 437.650 795.720 439.110 796.125 ;
RECT 439.950 795.720 441.410 796.125 ;
- RECT 442.250 795.720 443.710 796.125 ;
- RECT 444.550 795.720 446.010 796.125 ;
+ RECT 442.250 795.720 446.010 796.125 ;
RECT 446.850 795.720 448.310 796.125 ;
RECT 449.150 795.720 450.610 796.125 ;
- RECT 451.450 795.720 455.210 796.125 ;
+ RECT 451.450 795.720 452.910 796.125 ;
+ RECT 453.750 795.720 455.210 796.125 ;
RECT 456.050 795.720 457.510 796.125 ;
RECT 458.350 795.720 459.810 796.125 ;
- RECT 460.650 795.720 462.110 796.125 ;
- RECT 462.950 795.720 464.410 796.125 ;
+ RECT 460.650 795.720 464.410 796.125 ;
RECT 465.250 795.720 466.710 796.125 ;
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RECT 472.150 795.720 473.610 796.125 ;
RECT 474.450 795.720 475.910 796.125 ;
RECT 476.750 795.720 478.210 796.125 ;
- RECT 479.050 795.720 480.510 796.125 ;
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RECT 4.000 449.840 496.000 451.840 ;
- RECT 4.400 448.440 495.600 449.840 ;
+ RECT 4.000 448.440 495.600 449.840 ;
RECT 4.000 446.440 496.000 448.440 ;
- RECT 4.000 445.040 495.600 446.440 ;
+ RECT 4.400 445.040 495.600 446.440 ;
RECT 4.000 443.040 496.000 445.040 ;
RECT 4.400 441.640 495.600 443.040 ;
RECT 4.000 439.640 496.000 441.640 ;
@@ -7493,11 +7095,11 @@
RECT 4.000 432.840 496.000 434.840 ;
RECT 4.400 431.440 495.600 432.840 ;
RECT 4.000 429.440 496.000 431.440 ;
- RECT 4.400 428.040 495.600 429.440 ;
+ RECT 4.400 428.040 496.000 429.440 ;
RECT 4.000 426.040 496.000 428.040 ;
- RECT 4.400 424.640 495.600 426.040 ;
+ RECT 4.000 424.640 495.600 426.040 ;
RECT 4.000 422.640 496.000 424.640 ;
- RECT 4.400 421.240 496.000 422.640 ;
+ RECT 4.400 421.240 495.600 422.640 ;
RECT 4.000 419.240 496.000 421.240 ;
RECT 4.400 417.840 495.600 419.240 ;
RECT 4.000 415.840 496.000 417.840 ;
@@ -7509,9 +7111,9 @@
RECT 4.000 405.640 496.000 407.640 ;
RECT 4.400 404.240 495.600 405.640 ;
RECT 4.000 402.240 496.000 404.240 ;
- RECT 4.000 400.840 495.600 402.240 ;
+ RECT 4.400 400.840 496.000 402.240 ;
RECT 4.000 398.840 496.000 400.840 ;
- RECT 4.400 397.440 495.600 398.840 ;
+ RECT 4.000 397.440 495.600 398.840 ;
RECT 4.000 395.440 496.000 397.440 ;
RECT 4.400 394.040 495.600 395.440 ;
RECT 4.000 392.040 496.000 394.040 ;
@@ -7523,11 +7125,11 @@
RECT 4.000 381.840 496.000 383.840 ;
RECT 4.400 380.440 495.600 381.840 ;
RECT 4.000 378.440 496.000 380.440 ;
- RECT 4.400 377.040 496.000 378.440 ;
+ RECT 4.400 377.040 495.600 378.440 ;
RECT 4.000 375.040 496.000 377.040 ;
- RECT 4.400 373.640 495.600 375.040 ;
+ RECT 4.400 373.640 496.000 375.040 ;
RECT 4.000 371.640 496.000 373.640 ;
- RECT 4.400 370.240 495.600 371.640 ;
+ RECT 4.000 370.240 495.600 371.640 ;
RECT 4.000 368.240 496.000 370.240 ;
RECT 4.400 366.840 495.600 368.240 ;
RECT 4.000 364.840 496.000 366.840 ;
@@ -7535,33 +7137,33 @@
RECT 4.000 361.440 496.000 363.440 ;
RECT 4.400 360.040 495.600 361.440 ;
RECT 4.000 358.040 496.000 360.040 ;
- RECT 4.000 356.640 495.600 358.040 ;
+ RECT 4.400 356.640 495.600 358.040 ;
RECT 4.000 354.640 496.000 356.640 ;
RECT 4.400 353.240 495.600 354.640 ;
RECT 4.000 351.240 496.000 353.240 ;
- RECT 4.400 349.840 495.600 351.240 ;
+ RECT 4.400 349.840 496.000 351.240 ;
RECT 4.000 347.840 496.000 349.840 ;
RECT 4.400 346.440 495.600 347.840 ;
RECT 4.000 344.440 496.000 346.440 ;
- RECT 4.400 343.040 495.600 344.440 ;
+ RECT 4.000 343.040 495.600 344.440 ;
RECT 4.000 341.040 496.000 343.040 ;
RECT 4.400 339.640 495.600 341.040 ;
RECT 4.000 337.640 496.000 339.640 ;
RECT 4.400 336.240 495.600 337.640 ;
RECT 4.000 334.240 496.000 336.240 ;
- RECT 4.400 332.840 496.000 334.240 ;
+ RECT 4.400 332.840 495.600 334.240 ;
RECT 4.000 330.840 496.000 332.840 ;
RECT 4.400 329.440 495.600 330.840 ;
RECT 4.000 327.440 496.000 329.440 ;
RECT 4.400 326.040 495.600 327.440 ;
RECT 4.000 324.040 496.000 326.040 ;
- RECT 4.400 322.640 495.600 324.040 ;
+ RECT 4.400 322.640 496.000 324.040 ;
RECT 4.000 320.640 496.000 322.640 ;
- RECT 4.400 319.240 495.600 320.640 ;
+ RECT 4.000 319.240 495.600 320.640 ;
RECT 4.000 317.240 496.000 319.240 ;
RECT 4.400 315.840 495.600 317.240 ;
RECT 4.000 313.840 496.000 315.840 ;
- RECT 4.000 312.440 495.600 313.840 ;
+ RECT 4.400 312.440 495.600 313.840 ;
RECT 4.000 310.440 496.000 312.440 ;
RECT 4.400 309.040 495.600 310.440 ;
RECT 4.000 307.040 496.000 309.040 ;
@@ -7571,13 +7173,13 @@
RECT 4.000 300.240 496.000 302.240 ;
RECT 4.400 298.840 495.600 300.240 ;
RECT 4.000 296.840 496.000 298.840 ;
- RECT 4.400 295.440 495.600 296.840 ;
+ RECT 4.400 295.440 496.000 296.840 ;
RECT 4.000 293.440 496.000 295.440 ;
- RECT 4.400 292.040 495.600 293.440 ;
+ RECT 4.000 292.040 495.600 293.440 ;
RECT 4.000 290.040 496.000 292.040 ;
RECT 4.400 288.640 495.600 290.040 ;
RECT 4.000 286.640 496.000 288.640 ;
- RECT 4.400 285.240 496.000 286.640 ;
+ RECT 4.400 285.240 495.600 286.640 ;
RECT 4.000 283.240 496.000 285.240 ;
RECT 4.400 281.840 495.600 283.240 ;
RECT 4.000 279.840 496.000 281.840 ;
@@ -7587,9 +7189,9 @@
RECT 4.000 273.040 496.000 275.040 ;
RECT 4.400 271.640 495.600 273.040 ;
RECT 4.000 269.640 496.000 271.640 ;
- RECT 4.000 268.240 495.600 269.640 ;
+ RECT 4.400 268.240 496.000 269.640 ;
RECT 4.000 266.240 496.000 268.240 ;
- RECT 4.400 264.840 495.600 266.240 ;
+ RECT 4.000 264.840 495.600 266.240 ;
RECT 4.000 262.840 496.000 264.840 ;
RECT 4.400 261.440 495.600 262.840 ;
RECT 4.000 259.440 496.000 261.440 ;
@@ -7601,11 +7203,11 @@
RECT 4.000 249.240 496.000 251.240 ;
RECT 4.400 247.840 495.600 249.240 ;
RECT 4.000 245.840 496.000 247.840 ;
- RECT 4.400 244.440 495.600 245.840 ;
+ RECT 4.400 244.440 496.000 245.840 ;
RECT 4.000 242.440 496.000 244.440 ;
- RECT 4.400 241.040 496.000 242.440 ;
+ RECT 4.400 241.040 495.600 242.440 ;
RECT 4.000 239.040 496.000 241.040 ;
- RECT 4.400 237.640 495.600 239.040 ;
+ RECT 4.000 237.640 495.600 239.040 ;
RECT 4.000 235.640 496.000 237.640 ;
RECT 4.400 234.240 495.600 235.640 ;
RECT 4.000 232.240 496.000 234.240 ;
@@ -7613,13 +7215,13 @@
RECT 4.000 228.840 496.000 230.840 ;
RECT 4.400 227.440 495.600 228.840 ;
RECT 4.000 225.440 496.000 227.440 ;
- RECT 4.000 224.040 495.600 225.440 ;
+ RECT 4.400 224.040 495.600 225.440 ;
RECT 4.000 222.040 496.000 224.040 ;
RECT 4.400 220.640 495.600 222.040 ;
RECT 4.000 218.640 496.000 220.640 ;
- RECT 4.400 217.240 495.600 218.640 ;
+ RECT 4.400 217.240 496.000 218.640 ;
RECT 4.000 215.240 496.000 217.240 ;
- RECT 4.400 213.840 495.600 215.240 ;
+ RECT 4.000 213.840 495.600 215.240 ;
RECT 4.000 211.840 496.000 213.840 ;
RECT 4.400 210.440 495.600 211.840 ;
RECT 4.000 208.440 496.000 210.440 ;
@@ -7629,17 +7231,17 @@
RECT 4.000 201.640 496.000 203.640 ;
RECT 4.400 200.240 495.600 201.640 ;
RECT 4.000 198.240 496.000 200.240 ;
- RECT 4.400 196.840 496.000 198.240 ;
+ RECT 4.400 196.840 495.600 198.240 ;
RECT 4.000 194.840 496.000 196.840 ;
RECT 4.400 193.440 495.600 194.840 ;
RECT 4.000 191.440 496.000 193.440 ;
- RECT 4.400 190.040 495.600 191.440 ;
+ RECT 4.400 190.040 496.000 191.440 ;
RECT 4.000 188.040 496.000 190.040 ;
- RECT 4.400 186.640 495.600 188.040 ;
+ RECT 4.000 186.640 495.600 188.040 ;
RECT 4.000 184.640 496.000 186.640 ;
RECT 4.400 183.240 495.600 184.640 ;
RECT 4.000 181.240 496.000 183.240 ;
- RECT 4.000 179.840 495.600 181.240 ;
+ RECT 4.400 179.840 495.600 181.240 ;
RECT 4.000 177.840 496.000 179.840 ;
RECT 4.400 176.440 495.600 177.840 ;
RECT 4.000 174.440 496.000 176.440 ;
@@ -7649,13 +7251,13 @@
RECT 4.000 167.640 496.000 169.640 ;
RECT 4.400 166.240 495.600 167.640 ;
RECT 4.000 164.240 496.000 166.240 ;
- RECT 4.400 162.840 495.600 164.240 ;
+ RECT 4.400 162.840 496.000 164.240 ;
RECT 4.000 160.840 496.000 162.840 ;
- RECT 4.400 159.440 495.600 160.840 ;
+ RECT 4.000 159.440 495.600 160.840 ;
RECT 4.000 157.440 496.000 159.440 ;
RECT 4.400 156.040 495.600 157.440 ;
RECT 4.000 154.040 496.000 156.040 ;
- RECT 4.400 152.640 496.000 154.040 ;
+ RECT 4.400 152.640 495.600 154.040 ;
RECT 4.000 150.640 496.000 152.640 ;
RECT 4.400 149.240 495.600 150.640 ;
RECT 4.000 147.240 496.000 149.240 ;
@@ -7663,11 +7265,11 @@
RECT 4.000 143.840 496.000 145.840 ;
RECT 4.400 142.440 495.600 143.840 ;
RECT 4.000 140.440 496.000 142.440 ;
- RECT 4.400 139.040 495.600 140.440 ;
+ RECT 4.400 139.040 496.000 140.440 ;
RECT 4.000 137.040 496.000 139.040 ;
- RECT 4.000 135.640 495.600 137.040 ;
+ RECT 4.400 135.640 495.600 137.040 ;
RECT 4.000 133.640 496.000 135.640 ;
- RECT 4.400 132.240 495.600 133.640 ;
+ RECT 4.000 132.240 495.600 133.640 ;
RECT 4.000 130.240 496.000 132.240 ;
RECT 4.400 128.840 495.600 130.240 ;
RECT 4.000 126.840 496.000 128.840 ;
@@ -7679,9 +7281,9 @@
RECT 4.000 116.640 496.000 118.640 ;
RECT 4.400 115.240 495.600 116.640 ;
RECT 4.000 113.240 496.000 115.240 ;
- RECT 4.400 111.840 495.600 113.240 ;
+ RECT 4.400 111.840 496.000 113.240 ;
RECT 4.000 109.840 496.000 111.840 ;
- RECT 4.400 108.440 496.000 109.840 ;
+ RECT 4.000 108.440 495.600 109.840 ;
RECT 4.000 106.440 496.000 108.440 ;
RECT 4.400 105.040 495.600 106.440 ;
RECT 4.000 103.040 496.000 105.040 ;
@@ -7691,13 +7293,13 @@
RECT 4.000 96.240 496.000 98.240 ;
RECT 4.400 94.840 495.600 96.240 ;
RECT 4.000 92.840 496.000 94.840 ;
- RECT 4.000 91.440 495.600 92.840 ;
+ RECT 4.400 91.440 495.600 92.840 ;
RECT 4.000 89.440 496.000 91.440 ;
RECT 4.400 88.040 495.600 89.440 ;
RECT 4.000 86.040 496.000 88.040 ;
- RECT 4.400 84.640 495.600 86.040 ;
+ RECT 4.400 84.640 496.000 86.040 ;
RECT 4.000 82.640 496.000 84.640 ;
- RECT 4.400 81.240 495.600 82.640 ;
+ RECT 4.000 81.240 495.600 82.640 ;
RECT 4.000 79.240 496.000 81.240 ;
RECT 4.400 77.840 495.600 79.240 ;
RECT 4.000 75.840 496.000 77.840 ;
@@ -7707,17 +7309,17 @@
RECT 4.000 69.040 496.000 71.040 ;
RECT 4.400 67.640 495.600 69.040 ;
RECT 4.000 65.640 496.000 67.640 ;
- RECT 4.400 64.240 496.000 65.640 ;
+ RECT 4.400 64.240 495.600 65.640 ;
RECT 4.000 62.240 496.000 64.240 ;
RECT 4.400 60.840 495.600 62.240 ;
RECT 4.000 58.840 496.000 60.840 ;
- RECT 4.400 57.440 495.600 58.840 ;
+ RECT 4.400 57.440 496.000 58.840 ;
RECT 4.000 55.440 496.000 57.440 ;
- RECT 4.400 54.040 495.600 55.440 ;
+ RECT 4.000 54.040 495.600 55.440 ;
RECT 4.000 52.040 496.000 54.040 ;
RECT 4.400 50.640 495.600 52.040 ;
RECT 4.000 48.640 496.000 50.640 ;
- RECT 4.000 47.240 495.600 48.640 ;
+ RECT 4.400 47.240 495.600 48.640 ;
RECT 4.000 45.240 496.000 47.240 ;
RECT 4.400 43.840 495.600 45.240 ;
RECT 4.000 41.840 496.000 43.840 ;
@@ -7727,13 +7329,13 @@
RECT 4.000 35.040 496.000 37.040 ;
RECT 4.400 33.640 495.600 35.040 ;
RECT 4.000 31.640 496.000 33.640 ;
- RECT 4.400 30.240 495.600 31.640 ;
+ RECT 4.400 30.240 496.000 31.640 ;
RECT 4.000 28.240 496.000 30.240 ;
- RECT 4.400 26.840 495.600 28.240 ;
+ RECT 4.000 26.840 495.600 28.240 ;
RECT 4.000 24.840 496.000 26.840 ;
RECT 4.400 23.440 495.600 24.840 ;
RECT 4.000 21.440 496.000 23.440 ;
- RECT 4.400 20.040 496.000 21.440 ;
+ RECT 4.400 20.040 495.600 21.440 ;
RECT 4.000 18.040 496.000 20.040 ;
RECT 4.400 16.640 495.600 18.040 ;
RECT 4.000 14.640 496.000 16.640 ;
@@ -7741,11 +7343,19 @@
RECT 4.000 11.240 496.000 13.240 ;
RECT 4.400 9.840 495.600 11.240 ;
RECT 4.000 7.840 496.000 9.840 ;
- RECT 4.400 6.440 495.600 7.840 ;
+ RECT 4.400 6.440 496.000 7.840 ;
RECT 4.000 4.440 496.000 6.440 ;
RECT 4.000 3.575 495.600 4.440 ;
LAYER met4 ;
- RECT 244.095 12.415 244.425 414.625 ;
+ RECT 161.295 12.415 174.240 787.265 ;
+ RECT 176.640 12.415 177.540 787.265 ;
+ RECT 179.940 12.415 180.840 787.265 ;
+ RECT 183.240 12.415 184.140 787.265 ;
+ RECT 186.540 12.415 251.040 787.265 ;
+ RECT 253.440 12.415 254.340 787.265 ;
+ RECT 256.740 12.415 257.640 787.265 ;
+ RECT 260.040 12.415 260.940 787.265 ;
+ RECT 263.340 12.415 313.425 787.265 ;
END
END openram_testchip
END LIBRARY
diff --git a/lef/sky130_sram_1kbyte_1rw1r_8x1024_8.lef b/lef/sky130_sram_1kbyte_1rw1r_8x1024_8.lef
new file mode 100644
index 0000000..16eaf4b
--- /dev/null
+++ b/lef/sky130_sram_1kbyte_1rw1r_8x1024_8.lef
@@ -0,0 +1,529 @@
+VERSION 5.4 ;
+NAMESCASESENSITIVE ON ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+UNITS
+ DATABASE MICRONS 2000 ;
+END UNITS
+MACRO sky130_sram_1kbyte_1rw1r_8x1024_8
+ CLASS BLOCK ;
+ SIZE 451.9 BY 443.06 ;
+ SYMMETRY X Y R90 ;
+ PIN din0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 87.04 0.0 87.42 0.38 ;
+ END
+ END din0[0]
+ PIN din0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 93.16 0.0 93.54 0.38 ;
+ END
+ END din0[1]
+ PIN din0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 98.6 0.0 98.98 0.38 ;
+ END
+ END din0[2]
+ PIN din0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 104.04 0.0 104.42 0.38 ;
+ END
+ END din0[3]
+ PIN din0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 110.16 0.0 110.54 0.38 ;
+ END
+ END din0[4]
+ PIN din0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 115.6 0.0 115.98 0.38 ;
+ END
+ END din0[5]
+ PIN din0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 122.4 0.0 122.78 0.38 ;
+ END
+ END din0[6]
+ PIN din0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 127.16 0.0 127.54 0.38 ;
+ END
+ END din0[7]
+ PIN addr0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 63.24 0.0 63.62 0.38 ;
+ END
+ END addr0[0]
+ PIN addr0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 70.04 0.0 70.42 0.38 ;
+ END
+ END addr0[1]
+ PIN addr0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 75.48 0.0 75.86 0.38 ;
+ END
+ END addr0[2]
+ PIN addr0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 141.44 0.38 141.82 ;
+ END
+ END addr0[3]
+ PIN addr0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 149.6 0.38 149.98 ;
+ END
+ END addr0[4]
+ PIN addr0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 156.4 0.38 156.78 ;
+ END
+ END addr0[5]
+ PIN addr0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 164.56 0.38 164.94 ;
+ END
+ END addr0[6]
+ PIN addr0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 169.32 0.38 169.7 ;
+ END
+ END addr0[7]
+ PIN addr0[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 177.48 0.38 177.86 ;
+ END
+ END addr0[8]
+ PIN addr0[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 183.6 0.38 183.98 ;
+ END
+ END addr0[9]
+ PIN addr1[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 382.16 442.68 382.54 443.06 ;
+ END
+ END addr1[0]
+ PIN addr1[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 376.72 442.68 377.1 443.06 ;
+ END
+ END addr1[1]
+ PIN addr1[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 371.28 442.68 371.66 443.06 ;
+ END
+ END addr1[2]
+ PIN addr1[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 97.24 451.9 97.62 ;
+ END
+ END addr1[3]
+ PIN addr1[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 88.4 451.9 88.78 ;
+ END
+ END addr1[4]
+ PIN addr1[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 82.96 451.9 83.34 ;
+ END
+ END addr1[5]
+ PIN addr1[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 74.12 451.9 74.5 ;
+ END
+ END addr1[6]
+ PIN addr1[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 68.68 451.9 69.06 ;
+ END
+ END addr1[7]
+ PIN addr1[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 59.84 451.9 60.22 ;
+ END
+ END addr1[8]
+ PIN addr1[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 53.72 451.9 54.1 ;
+ END
+ END addr1[9]
+ PIN csb0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 41.48 0.38 41.86 ;
+ END
+ END csb0
+ PIN csb1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 395.76 451.9 396.14 ;
+ END
+ END csb1
+ PIN web0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 49.64 0.38 50.02 ;
+ END
+ END web0
+ PIN clk0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 42.16 0.38 42.54 ;
+ END
+ END clk0
+ PIN clk1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 451.52 395.08 451.9 395.46 ;
+ END
+ END clk1
+ PIN wmask0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 80.92 0.0 81.3 0.38 ;
+ END
+ END wmask0[0]
+ PIN dout0[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 125.12 0.0 125.5 0.38 ;
+ END
+ END dout0[0]
+ PIN dout0[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 150.96 0.0 151.34 0.38 ;
+ END
+ END dout0[1]
+ PIN dout0[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 176.12 0.0 176.5 0.38 ;
+ END
+ END dout0[2]
+ PIN dout0[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 201.28 0.0 201.66 0.38 ;
+ END
+ END dout0[3]
+ PIN dout0[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 226.44 0.0 226.82 0.38 ;
+ END
+ END dout0[4]
+ PIN dout0[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 250.92 0.0 251.3 0.38 ;
+ END
+ END dout0[5]
+ PIN dout0[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 276.08 0.0 276.46 0.38 ;
+ END
+ END dout0[6]
+ PIN dout0[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 301.24 0.0 301.62 0.38 ;
+ END
+ END dout0[7]
+ PIN dout1[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 126.48 442.68 126.86 443.06 ;
+ END
+ END dout1[0]
+ PIN dout1[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 151.64 442.68 152.02 443.06 ;
+ END
+ END dout1[1]
+ PIN dout1[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 176.8 442.68 177.18 443.06 ;
+ END
+ END dout1[2]
+ PIN dout1[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 201.96 442.68 202.34 443.06 ;
+ END
+ END dout1[3]
+ PIN dout1[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 226.44 442.68 226.82 443.06 ;
+ END
+ END dout1[4]
+ PIN dout1[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 250.92 442.68 251.3 443.06 ;
+ END
+ END dout1[5]
+ PIN dout1[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 276.76 442.68 277.14 443.06 ;
+ END
+ END dout1[6]
+ PIN dout1[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 301.92 442.68 302.3 443.06 ;
+ END
+ END dout1[7]
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met4 ;
+ RECT 448.8 1.36 450.54 441.7 ;
+ LAYER met3 ;
+ RECT 1.36 439.96 450.54 441.7 ;
+ LAYER met4 ;
+ RECT 1.36 1.36 3.1 441.7 ;
+ LAYER met3 ;
+ RECT 1.36 1.36 450.54 3.1 ;
+ END
+ END vccd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met3 ;
+ RECT 4.76 4.76 447.14 6.5 ;
+ LAYER met4 ;
+ RECT 4.76 4.76 6.5 438.3 ;
+ LAYER met3 ;
+ RECT 4.76 436.56 447.14 438.3 ;
+ LAYER met4 ;
+ RECT 445.4 4.76 447.14 438.3 ;
+ END
+ END vssd1
+ OBS
+ LAYER met1 ;
+ RECT 0.62 0.62 451.28 442.44 ;
+ LAYER met2 ;
+ RECT 0.62 0.62 451.28 442.44 ;
+ LAYER met3 ;
+ RECT 0.98 140.84 451.28 142.42 ;
+ RECT 0.62 142.42 0.98 149.0 ;
+ RECT 0.62 150.58 0.98 155.8 ;
+ RECT 0.62 157.38 0.98 163.96 ;
+ RECT 0.62 165.54 0.98 168.72 ;
+ RECT 0.62 170.3 0.98 176.88 ;
+ RECT 0.62 178.46 0.98 183.0 ;
+ RECT 0.98 96.64 450.92 98.22 ;
+ RECT 0.98 98.22 450.92 140.84 ;
+ RECT 450.92 98.22 451.28 140.84 ;
+ RECT 450.92 89.38 451.28 96.64 ;
+ RECT 450.92 83.94 451.28 87.8 ;
+ RECT 450.92 75.1 451.28 82.36 ;
+ RECT 450.92 69.66 451.28 73.52 ;
+ RECT 450.92 60.82 451.28 68.08 ;
+ RECT 450.92 54.7 451.28 59.24 ;
+ RECT 0.98 142.42 450.92 395.16 ;
+ RECT 0.98 395.16 450.92 396.74 ;
+ RECT 0.62 50.62 0.98 140.84 ;
+ RECT 0.62 43.14 0.98 49.04 ;
+ RECT 450.92 142.42 451.28 394.48 ;
+ RECT 0.62 184.58 0.76 439.36 ;
+ RECT 0.62 439.36 0.76 442.3 ;
+ RECT 0.62 442.3 0.76 442.44 ;
+ RECT 0.76 184.58 0.98 439.36 ;
+ RECT 0.76 442.3 0.98 442.44 ;
+ RECT 0.98 442.3 450.92 442.44 ;
+ RECT 450.92 396.74 451.14 439.36 ;
+ RECT 450.92 442.3 451.14 442.44 ;
+ RECT 451.14 396.74 451.28 439.36 ;
+ RECT 451.14 439.36 451.28 442.3 ;
+ RECT 451.14 442.3 451.28 442.44 ;
+ RECT 0.98 0.62 450.92 0.76 ;
+ RECT 450.92 0.62 451.14 0.76 ;
+ RECT 450.92 3.7 451.14 53.12 ;
+ RECT 451.14 0.62 451.28 0.76 ;
+ RECT 451.14 0.76 451.28 3.7 ;
+ RECT 451.14 3.7 451.28 53.12 ;
+ RECT 0.62 0.62 0.76 0.76 ;
+ RECT 0.62 0.76 0.76 3.7 ;
+ RECT 0.62 3.7 0.76 40.88 ;
+ RECT 0.76 0.62 0.98 0.76 ;
+ RECT 0.76 3.7 0.98 40.88 ;
+ RECT 0.98 3.7 4.16 4.16 ;
+ RECT 0.98 4.16 4.16 7.1 ;
+ RECT 0.98 7.1 4.16 96.64 ;
+ RECT 4.16 3.7 447.74 4.16 ;
+ RECT 4.16 7.1 447.74 96.64 ;
+ RECT 447.74 3.7 450.92 4.16 ;
+ RECT 447.74 4.16 450.92 7.1 ;
+ RECT 447.74 7.1 450.92 96.64 ;
+ RECT 0.98 396.74 4.16 435.96 ;
+ RECT 0.98 435.96 4.16 438.9 ;
+ RECT 0.98 438.9 4.16 439.36 ;
+ RECT 4.16 396.74 447.74 435.96 ;
+ RECT 4.16 438.9 447.74 439.36 ;
+ RECT 447.74 396.74 450.92 435.96 ;
+ RECT 447.74 435.96 450.92 438.9 ;
+ RECT 447.74 438.9 450.92 439.36 ;
+ LAYER met4 ;
+ RECT 86.44 0.98 88.02 442.44 ;
+ RECT 88.02 0.62 92.56 0.98 ;
+ RECT 94.14 0.62 98.0 0.98 ;
+ RECT 99.58 0.62 103.44 0.98 ;
+ RECT 105.02 0.62 109.56 0.98 ;
+ RECT 111.14 0.62 115.0 0.98 ;
+ RECT 116.58 0.62 121.8 0.98 ;
+ RECT 64.22 0.62 69.44 0.98 ;
+ RECT 71.02 0.62 74.88 0.98 ;
+ RECT 88.02 0.98 381.56 442.08 ;
+ RECT 381.56 0.98 383.14 442.08 ;
+ RECT 377.7 442.08 381.56 442.44 ;
+ RECT 372.26 442.08 376.12 442.44 ;
+ RECT 76.46 0.62 80.32 0.98 ;
+ RECT 81.9 0.62 86.44 0.98 ;
+ RECT 123.38 0.62 124.52 0.98 ;
+ RECT 126.1 0.62 126.56 0.98 ;
+ RECT 128.14 0.62 150.36 0.98 ;
+ RECT 151.94 0.62 175.52 0.98 ;
+ RECT 177.1 0.62 200.68 0.98 ;
+ RECT 202.26 0.62 225.84 0.98 ;
+ RECT 227.42 0.62 250.32 0.98 ;
+ RECT 251.9 0.62 275.48 0.98 ;
+ RECT 277.06 0.62 300.64 0.98 ;
+ RECT 88.02 442.08 125.88 442.44 ;
+ RECT 127.46 442.08 151.04 442.44 ;
+ RECT 152.62 442.08 176.2 442.44 ;
+ RECT 177.78 442.08 201.36 442.44 ;
+ RECT 202.94 442.08 225.84 442.44 ;
+ RECT 227.42 442.08 250.32 442.44 ;
+ RECT 251.9 442.08 276.16 442.44 ;
+ RECT 277.74 442.08 301.32 442.44 ;
+ RECT 302.9 442.08 370.68 442.44 ;
+ RECT 451.14 0.98 451.28 442.08 ;
+ RECT 383.14 442.08 448.2 442.3 ;
+ RECT 383.14 442.3 448.2 442.44 ;
+ RECT 448.2 442.3 451.14 442.44 ;
+ RECT 451.14 442.08 451.28 442.3 ;
+ RECT 451.14 442.3 451.28 442.44 ;
+ RECT 302.22 0.62 448.2 0.76 ;
+ RECT 302.22 0.76 448.2 0.98 ;
+ RECT 448.2 0.62 451.14 0.76 ;
+ RECT 451.14 0.62 451.28 0.76 ;
+ RECT 451.14 0.76 451.28 0.98 ;
+ RECT 0.62 0.98 0.76 442.3 ;
+ RECT 0.62 442.3 0.76 442.44 ;
+ RECT 0.76 442.3 3.7 442.44 ;
+ RECT 3.7 442.3 86.44 442.44 ;
+ RECT 0.62 0.62 0.76 0.76 ;
+ RECT 0.62 0.76 0.76 0.98 ;
+ RECT 0.76 0.62 3.7 0.76 ;
+ RECT 3.7 0.62 62.64 0.76 ;
+ RECT 3.7 0.76 62.64 0.98 ;
+ RECT 3.7 0.98 4.16 4.16 ;
+ RECT 3.7 4.16 4.16 438.9 ;
+ RECT 3.7 438.9 4.16 442.3 ;
+ RECT 4.16 0.98 7.1 4.16 ;
+ RECT 4.16 438.9 7.1 442.3 ;
+ RECT 7.1 0.98 86.44 4.16 ;
+ RECT 7.1 4.16 86.44 438.9 ;
+ RECT 7.1 438.9 86.44 442.3 ;
+ RECT 383.14 0.98 444.8 4.16 ;
+ RECT 383.14 4.16 444.8 438.9 ;
+ RECT 383.14 438.9 444.8 442.08 ;
+ RECT 444.8 0.98 447.74 4.16 ;
+ RECT 444.8 438.9 447.74 442.08 ;
+ RECT 447.74 0.98 448.2 4.16 ;
+ RECT 447.74 4.16 448.2 438.9 ;
+ RECT 447.74 438.9 448.2 442.08 ;
+ END
+END sky130_sram_1kbyte_1rw1r_8x1024_8
+END LIBRARY
diff --git a/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef b/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef
new file mode 100644
index 0000000..e66b47e
--- /dev/null
+++ b/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef
@@ -0,0 +1,1108 @@
+VERSION 5.4 ;
+NAMESCASESENSITIVE ON ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+UNITS
+ DATABASE MICRONS 2000 ;
+END UNITS
+MACRO sky130_sram_2kbyte_1rw1r_32x512_8
+ CLASS BLOCK ;
+ SIZE 679.02 BY 413.14 ;
+ SYMMETRY X Y R90 ;
+ PIN din0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 113.56 0.0 113.94 0.38 ;
+ END
+ END din0[0]
+ PIN din0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 119.0 0.0 119.38 0.38 ;
+ END
+ END din0[1]
+ PIN din0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 125.12 0.0 125.5 0.38 ;
+ END
+ END din0[2]
+ PIN din0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 130.56 0.0 130.94 0.38 ;
+ END
+ END din0[3]
+ PIN din0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 136.0 0.0 136.38 0.38 ;
+ END
+ END din0[4]
+ PIN din0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 141.44 0.0 141.82 0.38 ;
+ END
+ END din0[5]
+ PIN din0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 148.24 0.0 148.62 0.38 ;
+ END
+ END din0[6]
+ PIN din0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 154.36 0.0 154.74 0.38 ;
+ END
+ END din0[7]
+ PIN din0[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 159.8 0.0 160.18 0.38 ;
+ END
+ END din0[8]
+ PIN din0[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 165.24 0.0 165.62 0.38 ;
+ END
+ END din0[9]
+ PIN din0[10]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 170.68 0.0 171.06 0.38 ;
+ END
+ END din0[10]
+ PIN din0[11]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 177.48 0.0 177.86 0.38 ;
+ END
+ END din0[11]
+ PIN din0[12]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 182.92 0.0 183.3 0.38 ;
+ END
+ END din0[12]
+ PIN din0[13]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 188.36 0.0 188.74 0.38 ;
+ END
+ END din0[13]
+ PIN din0[14]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 195.16 0.0 195.54 0.38 ;
+ END
+ END din0[14]
+ PIN din0[15]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 201.28 0.0 201.66 0.38 ;
+ END
+ END din0[15]
+ PIN din0[16]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 206.72 0.0 207.1 0.38 ;
+ END
+ END din0[16]
+ PIN din0[17]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 212.16 0.0 212.54 0.38 ;
+ END
+ END din0[17]
+ PIN din0[18]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 217.6 0.0 217.98 0.38 ;
+ END
+ END din0[18]
+ PIN din0[19]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 224.4 0.0 224.78 0.38 ;
+ END
+ END din0[19]
+ PIN din0[20]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 229.84 0.0 230.22 0.38 ;
+ END
+ END din0[20]
+ PIN din0[21]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 235.96 0.0 236.34 0.38 ;
+ END
+ END din0[21]
+ PIN din0[22]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 241.4 0.0 241.78 0.38 ;
+ END
+ END din0[22]
+ PIN din0[23]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 246.84 0.0 247.22 0.38 ;
+ END
+ END din0[23]
+ PIN din0[24]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 253.64 0.0 254.02 0.38 ;
+ END
+ END din0[24]
+ PIN din0[25]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 259.08 0.0 259.46 0.38 ;
+ END
+ END din0[25]
+ PIN din0[26]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 264.52 0.0 264.9 0.38 ;
+ END
+ END din0[26]
+ PIN din0[27]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 269.96 0.0 270.34 0.38 ;
+ END
+ END din0[27]
+ PIN din0[28]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 276.76 0.0 277.14 0.38 ;
+ END
+ END din0[28]
+ PIN din0[29]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 282.88 0.0 283.26 0.38 ;
+ END
+ END din0[29]
+ PIN din0[30]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 288.32 0.0 288.7 0.38 ;
+ END
+ END din0[30]
+ PIN din0[31]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 293.76 0.0 294.14 0.38 ;
+ END
+ END din0[31]
+ PIN addr0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 78.2 0.0 78.58 0.38 ;
+ END
+ END addr0[0]
+ PIN addr0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 83.64 0.0 84.02 0.38 ;
+ END
+ END addr0[1]
+ PIN addr0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 139.4 0.38 139.78 ;
+ END
+ END addr0[2]
+ PIN addr0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 148.24 0.38 148.62 ;
+ END
+ END addr0[3]
+ PIN addr0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 154.36 0.38 154.74 ;
+ END
+ END addr0[4]
+ PIN addr0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 162.52 0.38 162.9 ;
+ END
+ END addr0[5]
+ PIN addr0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 167.96 0.38 168.34 ;
+ END
+ END addr0[6]
+ PIN addr0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 177.48 0.38 177.86 ;
+ END
+ END addr0[7]
+ PIN addr0[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 182.92 0.38 183.3 ;
+ END
+ END addr0[8]
+ PIN addr1[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 596.36 412.76 596.74 413.14 ;
+ END
+ END addr1[0]
+ PIN addr1[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 590.24 412.76 590.62 413.14 ;
+ END
+ END addr1[1]
+ PIN addr1[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 678.64 95.2 679.02 95.58 ;
+ END
+ END addr1[2]
+ PIN addr1[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 678.64 87.04 679.02 87.42 ;
+ END
+ END addr1[3]
+ PIN addr1[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 678.64 80.24 679.02 80.62 ;
+ END
+ END addr1[4]
+ PIN addr1[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 678.64 72.76 679.02 73.14 ;
+ END
+ END addr1[5]
+ PIN addr1[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 678.64 66.64 679.02 67.02 ;
+ END
+ END addr1[6]
+ PIN addr1[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 614.04 0.0 614.42 0.38 ;
+ END
+ END addr1[7]
+ PIN addr1[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 614.72 0.0 615.1 0.38 ;
+ END
+ END addr1[8]
+ PIN csb0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 38.76 0.38 39.14 ;
+ END
+ END csb0
+ PIN csb1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 678.64 394.4 679.02 394.78 ;
+ END
+ END csb1
+ PIN web0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 48.28 0.38 48.66 ;
+ END
+ END web0
+ PIN clk0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 40.12 0.38 40.5 ;
+ END
+ END clk0
+ PIN clk1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 652.12 412.76 652.5 413.14 ;
+ END
+ END clk1
+ PIN wmask0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 89.08 0.0 89.46 0.38 ;
+ END
+ END wmask0[0]
+ PIN wmask0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 95.88 0.0 96.26 0.38 ;
+ END
+ END wmask0[1]
+ PIN wmask0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 100.64 0.0 101.02 0.38 ;
+ END
+ END wmask0[2]
+ PIN wmask0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 106.76 0.0 107.14 0.38 ;
+ END
+ END wmask0[3]
+ PIN dout0[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 139.4 0.0 139.78 0.38 ;
+ END
+ END dout0[0]
+ PIN dout0[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 151.64 0.0 152.02 0.38 ;
+ END
+ END dout0[1]
+ PIN dout0[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 165.92 0.0 166.3 0.38 ;
+ END
+ END dout0[2]
+ PIN dout0[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 178.16 0.0 178.54 0.38 ;
+ END
+ END dout0[3]
+ PIN dout0[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 190.4 0.0 190.78 0.38 ;
+ END
+ END dout0[4]
+ PIN dout0[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 203.32 0.0 203.7 0.38 ;
+ END
+ END dout0[5]
+ PIN dout0[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 215.56 0.0 215.94 0.38 ;
+ END
+ END dout0[6]
+ PIN dout0[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 227.8 0.0 228.18 0.38 ;
+ END
+ END dout0[7]
+ PIN dout0[8]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 239.36 0.0 239.74 0.38 ;
+ END
+ END dout0[8]
+ PIN dout0[9]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 252.96 0.0 253.34 0.38 ;
+ END
+ END dout0[9]
+ PIN dout0[10]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 265.88 0.0 266.26 0.38 ;
+ END
+ END dout0[10]
+ PIN dout0[11]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 278.12 0.0 278.5 0.38 ;
+ END
+ END dout0[11]
+ PIN dout0[12]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 290.36 0.0 290.74 0.38 ;
+ END
+ END dout0[12]
+ PIN dout0[13]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 302.6 0.0 302.98 0.38 ;
+ END
+ END dout0[13]
+ PIN dout0[14]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 315.52 0.0 315.9 0.38 ;
+ END
+ END dout0[14]
+ PIN dout0[15]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 327.76 0.0 328.14 0.38 ;
+ END
+ END dout0[15]
+ PIN dout0[16]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 339.32 0.0 339.7 0.38 ;
+ END
+ END dout0[16]
+ PIN dout0[17]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 352.92 0.0 353.3 0.38 ;
+ END
+ END dout0[17]
+ PIN dout0[18]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 365.16 0.0 365.54 0.38 ;
+ END
+ END dout0[18]
+ PIN dout0[19]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 377.4 0.0 377.78 0.38 ;
+ END
+ END dout0[19]
+ PIN dout0[20]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 390.32 0.0 390.7 0.38 ;
+ END
+ END dout0[20]
+ PIN dout0[21]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 402.56 0.0 402.94 0.38 ;
+ END
+ END dout0[21]
+ PIN dout0[22]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 415.48 0.0 415.86 0.38 ;
+ END
+ END dout0[22]
+ PIN dout0[23]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 427.72 0.0 428.1 0.38 ;
+ END
+ END dout0[23]
+ PIN dout0[24]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 440.64 0.0 441.02 0.38 ;
+ END
+ END dout0[24]
+ PIN dout0[25]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 452.88 0.0 453.26 0.38 ;
+ END
+ END dout0[25]
+ PIN dout0[26]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 465.12 0.0 465.5 0.38 ;
+ END
+ END dout0[26]
+ PIN dout0[27]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 477.36 0.0 477.74 0.38 ;
+ END
+ END dout0[27]
+ PIN dout0[28]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 490.28 0.0 490.66 0.38 ;
+ END
+ END dout0[28]
+ PIN dout0[29]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 502.52 0.0 502.9 0.38 ;
+ END
+ END dout0[29]
+ PIN dout0[30]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 514.76 0.0 515.14 0.38 ;
+ END
+ END dout0[30]
+ PIN dout0[31]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 527.68 0.0 528.06 0.38 ;
+ END
+ END dout0[31]
+ PIN dout1[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 141.44 412.76 141.82 413.14 ;
+ END
+ END dout1[0]
+ PIN dout1[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 153.0 412.76 153.38 413.14 ;
+ END
+ END dout1[1]
+ PIN dout1[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 165.24 412.76 165.62 413.14 ;
+ END
+ END dout1[2]
+ PIN dout1[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 178.84 412.76 179.22 413.14 ;
+ END
+ END dout1[3]
+ PIN dout1[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 190.4 412.76 190.78 413.14 ;
+ END
+ END dout1[4]
+ PIN dout1[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 203.32 412.76 203.7 413.14 ;
+ END
+ END dout1[5]
+ PIN dout1[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 215.56 412.76 215.94 413.14 ;
+ END
+ END dout1[6]
+ PIN dout1[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 228.48 412.76 228.86 413.14 ;
+ END
+ END dout1[7]
+ PIN dout1[8]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 240.72 412.76 241.1 413.14 ;
+ END
+ END dout1[8]
+ PIN dout1[9]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 253.64 412.76 254.02 413.14 ;
+ END
+ END dout1[9]
+ PIN dout1[10]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 265.88 412.76 266.26 413.14 ;
+ END
+ END dout1[10]
+ PIN dout1[11]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 278.8 412.76 279.18 413.14 ;
+ END
+ END dout1[11]
+ PIN dout1[12]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 290.36 412.76 290.74 413.14 ;
+ END
+ END dout1[12]
+ PIN dout1[13]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 302.6 412.76 302.98 413.14 ;
+ END
+ END dout1[13]
+ PIN dout1[14]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 316.2 412.76 316.58 413.14 ;
+ END
+ END dout1[14]
+ PIN dout1[15]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 328.44 412.76 328.82 413.14 ;
+ END
+ END dout1[15]
+ PIN dout1[16]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 340.68 412.76 341.06 413.14 ;
+ END
+ END dout1[16]
+ PIN dout1[17]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 352.92 412.76 353.3 413.14 ;
+ END
+ END dout1[17]
+ PIN dout1[18]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 365.84 412.76 366.22 413.14 ;
+ END
+ END dout1[18]
+ PIN dout1[19]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 377.4 412.76 377.78 413.14 ;
+ END
+ END dout1[19]
+ PIN dout1[20]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 391.0 412.76 391.38 413.14 ;
+ END
+ END dout1[20]
+ PIN dout1[21]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 403.24 412.76 403.62 413.14 ;
+ END
+ END dout1[21]
+ PIN dout1[22]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 415.48 412.76 415.86 413.14 ;
+ END
+ END dout1[22]
+ PIN dout1[23]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 427.72 412.76 428.1 413.14 ;
+ END
+ END dout1[23]
+ PIN dout1[24]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 439.96 412.76 440.34 413.14 ;
+ END
+ END dout1[24]
+ PIN dout1[25]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 452.88 412.76 453.26 413.14 ;
+ END
+ END dout1[25]
+ PIN dout1[26]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 465.8 412.76 466.18 413.14 ;
+ END
+ END dout1[26]
+ PIN dout1[27]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 478.04 412.76 478.42 413.14 ;
+ END
+ END dout1[27]
+ PIN dout1[28]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 490.28 412.76 490.66 413.14 ;
+ END
+ END dout1[28]
+ PIN dout1[29]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 503.2 412.76 503.58 413.14 ;
+ END
+ END dout1[29]
+ PIN dout1[30]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 514.76 412.76 515.14 413.14 ;
+ END
+ END dout1[30]
+ PIN dout1[31]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 528.36 412.76 528.74 413.14 ;
+ END
+ END dout1[31]
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met3 ;
+ RECT 1.36 1.36 677.66 3.1 ;
+ LAYER met4 ;
+ RECT 675.92 1.36 677.66 411.78 ;
+ LAYER met4 ;
+ RECT 1.36 1.36 3.1 411.78 ;
+ LAYER met3 ;
+ RECT 1.36 410.04 677.66 411.78 ;
+ END
+ END vccd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met3 ;
+ RECT 4.76 4.76 674.26 6.5 ;
+ LAYER met4 ;
+ RECT 4.76 4.76 6.5 408.38 ;
+ LAYER met3 ;
+ RECT 4.76 406.64 674.26 408.38 ;
+ LAYER met4 ;
+ RECT 672.52 4.76 674.26 408.38 ;
+ END
+ END vssd1
+ OBS
+ LAYER met1 ;
+ RECT 0.62 0.62 678.4 412.52 ;
+ LAYER met2 ;
+ RECT 0.62 0.62 678.4 412.52 ;
+ LAYER met3 ;
+ RECT 0.98 138.8 678.4 140.38 ;
+ RECT 0.62 140.38 0.98 147.64 ;
+ RECT 0.62 149.22 0.98 153.76 ;
+ RECT 0.62 155.34 0.98 161.92 ;
+ RECT 0.62 163.5 0.98 167.36 ;
+ RECT 0.62 168.94 0.98 176.88 ;
+ RECT 0.62 178.46 0.98 182.32 ;
+ RECT 0.98 94.6 678.04 96.18 ;
+ RECT 0.98 96.18 678.04 138.8 ;
+ RECT 678.04 96.18 678.4 138.8 ;
+ RECT 678.04 88.02 678.4 94.6 ;
+ RECT 678.04 81.22 678.4 86.44 ;
+ RECT 678.04 73.74 678.4 79.64 ;
+ RECT 678.04 67.62 678.4 72.16 ;
+ RECT 0.98 140.38 678.04 393.8 ;
+ RECT 0.98 393.8 678.04 395.38 ;
+ RECT 678.04 140.38 678.4 393.8 ;
+ RECT 0.62 49.26 0.98 138.8 ;
+ RECT 0.62 41.1 0.98 47.68 ;
+ RECT 0.98 0.62 678.04 0.76 ;
+ RECT 678.04 0.62 678.26 0.76 ;
+ RECT 678.04 3.7 678.26 66.04 ;
+ RECT 678.26 0.62 678.4 0.76 ;
+ RECT 678.26 0.76 678.4 3.7 ;
+ RECT 678.26 3.7 678.4 66.04 ;
+ RECT 0.62 0.62 0.76 0.76 ;
+ RECT 0.62 0.76 0.76 3.7 ;
+ RECT 0.62 3.7 0.76 38.16 ;
+ RECT 0.76 0.62 0.98 0.76 ;
+ RECT 0.76 3.7 0.98 38.16 ;
+ RECT 0.62 183.9 0.76 409.44 ;
+ RECT 0.62 409.44 0.76 412.38 ;
+ RECT 0.62 412.38 0.76 412.52 ;
+ RECT 0.76 183.9 0.98 409.44 ;
+ RECT 0.76 412.38 0.98 412.52 ;
+ RECT 0.98 412.38 678.04 412.52 ;
+ RECT 678.04 395.38 678.26 409.44 ;
+ RECT 678.04 412.38 678.26 412.52 ;
+ RECT 678.26 395.38 678.4 409.44 ;
+ RECT 678.26 409.44 678.4 412.38 ;
+ RECT 678.26 412.38 678.4 412.52 ;
+ RECT 0.98 3.7 4.16 4.16 ;
+ RECT 0.98 4.16 4.16 7.1 ;
+ RECT 0.98 7.1 4.16 94.6 ;
+ RECT 4.16 3.7 674.86 4.16 ;
+ RECT 4.16 7.1 674.86 94.6 ;
+ RECT 674.86 3.7 678.04 4.16 ;
+ RECT 674.86 4.16 678.04 7.1 ;
+ RECT 674.86 7.1 678.04 94.6 ;
+ RECT 0.98 395.38 4.16 406.04 ;
+ RECT 0.98 406.04 4.16 408.98 ;
+ RECT 0.98 408.98 4.16 409.44 ;
+ RECT 4.16 395.38 674.86 406.04 ;
+ RECT 4.16 408.98 674.86 409.44 ;
+ RECT 674.86 395.38 678.04 406.04 ;
+ RECT 674.86 406.04 678.04 408.98 ;
+ RECT 674.86 408.98 678.04 409.44 ;
+ LAYER met4 ;
+ RECT 112.96 0.98 114.54 412.52 ;
+ RECT 114.54 0.62 118.4 0.98 ;
+ RECT 119.98 0.62 124.52 0.98 ;
+ RECT 126.1 0.62 129.96 0.98 ;
+ RECT 131.54 0.62 135.4 0.98 ;
+ RECT 142.42 0.62 147.64 0.98 ;
+ RECT 155.34 0.62 159.2 0.98 ;
+ RECT 160.78 0.62 164.64 0.98 ;
+ RECT 171.66 0.62 176.88 0.98 ;
+ RECT 183.9 0.62 187.76 0.98 ;
+ RECT 196.14 0.62 200.68 0.98 ;
+ RECT 207.7 0.62 211.56 0.98 ;
+ RECT 218.58 0.62 223.8 0.98 ;
+ RECT 230.82 0.62 235.36 0.98 ;
+ RECT 242.38 0.62 246.24 0.98 ;
+ RECT 254.62 0.62 258.48 0.98 ;
+ RECT 260.06 0.62 263.92 0.98 ;
+ RECT 270.94 0.62 276.16 0.98 ;
+ RECT 283.86 0.62 287.72 0.98 ;
+ RECT 79.18 0.62 83.04 0.98 ;
+ RECT 114.54 0.98 595.76 412.16 ;
+ RECT 595.76 0.98 597.34 412.16 ;
+ RECT 591.22 412.16 595.76 412.52 ;
+ RECT 597.34 412.16 651.52 412.52 ;
+ RECT 84.62 0.62 88.48 0.98 ;
+ RECT 90.06 0.62 95.28 0.98 ;
+ RECT 96.86 0.62 100.04 0.98 ;
+ RECT 101.62 0.62 106.16 0.98 ;
+ RECT 107.74 0.62 112.96 0.98 ;
+ RECT 136.98 0.62 138.8 0.98 ;
+ RECT 140.38 0.62 140.84 0.98 ;
+ RECT 149.22 0.62 151.04 0.98 ;
+ RECT 152.62 0.62 153.76 0.98 ;
+ RECT 166.9 0.62 170.08 0.98 ;
+ RECT 179.14 0.62 182.32 0.98 ;
+ RECT 189.34 0.62 189.8 0.98 ;
+ RECT 191.38 0.62 194.56 0.98 ;
+ RECT 202.26 0.62 202.72 0.98 ;
+ RECT 204.3 0.62 206.12 0.98 ;
+ RECT 213.14 0.62 214.96 0.98 ;
+ RECT 216.54 0.62 217.0 0.98 ;
+ RECT 225.38 0.62 227.2 0.98 ;
+ RECT 228.78 0.62 229.24 0.98 ;
+ RECT 236.94 0.62 238.76 0.98 ;
+ RECT 240.34 0.62 240.8 0.98 ;
+ RECT 247.82 0.62 252.36 0.98 ;
+ RECT 266.86 0.62 269.36 0.98 ;
+ RECT 279.1 0.62 282.28 0.98 ;
+ RECT 289.3 0.62 289.76 0.98 ;
+ RECT 291.34 0.62 293.16 0.98 ;
+ RECT 294.74 0.62 302.0 0.98 ;
+ RECT 303.58 0.62 314.92 0.98 ;
+ RECT 316.5 0.62 327.16 0.98 ;
+ RECT 328.74 0.62 338.72 0.98 ;
+ RECT 340.3 0.62 352.32 0.98 ;
+ RECT 353.9 0.62 364.56 0.98 ;
+ RECT 366.14 0.62 376.8 0.98 ;
+ RECT 378.38 0.62 389.72 0.98 ;
+ RECT 391.3 0.62 401.96 0.98 ;
+ RECT 403.54 0.62 414.88 0.98 ;
+ RECT 416.46 0.62 427.12 0.98 ;
+ RECT 428.7 0.62 440.04 0.98 ;
+ RECT 441.62 0.62 452.28 0.98 ;
+ RECT 453.86 0.62 464.52 0.98 ;
+ RECT 466.1 0.62 476.76 0.98 ;
+ RECT 478.34 0.62 489.68 0.98 ;
+ RECT 491.26 0.62 501.92 0.98 ;
+ RECT 503.5 0.62 514.16 0.98 ;
+ RECT 515.74 0.62 527.08 0.98 ;
+ RECT 528.66 0.62 613.44 0.98 ;
+ RECT 114.54 412.16 140.84 412.52 ;
+ RECT 142.42 412.16 152.4 412.52 ;
+ RECT 153.98 412.16 164.64 412.52 ;
+ RECT 166.22 412.16 178.24 412.52 ;
+ RECT 179.82 412.16 189.8 412.52 ;
+ RECT 191.38 412.16 202.72 412.52 ;
+ RECT 204.3 412.16 214.96 412.52 ;
+ RECT 216.54 412.16 227.88 412.52 ;
+ RECT 229.46 412.16 240.12 412.52 ;
+ RECT 241.7 412.16 253.04 412.52 ;
+ RECT 254.62 412.16 265.28 412.52 ;
+ RECT 266.86 412.16 278.2 412.52 ;
+ RECT 279.78 412.16 289.76 412.52 ;
+ RECT 291.34 412.16 302.0 412.52 ;
+ RECT 303.58 412.16 315.6 412.52 ;
+ RECT 317.18 412.16 327.84 412.52 ;
+ RECT 329.42 412.16 340.08 412.52 ;
+ RECT 341.66 412.16 352.32 412.52 ;
+ RECT 353.9 412.16 365.24 412.52 ;
+ RECT 366.82 412.16 376.8 412.52 ;
+ RECT 378.38 412.16 390.4 412.52 ;
+ RECT 391.98 412.16 402.64 412.52 ;
+ RECT 404.22 412.16 414.88 412.52 ;
+ RECT 416.46 412.16 427.12 412.52 ;
+ RECT 428.7 412.16 439.36 412.52 ;
+ RECT 440.94 412.16 452.28 412.52 ;
+ RECT 453.86 412.16 465.2 412.52 ;
+ RECT 466.78 412.16 477.44 412.52 ;
+ RECT 479.02 412.16 489.68 412.52 ;
+ RECT 491.26 412.16 502.6 412.52 ;
+ RECT 504.18 412.16 514.16 412.52 ;
+ RECT 515.74 412.16 527.76 412.52 ;
+ RECT 529.34 412.16 589.64 412.52 ;
+ RECT 678.26 0.98 678.4 412.16 ;
+ RECT 615.7 0.62 675.32 0.76 ;
+ RECT 615.7 0.76 675.32 0.98 ;
+ RECT 675.32 0.62 678.26 0.76 ;
+ RECT 678.26 0.62 678.4 0.76 ;
+ RECT 678.26 0.76 678.4 0.98 ;
+ RECT 653.1 412.16 675.32 412.38 ;
+ RECT 653.1 412.38 675.32 412.52 ;
+ RECT 675.32 412.38 678.26 412.52 ;
+ RECT 678.26 412.16 678.4 412.38 ;
+ RECT 678.26 412.38 678.4 412.52 ;
+ RECT 0.62 0.98 0.76 412.38 ;
+ RECT 0.62 412.38 0.76 412.52 ;
+ RECT 0.76 412.38 3.7 412.52 ;
+ RECT 3.7 412.38 112.96 412.52 ;
+ RECT 0.62 0.62 0.76 0.76 ;
+ RECT 0.62 0.76 0.76 0.98 ;
+ RECT 0.76 0.62 3.7 0.76 ;
+ RECT 3.7 0.62 77.6 0.76 ;
+ RECT 3.7 0.76 77.6 0.98 ;
+ RECT 3.7 0.98 4.16 4.16 ;
+ RECT 3.7 4.16 4.16 408.98 ;
+ RECT 3.7 408.98 4.16 412.38 ;
+ RECT 4.16 0.98 7.1 4.16 ;
+ RECT 4.16 408.98 7.1 412.38 ;
+ RECT 7.1 0.98 112.96 4.16 ;
+ RECT 7.1 4.16 112.96 408.98 ;
+ RECT 7.1 408.98 112.96 412.38 ;
+ RECT 597.34 0.98 671.92 4.16 ;
+ RECT 597.34 4.16 671.92 408.98 ;
+ RECT 597.34 408.98 671.92 412.16 ;
+ RECT 671.92 0.98 674.86 4.16 ;
+ RECT 671.92 408.98 674.86 412.16 ;
+ RECT 674.86 0.98 675.32 4.16 ;
+ RECT 674.86 4.16 675.32 408.98 ;
+ RECT 674.86 408.98 675.32 412.16 ;
+ END
+END sky130_sram_2kbyte_1rw1r_32x512_8
+END LIBRARY
diff --git a/lef/sky130_sram_4kbyte_1rw1r_32x1024_8.lef b/lef/sky130_sram_4kbyte_1rw1r_32x1024_8.lef
new file mode 100644
index 0000000..508b91e
--- /dev/null
+++ b/lef/sky130_sram_4kbyte_1rw1r_32x1024_8.lef
@@ -0,0 +1,1123 @@
+VERSION 5.4 ;
+NAMESCASESENSITIVE ON ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+UNITS
+ DATABASE MICRONS 2000 ;
+END UNITS
+MACRO sky130_sram_4kbyte_1rw1r_32x1024_8
+ CLASS BLOCK ;
+ SIZE 689.9 BY 666.1 ;
+ SYMMETRY X Y R90 ;
+ PIN din0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 116.28 0.0 116.66 0.38 ;
+ END
+ END din0[0]
+ PIN din0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 121.72 0.0 122.1 0.38 ;
+ END
+ END din0[1]
+ PIN din0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 127.84 0.0 128.22 0.38 ;
+ END
+ END din0[2]
+ PIN din0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 133.28 0.0 133.66 0.38 ;
+ END
+ END din0[3]
+ PIN din0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 138.72 0.0 139.1 0.38 ;
+ END
+ END din0[4]
+ PIN din0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 144.16 0.0 144.54 0.38 ;
+ END
+ END din0[5]
+ PIN din0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 150.96 0.0 151.34 0.38 ;
+ END
+ END din0[6]
+ PIN din0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 157.08 0.0 157.46 0.38 ;
+ END
+ END din0[7]
+ PIN din0[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 162.52 0.0 162.9 0.38 ;
+ END
+ END din0[8]
+ PIN din0[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 167.96 0.0 168.34 0.38 ;
+ END
+ END din0[9]
+ PIN din0[10]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 173.4 0.0 173.78 0.38 ;
+ END
+ END din0[10]
+ PIN din0[11]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 180.2 0.0 180.58 0.38 ;
+ END
+ END din0[11]
+ PIN din0[12]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 185.64 0.0 186.02 0.38 ;
+ END
+ END din0[12]
+ PIN din0[13]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 191.08 0.0 191.46 0.38 ;
+ END
+ END din0[13]
+ PIN din0[14]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 197.88 0.0 198.26 0.38 ;
+ END
+ END din0[14]
+ PIN din0[15]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 204.0 0.0 204.38 0.38 ;
+ END
+ END din0[15]
+ PIN din0[16]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 209.44 0.0 209.82 0.38 ;
+ END
+ END din0[16]
+ PIN din0[17]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 214.88 0.0 215.26 0.38 ;
+ END
+ END din0[17]
+ PIN din0[18]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 220.32 0.0 220.7 0.38 ;
+ END
+ END din0[18]
+ PIN din0[19]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 227.12 0.0 227.5 0.38 ;
+ END
+ END din0[19]
+ PIN din0[20]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 232.56 0.0 232.94 0.38 ;
+ END
+ END din0[20]
+ PIN din0[21]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 238.68 0.0 239.06 0.38 ;
+ END
+ END din0[21]
+ PIN din0[22]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 244.12 0.0 244.5 0.38 ;
+ END
+ END din0[22]
+ PIN din0[23]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 249.56 0.0 249.94 0.38 ;
+ END
+ END din0[23]
+ PIN din0[24]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 256.36 0.0 256.74 0.38 ;
+ END
+ END din0[24]
+ PIN din0[25]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 261.8 0.0 262.18 0.38 ;
+ END
+ END din0[25]
+ PIN din0[26]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 267.24 0.0 267.62 0.38 ;
+ END
+ END din0[26]
+ PIN din0[27]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 272.68 0.0 273.06 0.38 ;
+ END
+ END din0[27]
+ PIN din0[28]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 279.48 0.0 279.86 0.38 ;
+ END
+ END din0[28]
+ PIN din0[29]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 285.6 0.0 285.98 0.38 ;
+ END
+ END din0[29]
+ PIN din0[30]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 291.04 0.0 291.42 0.38 ;
+ END
+ END din0[30]
+ PIN din0[31]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 296.48 0.0 296.86 0.38 ;
+ END
+ END din0[31]
+ PIN addr0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 80.92 0.0 81.3 0.38 ;
+ END
+ END addr0[0]
+ PIN addr0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 86.36 0.0 86.74 0.38 ;
+ END
+ END addr0[1]
+ PIN addr0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 147.56 0.38 147.94 ;
+ END
+ END addr0[2]
+ PIN addr0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 155.72 0.38 156.1 ;
+ END
+ END addr0[3]
+ PIN addr0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 162.52 0.38 162.9 ;
+ END
+ END addr0[4]
+ PIN addr0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 171.36 0.38 171.74 ;
+ END
+ END addr0[5]
+ PIN addr0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 176.12 0.38 176.5 ;
+ END
+ END addr0[6]
+ PIN addr0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 184.28 0.38 184.66 ;
+ END
+ END addr0[7]
+ PIN addr0[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 189.72 0.38 190.1 ;
+ END
+ END addr0[8]
+ PIN addr0[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 199.24 0.38 199.62 ;
+ END
+ END addr0[9]
+ PIN addr1[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 603.84 665.72 604.22 666.1 ;
+ END
+ END addr1[0]
+ PIN addr1[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 597.72 665.72 598.1 666.1 ;
+ END
+ END addr1[1]
+ PIN addr1[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 689.52 95.2 689.9 95.58 ;
+ END
+ END addr1[2]
+ PIN addr1[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 689.52 87.04 689.9 87.42 ;
+ END
+ END addr1[3]
+ PIN addr1[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 689.52 80.92 689.9 81.3 ;
+ END
+ END addr1[4]
+ PIN addr1[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 689.52 72.08 689.9 72.46 ;
+ END
+ END addr1[5]
+ PIN addr1[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 622.2 0.0 622.58 0.38 ;
+ END
+ END addr1[6]
+ PIN addr1[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 620.16 0.0 620.54 0.38 ;
+ END
+ END addr1[7]
+ PIN addr1[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 620.84 0.0 621.22 0.38 ;
+ END
+ END addr1[8]
+ PIN addr1[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 621.52 0.0 621.9 0.38 ;
+ END
+ END addr1[9]
+ PIN csb0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 38.76 0.38 39.14 ;
+ END
+ END csb0
+ PIN csb1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 689.52 648.04 689.9 648.42 ;
+ END
+ END csb1
+ PIN web0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 47.6 0.38 47.98 ;
+ END
+ END web0
+ PIN clk0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 40.12 0.38 40.5 ;
+ END
+ END clk0
+ PIN clk1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 661.64 665.72 662.02 666.1 ;
+ END
+ END clk1
+ PIN wmask0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 91.8 0.0 92.18 0.38 ;
+ END
+ END wmask0[0]
+ PIN wmask0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 98.6 0.0 98.98 0.38 ;
+ END
+ END wmask0[1]
+ PIN wmask0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 103.36 0.0 103.74 0.38 ;
+ END
+ END wmask0[2]
+ PIN wmask0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 109.48 0.0 109.86 0.38 ;
+ END
+ END wmask0[3]
+ PIN dout0[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 142.8 0.0 143.18 0.38 ;
+ END
+ END dout0[0]
+ PIN dout0[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 157.76 0.0 158.14 0.38 ;
+ END
+ END dout0[1]
+ PIN dout0[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 170.0 0.0 170.38 0.38 ;
+ END
+ END dout0[2]
+ PIN dout0[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 182.92 0.0 183.3 0.38 ;
+ END
+ END dout0[3]
+ PIN dout0[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 195.16 0.0 195.54 0.38 ;
+ END
+ END dout0[4]
+ PIN dout0[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 206.72 0.0 207.1 0.38 ;
+ END
+ END dout0[5]
+ PIN dout0[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 218.96 0.0 219.34 0.38 ;
+ END
+ END dout0[6]
+ PIN dout0[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 230.52 0.0 230.9 0.38 ;
+ END
+ END dout0[7]
+ PIN dout0[8]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 247.52 0.0 247.9 0.38 ;
+ END
+ END dout0[8]
+ PIN dout0[9]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 257.72 0.0 258.1 0.38 ;
+ END
+ END dout0[9]
+ PIN dout0[10]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 270.64 0.0 271.02 0.38 ;
+ END
+ END dout0[10]
+ PIN dout0[11]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 282.88 0.0 283.26 0.38 ;
+ END
+ END dout0[11]
+ PIN dout0[12]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 294.44 0.0 294.82 0.38 ;
+ END
+ END dout0[12]
+ PIN dout0[13]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 307.36 0.0 307.74 0.38 ;
+ END
+ END dout0[13]
+ PIN dout0[14]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 320.28 0.0 320.66 0.38 ;
+ END
+ END dout0[14]
+ PIN dout0[15]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 332.52 0.0 332.9 0.38 ;
+ END
+ END dout0[15]
+ PIN dout0[16]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 345.44 0.0 345.82 0.38 ;
+ END
+ END dout0[16]
+ PIN dout0[17]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 357.68 0.0 358.06 0.38 ;
+ END
+ END dout0[17]
+ PIN dout0[18]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 369.92 0.0 370.3 0.38 ;
+ END
+ END dout0[18]
+ PIN dout0[19]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 382.16 0.0 382.54 0.38 ;
+ END
+ END dout0[19]
+ PIN dout0[20]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 395.08 0.0 395.46 0.38 ;
+ END
+ END dout0[20]
+ PIN dout0[21]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 407.32 0.0 407.7 0.38 ;
+ END
+ END dout0[21]
+ PIN dout0[22]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 419.56 0.0 419.94 0.38 ;
+ END
+ END dout0[22]
+ PIN dout0[23]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 432.48 0.0 432.86 0.38 ;
+ END
+ END dout0[23]
+ PIN dout0[24]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 443.36 0.0 443.74 0.38 ;
+ END
+ END dout0[24]
+ PIN dout0[25]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 457.64 0.0 458.02 0.38 ;
+ END
+ END dout0[25]
+ PIN dout0[26]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 469.88 0.0 470.26 0.38 ;
+ END
+ END dout0[26]
+ PIN dout0[27]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 482.12 0.0 482.5 0.38 ;
+ END
+ END dout0[27]
+ PIN dout0[28]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 495.04 0.0 495.42 0.38 ;
+ END
+ END dout0[28]
+ PIN dout0[29]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 507.28 0.0 507.66 0.38 ;
+ END
+ END dout0[29]
+ PIN dout0[30]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 519.52 0.0 519.9 0.38 ;
+ END
+ END dout0[30]
+ PIN dout0[31]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 532.44 0.0 532.82 0.38 ;
+ END
+ END dout0[31]
+ PIN dout1[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 146.2 665.72 146.58 666.1 ;
+ END
+ END dout1[0]
+ PIN dout1[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 157.76 665.72 158.14 666.1 ;
+ END
+ END dout1[1]
+ PIN dout1[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 170.68 665.72 171.06 666.1 ;
+ END
+ END dout1[2]
+ PIN dout1[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 182.92 665.72 183.3 666.1 ;
+ END
+ END dout1[3]
+ PIN dout1[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 195.84 665.72 196.22 666.1 ;
+ END
+ END dout1[4]
+ PIN dout1[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 208.08 665.72 208.46 666.1 ;
+ END
+ END dout1[5]
+ PIN dout1[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 221.0 665.72 221.38 666.1 ;
+ END
+ END dout1[6]
+ PIN dout1[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 233.24 665.72 233.62 666.1 ;
+ END
+ END dout1[7]
+ PIN dout1[8]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 245.48 665.72 245.86 666.1 ;
+ END
+ END dout1[8]
+ PIN dout1[9]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 257.72 665.72 258.1 666.1 ;
+ END
+ END dout1[9]
+ PIN dout1[10]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 269.96 665.72 270.34 666.1 ;
+ END
+ END dout1[10]
+ PIN dout1[11]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 282.88 665.72 283.26 666.1 ;
+ END
+ END dout1[11]
+ PIN dout1[12]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 295.8 665.72 296.18 666.1 ;
+ END
+ END dout1[12]
+ PIN dout1[13]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 308.04 665.72 308.42 666.1 ;
+ END
+ END dout1[13]
+ PIN dout1[14]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 320.96 665.72 321.34 666.1 ;
+ END
+ END dout1[14]
+ PIN dout1[15]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 333.2 665.72 333.58 666.1 ;
+ END
+ END dout1[15]
+ PIN dout1[16]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 344.76 665.72 345.14 666.1 ;
+ END
+ END dout1[16]
+ PIN dout1[17]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 358.36 665.72 358.74 666.1 ;
+ END
+ END dout1[17]
+ PIN dout1[18]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 369.92 665.72 370.3 666.1 ;
+ END
+ END dout1[18]
+ PIN dout1[19]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 382.84 665.72 383.22 666.1 ;
+ END
+ END dout1[19]
+ PIN dout1[20]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 395.08 665.72 395.46 666.1 ;
+ END
+ END dout1[20]
+ PIN dout1[21]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 408.0 665.72 408.38 666.1 ;
+ END
+ END dout1[21]
+ PIN dout1[22]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 420.24 665.72 420.62 666.1 ;
+ END
+ END dout1[22]
+ PIN dout1[23]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 433.16 665.72 433.54 666.1 ;
+ END
+ END dout1[23]
+ PIN dout1[24]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 445.4 665.72 445.78 666.1 ;
+ END
+ END dout1[24]
+ PIN dout1[25]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 457.64 665.72 458.02 666.1 ;
+ END
+ END dout1[25]
+ PIN dout1[26]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 469.88 665.72 470.26 666.1 ;
+ END
+ END dout1[26]
+ PIN dout1[27]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 482.12 665.72 482.5 666.1 ;
+ END
+ END dout1[27]
+ PIN dout1[28]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 495.04 665.72 495.42 666.1 ;
+ END
+ END dout1[28]
+ PIN dout1[29]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 507.96 665.72 508.34 666.1 ;
+ END
+ END dout1[29]
+ PIN dout1[30]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 520.2 665.72 520.58 666.1 ;
+ END
+ END dout1[30]
+ PIN dout1[31]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 533.12 665.72 533.5 666.1 ;
+ END
+ END dout1[31]
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met3 ;
+ RECT 1.36 663.0 688.54 664.74 ;
+ LAYER met4 ;
+ RECT 1.36 1.36 3.1 664.74 ;
+ LAYER met4 ;
+ RECT 686.8 1.36 688.54 664.74 ;
+ LAYER met3 ;
+ RECT 1.36 1.36 688.54 3.1 ;
+ END
+ END vccd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met4 ;
+ RECT 683.4 4.76 685.14 661.34 ;
+ LAYER met4 ;
+ RECT 4.76 4.76 6.5 661.34 ;
+ LAYER met3 ;
+ RECT 4.76 4.76 685.14 6.5 ;
+ LAYER met3 ;
+ RECT 4.76 659.6 685.14 661.34 ;
+ END
+ END vssd1
+ OBS
+ LAYER met1 ;
+ RECT 0.62 0.62 689.28 665.48 ;
+ LAYER met2 ;
+ RECT 0.62 0.62 689.28 665.48 ;
+ LAYER met3 ;
+ RECT 0.98 146.96 689.28 148.54 ;
+ RECT 0.62 148.54 0.98 155.12 ;
+ RECT 0.62 156.7 0.98 161.92 ;
+ RECT 0.62 163.5 0.98 170.76 ;
+ RECT 0.62 172.34 0.98 175.52 ;
+ RECT 0.62 177.1 0.98 183.68 ;
+ RECT 0.62 185.26 0.98 189.12 ;
+ RECT 0.62 190.7 0.98 198.64 ;
+ RECT 0.98 94.6 688.92 96.18 ;
+ RECT 0.98 96.18 688.92 146.96 ;
+ RECT 688.92 96.18 689.28 146.96 ;
+ RECT 688.92 88.02 689.28 94.6 ;
+ RECT 688.92 81.9 689.28 86.44 ;
+ RECT 688.92 73.06 689.28 80.32 ;
+ RECT 0.98 148.54 688.92 647.44 ;
+ RECT 0.98 647.44 688.92 649.02 ;
+ RECT 688.92 148.54 689.28 647.44 ;
+ RECT 0.62 48.58 0.98 146.96 ;
+ RECT 0.62 41.1 0.98 47.0 ;
+ RECT 0.62 200.22 0.76 662.4 ;
+ RECT 0.62 662.4 0.76 665.34 ;
+ RECT 0.62 665.34 0.76 665.48 ;
+ RECT 0.76 200.22 0.98 662.4 ;
+ RECT 0.76 665.34 0.98 665.48 ;
+ RECT 0.98 665.34 688.92 665.48 ;
+ RECT 688.92 649.02 689.14 662.4 ;
+ RECT 688.92 665.34 689.14 665.48 ;
+ RECT 689.14 649.02 689.28 662.4 ;
+ RECT 689.14 662.4 689.28 665.34 ;
+ RECT 689.14 665.34 689.28 665.48 ;
+ RECT 0.98 0.62 688.92 0.76 ;
+ RECT 688.92 0.62 689.14 0.76 ;
+ RECT 688.92 3.7 689.14 71.48 ;
+ RECT 689.14 0.62 689.28 0.76 ;
+ RECT 689.14 0.76 689.28 3.7 ;
+ RECT 689.14 3.7 689.28 71.48 ;
+ RECT 0.62 0.62 0.76 0.76 ;
+ RECT 0.62 0.76 0.76 3.7 ;
+ RECT 0.62 3.7 0.76 38.16 ;
+ RECT 0.76 0.62 0.98 0.76 ;
+ RECT 0.76 3.7 0.98 38.16 ;
+ RECT 0.98 3.7 4.16 4.16 ;
+ RECT 0.98 4.16 4.16 7.1 ;
+ RECT 0.98 7.1 4.16 94.6 ;
+ RECT 4.16 3.7 685.74 4.16 ;
+ RECT 4.16 7.1 685.74 94.6 ;
+ RECT 685.74 3.7 688.92 4.16 ;
+ RECT 685.74 4.16 688.92 7.1 ;
+ RECT 685.74 7.1 688.92 94.6 ;
+ RECT 0.98 649.02 4.16 659.0 ;
+ RECT 0.98 659.0 4.16 661.94 ;
+ RECT 0.98 661.94 4.16 662.4 ;
+ RECT 4.16 649.02 685.74 659.0 ;
+ RECT 4.16 661.94 685.74 662.4 ;
+ RECT 685.74 649.02 688.92 659.0 ;
+ RECT 685.74 659.0 688.92 661.94 ;
+ RECT 685.74 661.94 688.92 662.4 ;
+ LAYER met4 ;
+ RECT 115.68 0.98 117.26 665.48 ;
+ RECT 117.26 0.62 121.12 0.98 ;
+ RECT 122.7 0.62 127.24 0.98 ;
+ RECT 128.82 0.62 132.68 0.98 ;
+ RECT 134.26 0.62 138.12 0.98 ;
+ RECT 145.14 0.62 150.36 0.98 ;
+ RECT 151.94 0.62 156.48 0.98 ;
+ RECT 163.5 0.62 167.36 0.98 ;
+ RECT 174.38 0.62 179.6 0.98 ;
+ RECT 186.62 0.62 190.48 0.98 ;
+ RECT 198.86 0.62 203.4 0.98 ;
+ RECT 210.42 0.62 214.28 0.98 ;
+ RECT 221.3 0.62 226.52 0.98 ;
+ RECT 233.54 0.62 238.08 0.98 ;
+ RECT 239.66 0.62 243.52 0.98 ;
+ RECT 250.54 0.62 255.76 0.98 ;
+ RECT 262.78 0.62 266.64 0.98 ;
+ RECT 273.66 0.62 278.88 0.98 ;
+ RECT 286.58 0.62 290.44 0.98 ;
+ RECT 81.9 0.62 85.76 0.98 ;
+ RECT 117.26 0.98 603.24 665.12 ;
+ RECT 603.24 0.98 604.82 665.12 ;
+ RECT 598.7 665.12 603.24 665.48 ;
+ RECT 604.82 665.12 661.04 665.48 ;
+ RECT 87.34 0.62 91.2 0.98 ;
+ RECT 92.78 0.62 98.0 0.98 ;
+ RECT 99.58 0.62 102.76 0.98 ;
+ RECT 104.34 0.62 108.88 0.98 ;
+ RECT 110.46 0.62 115.68 0.98 ;
+ RECT 139.7 0.62 142.2 0.98 ;
+ RECT 158.74 0.62 161.92 0.98 ;
+ RECT 168.94 0.62 169.4 0.98 ;
+ RECT 170.98 0.62 172.8 0.98 ;
+ RECT 181.18 0.62 182.32 0.98 ;
+ RECT 183.9 0.62 185.04 0.98 ;
+ RECT 192.06 0.62 194.56 0.98 ;
+ RECT 196.14 0.62 197.28 0.98 ;
+ RECT 204.98 0.62 206.12 0.98 ;
+ RECT 207.7 0.62 208.84 0.98 ;
+ RECT 215.86 0.62 218.36 0.98 ;
+ RECT 228.1 0.62 229.92 0.98 ;
+ RECT 231.5 0.62 231.96 0.98 ;
+ RECT 245.1 0.62 246.92 0.98 ;
+ RECT 248.5 0.62 248.96 0.98 ;
+ RECT 258.7 0.62 261.2 0.98 ;
+ RECT 268.22 0.62 270.04 0.98 ;
+ RECT 271.62 0.62 272.08 0.98 ;
+ RECT 280.46 0.62 282.28 0.98 ;
+ RECT 283.86 0.62 285.0 0.98 ;
+ RECT 292.02 0.62 293.84 0.98 ;
+ RECT 295.42 0.62 295.88 0.98 ;
+ RECT 297.46 0.62 306.76 0.98 ;
+ RECT 308.34 0.62 319.68 0.98 ;
+ RECT 321.26 0.62 331.92 0.98 ;
+ RECT 333.5 0.62 344.84 0.98 ;
+ RECT 346.42 0.62 357.08 0.98 ;
+ RECT 358.66 0.62 369.32 0.98 ;
+ RECT 370.9 0.62 381.56 0.98 ;
+ RECT 383.14 0.62 394.48 0.98 ;
+ RECT 396.06 0.62 406.72 0.98 ;
+ RECT 408.3 0.62 418.96 0.98 ;
+ RECT 420.54 0.62 431.88 0.98 ;
+ RECT 433.46 0.62 442.76 0.98 ;
+ RECT 444.34 0.62 457.04 0.98 ;
+ RECT 458.62 0.62 469.28 0.98 ;
+ RECT 470.86 0.62 481.52 0.98 ;
+ RECT 483.1 0.62 494.44 0.98 ;
+ RECT 496.02 0.62 506.68 0.98 ;
+ RECT 508.26 0.62 518.92 0.98 ;
+ RECT 520.5 0.62 531.84 0.98 ;
+ RECT 533.42 0.62 619.56 0.98 ;
+ RECT 117.26 665.12 145.6 665.48 ;
+ RECT 147.18 665.12 157.16 665.48 ;
+ RECT 158.74 665.12 170.08 665.48 ;
+ RECT 171.66 665.12 182.32 665.48 ;
+ RECT 183.9 665.12 195.24 665.48 ;
+ RECT 196.82 665.12 207.48 665.48 ;
+ RECT 209.06 665.12 220.4 665.48 ;
+ RECT 221.98 665.12 232.64 665.48 ;
+ RECT 234.22 665.12 244.88 665.48 ;
+ RECT 246.46 665.12 257.12 665.48 ;
+ RECT 258.7 665.12 269.36 665.48 ;
+ RECT 270.94 665.12 282.28 665.48 ;
+ RECT 283.86 665.12 295.2 665.48 ;
+ RECT 296.78 665.12 307.44 665.48 ;
+ RECT 309.02 665.12 320.36 665.48 ;
+ RECT 321.94 665.12 332.6 665.48 ;
+ RECT 334.18 665.12 344.16 665.48 ;
+ RECT 345.74 665.12 357.76 665.48 ;
+ RECT 359.34 665.12 369.32 665.48 ;
+ RECT 370.9 665.12 382.24 665.48 ;
+ RECT 383.82 665.12 394.48 665.48 ;
+ RECT 396.06 665.12 407.4 665.48 ;
+ RECT 408.98 665.12 419.64 665.48 ;
+ RECT 421.22 665.12 432.56 665.48 ;
+ RECT 434.14 665.12 444.8 665.48 ;
+ RECT 446.38 665.12 457.04 665.48 ;
+ RECT 458.62 665.12 469.28 665.48 ;
+ RECT 470.86 665.12 481.52 665.48 ;
+ RECT 483.1 665.12 494.44 665.48 ;
+ RECT 496.02 665.12 507.36 665.48 ;
+ RECT 508.94 665.12 519.6 665.48 ;
+ RECT 521.18 665.12 532.52 665.48 ;
+ RECT 534.1 665.12 597.12 665.48 ;
+ RECT 0.62 0.98 0.76 665.34 ;
+ RECT 0.62 665.34 0.76 665.48 ;
+ RECT 0.76 665.34 3.7 665.48 ;
+ RECT 3.7 665.34 115.68 665.48 ;
+ RECT 0.62 0.62 0.76 0.76 ;
+ RECT 0.62 0.76 0.76 0.98 ;
+ RECT 0.76 0.62 3.7 0.76 ;
+ RECT 3.7 0.62 80.32 0.76 ;
+ RECT 3.7 0.76 80.32 0.98 ;
+ RECT 689.14 0.98 689.28 665.12 ;
+ RECT 623.18 0.62 686.2 0.76 ;
+ RECT 623.18 0.76 686.2 0.98 ;
+ RECT 686.2 0.62 689.14 0.76 ;
+ RECT 689.14 0.62 689.28 0.76 ;
+ RECT 689.14 0.76 689.28 0.98 ;
+ RECT 662.62 665.12 686.2 665.34 ;
+ RECT 662.62 665.34 686.2 665.48 ;
+ RECT 686.2 665.34 689.14 665.48 ;
+ RECT 689.14 665.12 689.28 665.34 ;
+ RECT 689.14 665.34 689.28 665.48 ;
+ RECT 604.82 0.98 682.8 4.16 ;
+ RECT 604.82 4.16 682.8 661.94 ;
+ RECT 604.82 661.94 682.8 665.12 ;
+ RECT 682.8 0.98 685.74 4.16 ;
+ RECT 682.8 661.94 685.74 665.12 ;
+ RECT 685.74 0.98 686.2 4.16 ;
+ RECT 685.74 4.16 686.2 661.94 ;
+ RECT 685.74 661.94 686.2 665.12 ;
+ RECT 3.7 0.98 4.16 4.16 ;
+ RECT 3.7 4.16 4.16 661.94 ;
+ RECT 3.7 661.94 4.16 665.34 ;
+ RECT 4.16 0.98 7.1 4.16 ;
+ RECT 4.16 661.94 7.1 665.34 ;
+ RECT 7.1 0.98 115.68 4.16 ;
+ RECT 7.1 4.16 115.68 661.94 ;
+ RECT 7.1 661.94 115.68 665.34 ;
+ END
+END sky130_sram_4kbyte_1rw1r_32x1024_8
+END LIBRARY
diff --git a/lef/sky130_sram_8kbyte_1rw1r_32x2048_8.lef b/lef/sky130_sram_8kbyte_1rw1r_32x2048_8.lef
new file mode 100644
index 0000000..6449e76
--- /dev/null
+++ b/lef/sky130_sram_8kbyte_1rw1r_32x2048_8.lef
@@ -0,0 +1,1144 @@
+VERSION 5.4 ;
+NAMESCASESENSITIVE ON ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+UNITS
+ DATABASE MICRONS 2000 ;
+END UNITS
+MACRO sky130_sram_8kbyte_1rw1r_32x2048_8
+ CLASS BLOCK ;
+ SIZE 1093.82 BY 720.5 ;
+ SYMMETRY X Y R90 ;
+ PIN din0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 123.08 0.0 123.46 0.38 ;
+ END
+ END din0[0]
+ PIN din0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 129.88 0.0 130.26 0.38 ;
+ END
+ END din0[1]
+ PIN din0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 135.32 0.0 135.7 0.38 ;
+ END
+ END din0[2]
+ PIN din0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 141.44 0.0 141.82 0.38 ;
+ END
+ END din0[3]
+ PIN din0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 146.2 0.0 146.58 0.38 ;
+ END
+ END din0[4]
+ PIN din0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 153.0 0.0 153.38 0.38 ;
+ END
+ END din0[5]
+ PIN din0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 158.44 0.0 158.82 0.38 ;
+ END
+ END din0[6]
+ PIN din0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 163.88 0.0 164.26 0.38 ;
+ END
+ END din0[7]
+ PIN din0[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 170.0 0.0 170.38 0.38 ;
+ END
+ END din0[8]
+ PIN din0[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 175.44 0.0 175.82 0.38 ;
+ END
+ END din0[9]
+ PIN din0[10]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 182.24 0.0 182.62 0.38 ;
+ END
+ END din0[10]
+ PIN din0[11]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 187.68 0.0 188.06 0.38 ;
+ END
+ END din0[11]
+ PIN din0[12]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 193.12 0.0 193.5 0.38 ;
+ END
+ END din0[12]
+ PIN din0[13]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 199.24 0.0 199.62 0.38 ;
+ END
+ END din0[13]
+ PIN din0[14]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 204.68 0.0 205.06 0.38 ;
+ END
+ END din0[14]
+ PIN din0[15]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 211.48 0.0 211.86 0.38 ;
+ END
+ END din0[15]
+ PIN din0[16]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 216.92 0.0 217.3 0.38 ;
+ END
+ END din0[16]
+ PIN din0[17]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 223.04 0.0 223.42 0.38 ;
+ END
+ END din0[17]
+ PIN din0[18]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 229.16 0.0 229.54 0.38 ;
+ END
+ END din0[18]
+ PIN din0[19]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 234.6 0.0 234.98 0.38 ;
+ END
+ END din0[19]
+ PIN din0[20]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 240.04 0.0 240.42 0.38 ;
+ END
+ END din0[20]
+ PIN din0[21]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 245.48 0.0 245.86 0.38 ;
+ END
+ END din0[21]
+ PIN din0[22]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 251.6 0.0 251.98 0.38 ;
+ END
+ END din0[22]
+ PIN din0[23]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 257.72 0.0 258.1 0.38 ;
+ END
+ END din0[23]
+ PIN din0[24]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 263.84 0.0 264.22 0.38 ;
+ END
+ END din0[24]
+ PIN din0[25]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 269.28 0.0 269.66 0.38 ;
+ END
+ END din0[25]
+ PIN din0[26]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 274.72 0.0 275.1 0.38 ;
+ END
+ END din0[26]
+ PIN din0[27]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 280.84 0.0 281.22 0.38 ;
+ END
+ END din0[27]
+ PIN din0[28]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 286.96 0.0 287.34 0.38 ;
+ END
+ END din0[28]
+ PIN din0[29]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 293.08 0.0 293.46 0.38 ;
+ END
+ END din0[29]
+ PIN din0[30]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 299.2 0.0 299.58 0.38 ;
+ END
+ END din0[30]
+ PIN din0[31]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 303.96 0.0 304.34 0.38 ;
+ END
+ END din0[31]
+ PIN addr0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 82.28 0.0 82.66 0.38 ;
+ END
+ END addr0[0]
+ PIN addr0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 88.4 0.0 88.78 0.38 ;
+ END
+ END addr0[1]
+ PIN addr0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 93.84 0.0 94.22 0.38 ;
+ END
+ END addr0[2]
+ PIN addr0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 174.08 0.38 174.46 ;
+ END
+ END addr0[3]
+ PIN addr0[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 182.24 0.38 182.62 ;
+ END
+ END addr0[4]
+ PIN addr0[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 189.04 0.38 189.42 ;
+ END
+ END addr0[5]
+ PIN addr0[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 197.2 0.38 197.58 ;
+ END
+ END addr0[6]
+ PIN addr0[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 202.64 0.38 203.02 ;
+ END
+ END addr0[7]
+ PIN addr0[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 210.8 0.38 211.18 ;
+ END
+ END addr0[8]
+ PIN addr0[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 216.24 0.38 216.62 ;
+ END
+ END addr0[9]
+ PIN addr0[10]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 225.76 0.38 226.14 ;
+ END
+ END addr0[10]
+ PIN addr1[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 1005.04 720.12 1005.42 720.5 ;
+ END
+ END addr1[0]
+ PIN addr1[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 999.6 720.12 999.98 720.5 ;
+ END
+ END addr1[1]
+ PIN addr1[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 992.8 720.12 993.18 720.5 ;
+ END
+ END addr1[2]
+ PIN addr1[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 121.04 1093.82 121.42 ;
+ END
+ END addr1[3]
+ PIN addr1[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 112.88 1093.82 113.26 ;
+ END
+ END addr1[4]
+ PIN addr1[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 107.44 1093.82 107.82 ;
+ END
+ END addr1[5]
+ PIN addr1[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 97.92 1093.82 98.3 ;
+ END
+ END addr1[6]
+ PIN addr1[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 92.48 1093.82 92.86 ;
+ END
+ END addr1[7]
+ PIN addr1[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 84.32 1093.82 84.7 ;
+ END
+ END addr1[8]
+ PIN addr1[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 78.88 1093.82 79.26 ;
+ END
+ END addr1[9]
+ PIN addr1[10]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 70.72 1093.82 71.1 ;
+ END
+ END addr1[10]
+ PIN csb0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 65.96 0.38 66.34 ;
+ END
+ END csb0
+ PIN csb1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 673.2 1093.82 673.58 ;
+ END
+ END csb1
+ PIN web0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 74.8 0.38 75.18 ;
+ END
+ END web0
+ PIN clk0
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.0 66.64 0.38 67.02 ;
+ END
+ END clk0
+ PIN clk1
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 1093.44 672.52 1093.82 672.9 ;
+ END
+ END clk1
+ PIN wmask0[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 99.96 0.0 100.34 0.38 ;
+ END
+ END wmask0[0]
+ PIN wmask0[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 105.4 0.0 105.78 0.38 ;
+ END
+ END wmask0[1]
+ PIN wmask0[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 111.52 0.0 111.9 0.38 ;
+ END
+ END wmask0[2]
+ PIN wmask0[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 117.64 0.0 118.02 0.38 ;
+ END
+ END wmask0[3]
+ PIN dout0[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 144.84 0.0 145.22 0.38 ;
+ END
+ END dout0[0]
+ PIN dout0[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 172.72 0.0 173.1 0.38 ;
+ END
+ END dout0[1]
+ PIN dout0[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 197.2 0.0 197.58 0.38 ;
+ END
+ END dout0[2]
+ PIN dout0[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 221.0 0.0 221.38 0.38 ;
+ END
+ END dout0[3]
+ PIN dout0[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 247.52 0.0 247.9 0.38 ;
+ END
+ END dout0[4]
+ PIN dout0[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 272.68 0.0 273.06 0.38 ;
+ END
+ END dout0[5]
+ PIN dout0[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 296.48 0.0 296.86 0.38 ;
+ END
+ END dout0[6]
+ PIN dout0[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 322.32 0.0 322.7 0.38 ;
+ END
+ END dout0[7]
+ PIN dout0[8]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 347.48 0.0 347.86 0.38 ;
+ END
+ END dout0[8]
+ PIN dout0[9]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 371.96 0.0 372.34 0.38 ;
+ END
+ END dout0[9]
+ PIN dout0[10]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 397.12 0.0 397.5 0.38 ;
+ END
+ END dout0[10]
+ PIN dout0[11]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 421.6 0.0 421.98 0.38 ;
+ END
+ END dout0[11]
+ PIN dout0[12]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 446.76 0.0 447.14 0.38 ;
+ END
+ END dout0[12]
+ PIN dout0[13]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 471.92 0.0 472.3 0.38 ;
+ END
+ END dout0[13]
+ PIN dout0[14]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 497.08 0.0 497.46 0.38 ;
+ END
+ END dout0[14]
+ PIN dout0[15]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 521.56 0.0 521.94 0.38 ;
+ END
+ END dout0[15]
+ PIN dout0[16]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 545.36 0.0 545.74 0.38 ;
+ END
+ END dout0[16]
+ PIN dout0[17]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 571.88 0.0 572.26 0.38 ;
+ END
+ END dout0[17]
+ PIN dout0[18]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 596.36 0.0 596.74 0.38 ;
+ END
+ END dout0[18]
+ PIN dout0[19]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 621.52 0.0 621.9 0.38 ;
+ END
+ END dout0[19]
+ PIN dout0[20]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 646.68 0.0 647.06 0.38 ;
+ END
+ END dout0[20]
+ PIN dout0[21]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 671.84 0.0 672.22 0.38 ;
+ END
+ END dout0[21]
+ PIN dout0[22]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 696.32 0.0 696.7 0.38 ;
+ END
+ END dout0[22]
+ PIN dout0[23]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 721.48 0.0 721.86 0.38 ;
+ END
+ END dout0[23]
+ PIN dout0[24]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 745.28 0.0 745.66 0.38 ;
+ END
+ END dout0[24]
+ PIN dout0[25]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 771.12 0.0 771.5 0.38 ;
+ END
+ END dout0[25]
+ PIN dout0[26]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 796.28 0.0 796.66 0.38 ;
+ END
+ END dout0[26]
+ PIN dout0[27]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 821.44 0.0 821.82 0.38 ;
+ END
+ END dout0[27]
+ PIN dout0[28]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 845.92 0.0 846.3 0.38 ;
+ END
+ END dout0[28]
+ PIN dout0[29]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 871.08 0.0 871.46 0.38 ;
+ END
+ END dout0[29]
+ PIN dout0[30]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 896.24 0.0 896.62 0.38 ;
+ END
+ END dout0[30]
+ PIN dout0[31]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 921.4 0.0 921.78 0.38 ;
+ END
+ END dout0[31]
+ PIN dout1[0]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 147.56 720.12 147.94 720.5 ;
+ END
+ END dout1[0]
+ PIN dout1[1]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 172.04 720.12 172.42 720.5 ;
+ END
+ END dout1[1]
+ PIN dout1[2]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 197.2 720.12 197.58 720.5 ;
+ END
+ END dout1[2]
+ PIN dout1[3]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 222.36 720.12 222.74 720.5 ;
+ END
+ END dout1[3]
+ PIN dout1[4]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 247.52 720.12 247.9 720.5 ;
+ END
+ END dout1[4]
+ PIN dout1[5]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 272.68 720.12 273.06 720.5 ;
+ END
+ END dout1[5]
+ PIN dout1[6]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 297.16 720.12 297.54 720.5 ;
+ END
+ END dout1[6]
+ PIN dout1[7]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 322.32 720.12 322.7 720.5 ;
+ END
+ END dout1[7]
+ PIN dout1[8]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 347.48 720.12 347.86 720.5 ;
+ END
+ END dout1[8]
+ PIN dout1[9]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 372.64 720.12 373.02 720.5 ;
+ END
+ END dout1[9]
+ PIN dout1[10]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 397.8 720.12 398.18 720.5 ;
+ END
+ END dout1[10]
+ PIN dout1[11]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 421.6 720.12 421.98 720.5 ;
+ END
+ END dout1[11]
+ PIN dout1[12]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 446.76 720.12 447.14 720.5 ;
+ END
+ END dout1[12]
+ PIN dout1[13]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 472.6 720.12 472.98 720.5 ;
+ END
+ END dout1[13]
+ PIN dout1[14]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 497.08 720.12 497.46 720.5 ;
+ END
+ END dout1[14]
+ PIN dout1[15]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 521.56 720.12 521.94 720.5 ;
+ END
+ END dout1[15]
+ PIN dout1[16]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 546.72 720.12 547.1 720.5 ;
+ END
+ END dout1[16]
+ PIN dout1[17]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 571.88 720.12 572.26 720.5 ;
+ END
+ END dout1[17]
+ PIN dout1[18]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 596.36 720.12 596.74 720.5 ;
+ END
+ END dout1[18]
+ PIN dout1[19]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 621.52 720.12 621.9 720.5 ;
+ END
+ END dout1[19]
+ PIN dout1[20]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 646.68 720.12 647.06 720.5 ;
+ END
+ END dout1[20]
+ PIN dout1[21]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 671.84 720.12 672.22 720.5 ;
+ END
+ END dout1[21]
+ PIN dout1[22]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 697.0 720.12 697.38 720.5 ;
+ END
+ END dout1[22]
+ PIN dout1[23]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 721.48 720.12 721.86 720.5 ;
+ END
+ END dout1[23]
+ PIN dout1[24]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 746.64 720.12 747.02 720.5 ;
+ END
+ END dout1[24]
+ PIN dout1[25]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 771.8 720.12 772.18 720.5 ;
+ END
+ END dout1[25]
+ PIN dout1[26]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 796.96 720.12 797.34 720.5 ;
+ END
+ END dout1[26]
+ PIN dout1[27]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 822.12 720.12 822.5 720.5 ;
+ END
+ END dout1[27]
+ PIN dout1[28]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 845.92 720.12 846.3 720.5 ;
+ END
+ END dout1[28]
+ PIN dout1[29]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 871.08 720.12 871.46 720.5 ;
+ END
+ END dout1[29]
+ PIN dout1[30]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 896.92 720.12 897.3 720.5 ;
+ END
+ END dout1[30]
+ PIN dout1[31]
+ DIRECTION OUTPUT ;
+ PORT
+ LAYER met4 ;
+ RECT 921.4 720.12 921.78 720.5 ;
+ END
+ END dout1[31]
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met3 ;
+ RECT 1.36 1.36 1092.46 3.1 ;
+ LAYER met4 ;
+ RECT 1.36 1.36 3.1 719.14 ;
+ LAYER met3 ;
+ RECT 1.36 717.4 1092.46 719.14 ;
+ LAYER met4 ;
+ RECT 1090.72 1.36 1092.46 719.14 ;
+ END
+ END vccd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER met3 ;
+ RECT 4.76 714.0 1089.06 715.74 ;
+ LAYER met4 ;
+ RECT 1087.32 4.76 1089.06 715.74 ;
+ LAYER met3 ;
+ RECT 4.76 4.76 1089.06 6.5 ;
+ LAYER met4 ;
+ RECT 4.76 4.76 6.5 715.74 ;
+ END
+ END vssd1
+ OBS
+ LAYER met1 ;
+ RECT 0.62 0.62 1093.2 719.88 ;
+ LAYER met2 ;
+ RECT 0.62 0.62 1093.2 719.88 ;
+ LAYER met3 ;
+ RECT 0.98 173.48 1093.2 175.06 ;
+ RECT 0.62 175.06 0.98 181.64 ;
+ RECT 0.62 183.22 0.98 188.44 ;
+ RECT 0.62 190.02 0.98 196.6 ;
+ RECT 0.62 198.18 0.98 202.04 ;
+ RECT 0.62 203.62 0.98 210.2 ;
+ RECT 0.62 211.78 0.98 215.64 ;
+ RECT 0.62 217.22 0.98 225.16 ;
+ RECT 0.98 120.44 1092.84 122.02 ;
+ RECT 0.98 122.02 1092.84 173.48 ;
+ RECT 1092.84 122.02 1093.2 173.48 ;
+ RECT 1092.84 113.86 1093.2 120.44 ;
+ RECT 1092.84 108.42 1093.2 112.28 ;
+ RECT 1092.84 98.9 1093.2 106.84 ;
+ RECT 1092.84 93.46 1093.2 97.32 ;
+ RECT 1092.84 85.3 1093.2 91.88 ;
+ RECT 1092.84 79.86 1093.2 83.72 ;
+ RECT 1092.84 71.7 1093.2 78.28 ;
+ RECT 0.98 175.06 1092.84 672.6 ;
+ RECT 0.98 672.6 1092.84 674.18 ;
+ RECT 0.62 75.78 0.98 173.48 ;
+ RECT 0.62 67.62 0.98 74.2 ;
+ RECT 1092.84 175.06 1093.2 671.92 ;
+ RECT 0.98 0.62 1092.84 0.76 ;
+ RECT 1092.84 0.62 1093.06 0.76 ;
+ RECT 1092.84 3.7 1093.06 70.12 ;
+ RECT 1093.06 0.62 1093.2 0.76 ;
+ RECT 1093.06 0.76 1093.2 3.7 ;
+ RECT 1093.06 3.7 1093.2 70.12 ;
+ RECT 0.62 0.62 0.76 0.76 ;
+ RECT 0.62 0.76 0.76 3.7 ;
+ RECT 0.62 3.7 0.76 65.36 ;
+ RECT 0.76 0.62 0.98 0.76 ;
+ RECT 0.76 3.7 0.98 65.36 ;
+ RECT 0.62 226.74 0.76 716.8 ;
+ RECT 0.62 716.8 0.76 719.74 ;
+ RECT 0.62 719.74 0.76 719.88 ;
+ RECT 0.76 226.74 0.98 716.8 ;
+ RECT 0.76 719.74 0.98 719.88 ;
+ RECT 0.98 719.74 1092.84 719.88 ;
+ RECT 1092.84 674.18 1093.06 716.8 ;
+ RECT 1092.84 719.74 1093.06 719.88 ;
+ RECT 1093.06 674.18 1093.2 716.8 ;
+ RECT 1093.06 716.8 1093.2 719.74 ;
+ RECT 1093.06 719.74 1093.2 719.88 ;
+ RECT 0.98 674.18 4.16 713.4 ;
+ RECT 0.98 713.4 4.16 716.34 ;
+ RECT 0.98 716.34 4.16 716.8 ;
+ RECT 4.16 674.18 1089.66 713.4 ;
+ RECT 4.16 716.34 1089.66 716.8 ;
+ RECT 1089.66 674.18 1092.84 713.4 ;
+ RECT 1089.66 713.4 1092.84 716.34 ;
+ RECT 1089.66 716.34 1092.84 716.8 ;
+ RECT 0.98 3.7 4.16 4.16 ;
+ RECT 0.98 4.16 4.16 7.1 ;
+ RECT 0.98 7.1 4.16 120.44 ;
+ RECT 4.16 3.7 1089.66 4.16 ;
+ RECT 4.16 7.1 1089.66 120.44 ;
+ RECT 1089.66 3.7 1092.84 4.16 ;
+ RECT 1089.66 4.16 1092.84 7.1 ;
+ RECT 1089.66 7.1 1092.84 120.44 ;
+ LAYER met4 ;
+ RECT 122.48 0.98 124.06 719.88 ;
+ RECT 124.06 0.62 129.28 0.98 ;
+ RECT 130.86 0.62 134.72 0.98 ;
+ RECT 136.3 0.62 140.84 0.98 ;
+ RECT 147.18 0.62 152.4 0.98 ;
+ RECT 153.98 0.62 157.84 0.98 ;
+ RECT 159.42 0.62 163.28 0.98 ;
+ RECT 164.86 0.62 169.4 0.98 ;
+ RECT 176.42 0.62 181.64 0.98 ;
+ RECT 183.22 0.62 187.08 0.98 ;
+ RECT 188.66 0.62 192.52 0.98 ;
+ RECT 200.22 0.62 204.08 0.98 ;
+ RECT 205.66 0.62 210.88 0.98 ;
+ RECT 212.46 0.62 216.32 0.98 ;
+ RECT 224.02 0.62 228.56 0.98 ;
+ RECT 230.14 0.62 234.0 0.98 ;
+ RECT 235.58 0.62 239.44 0.98 ;
+ RECT 241.02 0.62 244.88 0.98 ;
+ RECT 252.58 0.62 257.12 0.98 ;
+ RECT 258.7 0.62 263.24 0.98 ;
+ RECT 264.82 0.62 268.68 0.98 ;
+ RECT 275.7 0.62 280.24 0.98 ;
+ RECT 281.82 0.62 286.36 0.98 ;
+ RECT 287.94 0.62 292.48 0.98 ;
+ RECT 300.18 0.62 303.36 0.98 ;
+ RECT 83.26 0.62 87.8 0.98 ;
+ RECT 89.38 0.62 93.24 0.98 ;
+ RECT 124.06 0.98 1004.44 719.52 ;
+ RECT 1004.44 0.98 1006.02 719.52 ;
+ RECT 1000.58 719.52 1004.44 719.88 ;
+ RECT 993.78 719.52 999.0 719.88 ;
+ RECT 94.82 0.62 99.36 0.98 ;
+ RECT 100.94 0.62 104.8 0.98 ;
+ RECT 106.38 0.62 110.92 0.98 ;
+ RECT 112.5 0.62 117.04 0.98 ;
+ RECT 118.62 0.62 122.48 0.98 ;
+ RECT 142.42 0.62 144.24 0.98 ;
+ RECT 170.98 0.62 172.12 0.98 ;
+ RECT 173.7 0.62 174.84 0.98 ;
+ RECT 194.1 0.62 196.6 0.98 ;
+ RECT 198.18 0.62 198.64 0.98 ;
+ RECT 217.9 0.62 220.4 0.98 ;
+ RECT 221.98 0.62 222.44 0.98 ;
+ RECT 246.46 0.62 246.92 0.98 ;
+ RECT 248.5 0.62 251.0 0.98 ;
+ RECT 270.26 0.62 272.08 0.98 ;
+ RECT 273.66 0.62 274.12 0.98 ;
+ RECT 294.06 0.62 295.88 0.98 ;
+ RECT 297.46 0.62 298.6 0.98 ;
+ RECT 304.94 0.62 321.72 0.98 ;
+ RECT 323.3 0.62 346.88 0.98 ;
+ RECT 348.46 0.62 371.36 0.98 ;
+ RECT 372.94 0.62 396.52 0.98 ;
+ RECT 398.1 0.62 421.0 0.98 ;
+ RECT 422.58 0.62 446.16 0.98 ;
+ RECT 447.74 0.62 471.32 0.98 ;
+ RECT 472.9 0.62 496.48 0.98 ;
+ RECT 498.06 0.62 520.96 0.98 ;
+ RECT 522.54 0.62 544.76 0.98 ;
+ RECT 546.34 0.62 571.28 0.98 ;
+ RECT 572.86 0.62 595.76 0.98 ;
+ RECT 597.34 0.62 620.92 0.98 ;
+ RECT 622.5 0.62 646.08 0.98 ;
+ RECT 647.66 0.62 671.24 0.98 ;
+ RECT 672.82 0.62 695.72 0.98 ;
+ RECT 697.3 0.62 720.88 0.98 ;
+ RECT 722.46 0.62 744.68 0.98 ;
+ RECT 746.26 0.62 770.52 0.98 ;
+ RECT 772.1 0.62 795.68 0.98 ;
+ RECT 797.26 0.62 820.84 0.98 ;
+ RECT 822.42 0.62 845.32 0.98 ;
+ RECT 846.9 0.62 870.48 0.98 ;
+ RECT 872.06 0.62 895.64 0.98 ;
+ RECT 897.22 0.62 920.8 0.98 ;
+ RECT 124.06 719.52 146.96 719.88 ;
+ RECT 148.54 719.52 171.44 719.88 ;
+ RECT 173.02 719.52 196.6 719.88 ;
+ RECT 198.18 719.52 221.76 719.88 ;
+ RECT 223.34 719.52 246.92 719.88 ;
+ RECT 248.5 719.52 272.08 719.88 ;
+ RECT 273.66 719.52 296.56 719.88 ;
+ RECT 298.14 719.52 321.72 719.88 ;
+ RECT 323.3 719.52 346.88 719.88 ;
+ RECT 348.46 719.52 372.04 719.88 ;
+ RECT 373.62 719.52 397.2 719.88 ;
+ RECT 398.78 719.52 421.0 719.88 ;
+ RECT 422.58 719.52 446.16 719.88 ;
+ RECT 447.74 719.52 472.0 719.88 ;
+ RECT 473.58 719.52 496.48 719.88 ;
+ RECT 498.06 719.52 520.96 719.88 ;
+ RECT 522.54 719.52 546.12 719.88 ;
+ RECT 547.7 719.52 571.28 719.88 ;
+ RECT 572.86 719.52 595.76 719.88 ;
+ RECT 597.34 719.52 620.92 719.88 ;
+ RECT 622.5 719.52 646.08 719.88 ;
+ RECT 647.66 719.52 671.24 719.88 ;
+ RECT 672.82 719.52 696.4 719.88 ;
+ RECT 697.98 719.52 720.88 719.88 ;
+ RECT 722.46 719.52 746.04 719.88 ;
+ RECT 747.62 719.52 771.2 719.88 ;
+ RECT 772.78 719.52 796.36 719.88 ;
+ RECT 797.94 719.52 821.52 719.88 ;
+ RECT 823.1 719.52 845.32 719.88 ;
+ RECT 846.9 719.52 870.48 719.88 ;
+ RECT 872.06 719.52 896.32 719.88 ;
+ RECT 897.9 719.52 920.8 719.88 ;
+ RECT 922.38 719.52 992.2 719.88 ;
+ RECT 0.62 0.98 0.76 719.74 ;
+ RECT 0.62 719.74 0.76 719.88 ;
+ RECT 0.76 719.74 3.7 719.88 ;
+ RECT 3.7 719.74 122.48 719.88 ;
+ RECT 0.62 0.62 0.76 0.76 ;
+ RECT 0.62 0.76 0.76 0.98 ;
+ RECT 0.76 0.62 3.7 0.76 ;
+ RECT 3.7 0.62 81.68 0.76 ;
+ RECT 3.7 0.76 81.68 0.98 ;
+ RECT 1093.06 0.98 1093.2 719.52 ;
+ RECT 1006.02 719.52 1090.12 719.74 ;
+ RECT 1006.02 719.74 1090.12 719.88 ;
+ RECT 1090.12 719.74 1093.06 719.88 ;
+ RECT 1093.06 719.52 1093.2 719.74 ;
+ RECT 1093.06 719.74 1093.2 719.88 ;
+ RECT 922.38 0.62 1090.12 0.76 ;
+ RECT 922.38 0.76 1090.12 0.98 ;
+ RECT 1090.12 0.62 1093.06 0.76 ;
+ RECT 1093.06 0.62 1093.2 0.76 ;
+ RECT 1093.06 0.76 1093.2 0.98 ;
+ RECT 1006.02 0.98 1086.72 4.16 ;
+ RECT 1006.02 4.16 1086.72 716.34 ;
+ RECT 1006.02 716.34 1086.72 719.52 ;
+ RECT 1086.72 0.98 1089.66 4.16 ;
+ RECT 1086.72 716.34 1089.66 719.52 ;
+ RECT 1089.66 0.98 1090.12 4.16 ;
+ RECT 1089.66 4.16 1090.12 716.34 ;
+ RECT 1089.66 716.34 1090.12 719.52 ;
+ RECT 3.7 0.98 4.16 4.16 ;
+ RECT 3.7 4.16 4.16 716.34 ;
+ RECT 3.7 716.34 4.16 719.74 ;
+ RECT 4.16 0.98 7.1 4.16 ;
+ RECT 4.16 716.34 7.1 719.74 ;
+ RECT 7.1 0.98 122.48 4.16 ;
+ RECT 7.1 4.16 122.48 716.34 ;
+ RECT 7.1 716.34 122.48 719.74 ;
+ END
+END sky130_sram_8kbyte_1rw1r_32x2048_8
+END LIBRARY
diff --git a/openlane/openram_testchip/config.tcl b/openlane/openram_testchip/config.tcl
new file mode 100644
index 0000000..e9e966a
--- /dev/null
+++ b/openlane/openram_testchip/config.tcl
@@ -0,0 +1,31 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) openram_testchip
+
+set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(VERILOG_FILES) "$script_dir/../../verilog/rtl/openram_testchip.v"
+#set ::env(BASE_SDC_FILE) "$script_dir/clks.sdc"
+
+set ::env(CLOCK_PORT) "la_clk"
+set ::env(CLOCK_NET) "clk"
+set ::env(CLOCK_PERIOD) "10"
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 800 2900"
+set ::env(DESIGN_IS_CORE) 0
+
+set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
+set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+
+#set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+#set ::env(SYNTH_NO_FLAT) 1
+set ::env(GLB_RT_ADJUSTMENT) 0.20
+set ::env(RUN_KLAYOUT_DRC) 0
+set ::env(PL_TARGET_DENSITY) 0.40
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 9e01907..e224270 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -30,7 +30,7 @@
$script_dir/../../verilog/rtl/user_project_wrapper.v "
## Clock configurations
-set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_PORT) "user_clock2"
set ::env(CLOCK_NET) "wb_clk_i"
set ::env(CLOCK_PERIOD) "10"
@@ -47,7 +47,7 @@
$script_dir/../../verilog/rtl/sram_1rw0r0w_32_256_sky130.v \
$script_dir/../../verilog/rtl/sram_1rw0r0w_32_512_sky130.v \
$script_dir/../../verilog/rtl/sram_1rw0r0w_64_512_sky130.v \
- $script_dir/../../verilog/rtl/testchip/openram_testchip.v "
+ $script_dir/../../verilog/rtl/openram_testchip.v "
set ::env(EXTRA_LEFS) "\
$script_dir/../../lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef \
@@ -86,15 +86,15 @@
set ::env(RUN_KLAYOUT_XOR) 0
# The following is because there are no std cells in the example wrapper project.
-set ::env(SYNTH_TOP_LEVEL) 1
-set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+#set ::env(SYNTH_TOP_LEVEL) 1
+#set ::env(PL_RANDOM_GLB_PLACEMENT) 1
-set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
-set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+#set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+#set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+#set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
+#set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
-set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(FILL_INSERTION) 0
-set ::env(TAP_DECAP_INSERTION) 0
+#set ::env(DIODE_INSERTION_STRATEGY) 0
+#set ::env(FILL_INSERTION) 0
+#set ::env(TAP_DECAP_INSERTION) 0
# set ::env(CLOCK_TREE_SYNTH) 0
diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
new file mode 100644
index 0000000..d363874
--- /dev/null
+++ b/verilog/rtl/openram_testchip.v
@@ -0,0 +1,376 @@
+`define WMASK_SIZE 4
+`define ADDR_SIZE 16
+`define DATA_SIZE 32
+`define SELECT_SIZE 4
+`define MAX_CHIPS 16
+`define PORT_SIZE `DATA_SIZE+`DATA_SIZE+`WMASK_SIZE+2
+`define TOTAL_SIZE 2*`PORT_SIZE + `SELECT_SIZE
+
+module openram_testchip(
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+ input reset,
+ // Select either GPIO or LA mode
+ input in_select,
+
+ input la_clk,
+ input la_sram_clk,
+ input la_in_load,
+ input la_sram_load,
+ input [`TOTAL_SIZE-1:0] la_data_in,
+ // GPIO bit to clock control register
+ input gpio_clk,
+ input gpio_in,
+ input gpio_sram_clk,
+ input gpio_scan,
+ input gpio_sram_load,
+
+ // SRAM data outputs to be captured
+ input [`DATA_SIZE-1:0] sram0_dout0,
+ input [`DATA_SIZE-1:0] sram0_dout1,
+ input [`DATA_SIZE-1:0] sram1_dout0,
+ input [`DATA_SIZE-1:0] sram1_dout1,
+ input [`DATA_SIZE-1:0] sram2_dout0,
+ input [`DATA_SIZE-1:0] sram2_dout1,
+ input [`DATA_SIZE-1:0] sram3_dout0,
+ input [`DATA_SIZE-1:0] sram3_dout1,
+ input [`DATA_SIZE-1:0] sram4_dout0,
+ input [`DATA_SIZE-1:0] sram4_dout1,
+ input [`DATA_SIZE-1:0] sram5_dout0,
+ input [`DATA_SIZE-1:0] sram5_dout1,
+ input [`DATA_SIZE-1:0] sram6_dout0,
+ input [`DATA_SIZE-1:0] sram6_dout1,
+ input [`DATA_SIZE-1:0] sram7_dout0,
+ input [`DATA_SIZE-1:0] sram7_dout1,
+ input [`DATA_SIZE-1:0] sram8_dout0,
+ input [`DATA_SIZE-1:0] sram8_dout1,
+ input [`DATA_SIZE-1:0] sram9_dout0,
+ input [`DATA_SIZE-1:0] sram9_dout1,
+ input [`DATA_SIZE-1:0] sram10_dout0,
+ input [`DATA_SIZE-1:0] sram10_dout1,
+ input [`DATA_SIZE-1:0] sram11_dout0,
+ input [`DATA_SIZE-1:0] sram11_dout1,
+ input [`DATA_SIZE-1:0] sram12_dout0,
+ input [`DATA_SIZE-1:0] sram12_dout1,
+ input [`DATA_SIZE-1:0] sram13_dout0,
+ input [`DATA_SIZE-1:0] sram13_dout1,
+ input [`DATA_SIZE-1:0] sram14_dout0,
+ input [`DATA_SIZE-1:0] sram14_dout1,
+ input [`DATA_SIZE-1:0] sram15_dout0,
+ input [`DATA_SIZE-1:0] sram15_dout1,
+
+ // Shared control/data to the SRAMs
+ output reg [`ADDR_SIZE-1:0] addr0,
+ output reg [`DATA_SIZE-1:0] din0,
+ output reg web0,
+ output reg [`WMASK_SIZE-1:0] wmask0,
+ output reg [`ADDR_SIZE-1:0] addr1,
+ output reg [`DATA_SIZE-1:0] din1,
+ output reg web1,
+ output reg [`WMASK_SIZE-1:0] wmask1,
+ // One CSB for each SRAM
+ output reg [`ADDR_SIZE-1:0] csb0,
+ output reg [`ADDR_SIZE-1:0] csb1,
+
+ // Clocks for each SRAM
+ output reg sram0_clk,
+ output reg sram1_clk,
+ output reg sram2_clk,
+ output reg sram3_clk,
+ output reg sram4_clk,
+ output reg sram5_clk,
+ output reg sram6_clk,
+ output reg sram7_clk,
+ output reg sram8_clk,
+ output reg sram9_clk,
+ output reg sram10_clk,
+ output reg sram11_clk,
+ output reg sram12_clk,
+ output reg sram13_clk,
+ output reg sram14_clk,
+ output reg sram15_clk,
+ output reg [`TOTAL_SIZE-1:0] la_data_out,
+ output reg gpio_out
+);
+
+ reg clk;
+ reg sram_clk;
+
+// Store input instruction
+ reg [`TOTAL_SIZE-1:0] sram_register;
+ reg csb0_temp;
+ reg csb1_temp;
+
+// Hold dout from SRAM
+// clocked by SRAM clk
+ reg [`DATA_SIZE-1:0] sram0_data0;
+ reg [`DATA_SIZE-1:0] sram0_data1;
+ reg [`DATA_SIZE-1:0] sram1_data0;
+ reg [`DATA_SIZE-1:0] sram1_data1;
+ reg [`DATA_SIZE-1:0] sram2_data0;
+ reg [`DATA_SIZE-1:0] sram2_data1;
+ reg [`DATA_SIZE-1:0] sram3_data0;
+ reg [`DATA_SIZE-1:0] sram3_data1;
+ reg [`DATA_SIZE-1:0] sram4_data0;
+ reg [`DATA_SIZE-1:0] sram4_data1;
+ reg [`DATA_SIZE-1:0] sram5_data0;
+ reg [`DATA_SIZE-1:0] sram5_data1;
+ reg [`DATA_SIZE-1:0] sram6_data0;
+ reg [`DATA_SIZE-1:0] sram6_data1;
+ reg [`DATA_SIZE-1:0] sram7_data0;
+ reg [`DATA_SIZE-1:0] sram7_data1;
+ reg [`DATA_SIZE-1:0] sram8_data0;
+ reg [`DATA_SIZE-1:0] sram8_data1;
+ reg [`DATA_SIZE-1:0] sram9_data0;
+ reg [`DATA_SIZE-1:0] sram9_data1;
+ reg [`DATA_SIZE-1:0] sram10_data0;
+ reg [`DATA_SIZE-1:0] sram10_data1;
+ reg [`DATA_SIZE-1:0] sram11_data0;
+ reg [`DATA_SIZE-1:0] sram11_data1;
+ reg [`DATA_SIZE-1:0] sram12_data0;
+ reg [`DATA_SIZE-1:0] sram12_data1;
+ reg [`DATA_SIZE-1:0] sram13_data0;
+ reg [`DATA_SIZE-1:0] sram13_data1;
+ reg [`DATA_SIZE-1:0] sram14_data0;
+ reg [`DATA_SIZE-1:0] sram14_data1;
+ reg [`DATA_SIZE-1:0] sram15_data0;
+ reg [`DATA_SIZE-1:0] sram15_data1;
+
+// Mux output to connect final output data
+// into sram_register
+ reg [`DATA_SIZE-1:0] read_data0;
+ reg [`DATA_SIZE-1:0] read_data1;
+
+// SRAM input connections
+ reg [`SELECT_SIZE-1:0] chip_select;
+
+//Selecting clock pin
+always @(*) begin
+ clk = in_select ? gpio_clk : la_clk;
+ sram_clk = in_select ? gpio_sram_clk : la_sram_clk;
+ sram0_clk = sram_clk;
+ sram1_clk = sram_clk;
+ sram2_clk = sram_clk;
+ sram3_clk = sram_clk;
+ sram4_clk = sram_clk;
+ sram5_clk = sram_clk;
+ sram6_clk = sram_clk;
+ sram7_clk = sram_clk;
+ sram8_clk = sram_clk;
+ sram9_clk = sram_clk;
+ sram10_clk = sram_clk;
+ sram11_clk = sram_clk;
+ sram12_clk = sram_clk;
+ sram13_clk = sram_clk;
+ sram14_clk = sram_clk;
+ sram15_clk = sram_clk;
+end
+
+always @ (posedge clk) begin
+ if(reset) begin
+ sram_register <= {`TOTAL_SIZE{1'b0}};
+ end
+ // GPIO scanning for transfer
+ else if(gpio_scan) begin
+ sram_register <= {sram_register[`TOTAL_SIZE-2:0], gpio_in};
+ end
+ // LA parallel load
+ else if(la_in_load) begin
+ sram_register <= la_data_in;
+ end
+ // Store results for read out
+ else if(gpio_sram_load || la_sram_load) begin
+ sram_register <= {sram_register[`TOTAL_SIZE-1:`TOTAL_SIZE-`SELECT_SIZE-`ADDR_SIZE-1],
+ read_data0,
+ sram_register[`ADDR_SIZE+`DATA_SIZE+2*`WMASK_SIZE+5:`DATA_SIZE+`WMASK_SIZE+3],
+ read_data1,
+ sram_register[`WMASK_SIZE+3:0]};
+ end
+end
+
+// Splitting register bits into fields
+always @(*) begin
+
+ // TODO: Use defines for these
+ chip_select = sram_register[`TOTAL_SIZE-1:108];
+
+ addr0 = sram_register[107:92];
+ din0 = sram_register[91:60];
+ csb0_temp = sram_register[59];
+ web0 = sram_register[58];
+ wmask0 = sram_register[57:54];
+
+ addr1 = sram_register[`PORT_SIZE-1:`DATA_SIZE+`WMASK_SIZE+2];
+ din1 = sram_register[`DATA_SIZE+`WMASK_SIZE+1:`WMASK_SIZE+2];
+ csb1_temp = sram_register[`WMASK_SIZE+1];
+ web1 = sram_register[`WMASK_SIZE];
+ wmask1 = sram_register[`WMASK_SIZE-1:0];
+end
+
+// Apply the correct CSB
+always @(*) begin
+ csb0 = csb0_temp << chip_select;
+ csb1 = csb1_temp << chip_select;
+end
+
+
+// Store dout of each SRAM
+always @(posedge sram_clk) begin
+ if(reset) begin
+ sram0_data0 <= 0;
+ sram0_data1 <= 0;
+ sram1_data0 <= 0;
+ sram1_data1 <= 0;
+ sram2_data0 <= 0;
+ sram2_data1 <= 0;
+ sram3_data0 <= 0;
+ sram3_data1 <= 0;
+ sram4_data0 <= 0;
+ sram4_data1 <= 0;
+ sram5_data0 <= 0;
+ sram5_data1 <= 0;
+ sram6_data0 <= 0;
+ sram6_data1 <= 0;
+ sram7_data0 <= 0;
+ sram7_data1 <= 0;
+ sram8_data0 <= 0;
+ sram8_data1 <= 0;
+ sram9_data0 <= 0;
+ sram9_data1 <= 0;
+ sram10_data0 <= 0;
+ sram10_data1 <= 0;
+ sram11_data0 <= 0;
+ sram11_data1 <= 0;
+ sram12_data0 <= 0;
+ sram12_data1 <= 0;
+ sram13_data0 <= 0;
+ sram13_data1 <= 0;
+ sram14_data0 <= 0;
+ sram14_data1 <= 0;
+ sram15_data0 <= 0;
+ sram15_data1 <= 0;
+ end
+ else begin
+ sram0_data0 <= sram0_dout0;
+ sram0_data1 <= sram0_dout1;
+ sram1_data0 <= sram1_dout0;
+ sram1_data1 <= sram1_dout1;
+ sram2_data0 <= sram2_dout0;
+ sram2_data1 <= sram2_dout1;
+ sram3_data0 <= sram3_dout0;
+ sram3_data1 <= sram3_dout1;
+ sram4_data0 <= sram4_dout0;
+ sram4_data1 <= sram4_dout1;
+ sram5_data0 <= sram5_dout0;
+ sram5_data1 <= sram5_dout1;
+ sram6_data0 <= sram6_dout0;
+ sram6_data1 <= sram6_dout1;
+ sram7_data0 <= sram7_dout0;
+ sram7_data1 <= sram7_dout1;
+ sram8_data0 <= sram8_dout0;
+ sram8_data1 <= sram8_dout1;
+ sram9_data0 <= sram9_dout0;
+ sram9_data1 <= sram9_dout1;
+ sram10_data0 <= sram10_dout0;
+ sram10_data1 <= sram10_dout1;
+ sram11_data0 <= sram11_dout0;
+ sram11_data1 <= sram11_dout1;
+ sram12_data0 <= sram12_dout0;
+ sram12_data1 <= sram12_dout1;
+ sram13_data0 <= sram13_dout0;
+ sram13_data1 <= sram13_dout1;
+ sram14_data0 <= sram14_dout0;
+ sram14_data1 <= sram14_dout1;
+ sram15_data0 <= sram15_dout0;
+ sram15_data1 <= sram15_dout1;
+ end
+end
+
+// Mux value of correct SRAM dout FF to feed into
+// DFF clocked by la/gpio clk
+always @ (*) begin
+ case(chip_select)
+ 4'd0: begin
+ read_data0 = sram0_dout0;
+ read_data1 = sram0_dout1;
+ end
+ 4'd1: begin
+ read_data0 = sram1_dout0;
+ read_data1 = sram1_dout1;
+ end
+ 4'd2: begin
+ read_data0 = sram2_dout0;
+ read_data1 = sram2_dout1;
+ end
+ 4'd3: begin
+ read_data0 = sram3_dout0;
+ read_data1 = sram3_dout1;
+ end
+ 4'd4: begin
+ read_data0 = sram4_dout0;
+ read_data1 = sram4_dout1;
+ end
+ 4'd5: begin
+ read_data0 = sram5_dout0;
+ read_data1 = sram5_dout1;
+ end
+ 4'd6: begin
+ read_data0 = sram6_dout0;
+ read_data1 = sram6_dout1;
+ end
+ 4'd7: begin
+ read_data0 = sram7_dout0;
+ read_data1 = sram7_dout1;
+ end
+ 4'd8: begin
+ read_data0 = sram8_dout0;
+ read_data1 = sram8_dout1;
+ end
+ 4'd9: begin
+ read_data0 = sram9_dout0;
+ read_data1 = sram9_dout1;
+ end
+ 4'd10: begin
+ read_data0 = sram10_dout0;
+ read_data1 = sram10_dout1;
+ end
+ 4'd11: begin
+ read_data0 = sram11_dout0;
+ read_data1 = sram11_dout1;
+ end
+ 4'd12: begin
+ read_data0 = sram12_dout0;
+ read_data1 = sram12_dout1;
+ end
+ 4'd13: begin
+ read_data0 = sram13_dout0;
+ read_data1 = sram13_dout1;
+ end
+ 4'd14: begin
+ read_data0 = sram14_dout0;
+ read_data1 = sram14_dout1;
+ end
+ 4'd15: begin
+ read_data0 = sram15_dout0;
+ read_data1 = sram15_dout1;
+ end
+ endcase
+end
+
+// Output logic
+always @ (*) begin
+ gpio_out = sram_register[`TOTAL_SIZE-1];
+ la_data_out = {16'd0, sram_register};
+end
+
+endmodule
+
+
diff --git a/verilog/rtl/openram_testchip_tb.v b/verilog/rtl/openram_testchip_tb.v
new file mode 100644
index 0000000..4b43c1d
--- /dev/null
+++ b/verilog/rtl/openram_testchip_tb.v
@@ -0,0 +1,212 @@
+`define assert(signal, value) \
+if (!(signal === value)) begin \
+ $display("ASSERTION FAILED in %m: signal != value"); \
+ $finish;\
+end
+
+`timescale 1ns/1ns
+
+`include "sky130_sram_1kbyte_1rw1r_32x256_8.v"
+`include "sram_1rw0r0w_32_256_sky130.v"
+`include "sram_1rw0r0w_32_512_sky130.v"
+`include "sram_1rw0r0w_32_1024_sky130.v"
+//`include "sram_1rw0r0w_64_512_sky130.v"
+`include "openram_testchip.v"
+
+module test_chip_tb;
+
+ reg la_clk;
+ reg gpio_clk;
+ reg la_sram_clk;
+ reg gpio_sram_clk;
+ reg reset;
+ reg la_in_load;
+ reg gpio_scan;
+ reg la_sram_load;
+ reg gpio_sram_load;
+ reg [111:0] la_bits;
+ reg gpio_bit;
+ reg in_select;
+ wire [31:0] sram0_rw_in;
+ wire [31:0] sram0_ro_in;
+ wire [31:0] sram1_rw_in;
+ wire [31:0] sram1_ro_in;
+ wire [31:0] sram2_rw_in;
+ wire [31:0] sram3_rw_in;
+ wire [31:0] sram4_rw_in;
+ //wire [63:0] sram5_rw_in;
+ wire [54:0] sram0_connections;
+ wire [54:0] sram1_connections;
+ wire [47:0] sram2_connections;
+ wire [45:0] sram3_connections;
+ wire [46:0] sram4_connections;
+ //wire [82:0] sram5_connections;
+ wire sram0_clk;
+ wire sram1_clk;
+ wire sram2_clk;
+ wire sram3_clk;
+ wire sram4_clk;
+ //wire sram5_clk;
+ wire [31:0] la_data0;
+ wire [31:0] la_data1;
+ wire gpio_data0;
+ wire gpio_data1;
+
+openram_testchip CONTROL_LOGIC(
+ .la_clk(la_clk),
+ .gpio_clk(gpio_clk),
+ .la_sram_clk(la_sram_clk),
+ .gpio_sram_clk(gpio_sram_clk),
+ .reset(reset),
+ .la_in_load(la_in_load),
+ .gpio_scan(gpio_scan),
+ .la_sram_load(la_sram_load),
+ .gpio_sram_load(gpio_sram_load),
+ .la_bits(la_bits),
+ .gpio_bit(gpio_bit),
+ .in_select(in_select),
+ .sram0_rw_in(sram0_rw_in),
+ .sram0_ro_in(sram0_ro_in),
+ .sram1_rw_in(sram1_rw_in),
+ .sram1_ro_in(sram1_ro_in),
+ .sram2_rw_in(sram2_rw_in),
+ .sram3_rw_in(sram3_rw_in),
+ .sram4_rw_in(sram4_rw_in),
+ //.sram5_rw_in(sram5_rw_out),
+ .sram0_connections(sram0_connections),
+ .sram1_connections(sram1_connections),
+ .sram2_connections(sram2_connections),
+ .sram3_connections(sram3_connections),
+ .sram4_connections(sram4_connections),
+ //.sram5_connections(sram5_connections),
+ .sram0_clk(sram0_clk),
+ .sram1_clk(sram1_clk),
+ .sram2_clk(sram2_clk),
+ .sram3_clk(sram3_clk),
+ .sram4_clk(sram4_clk),
+ //.sram5_clk(sram5_clk),
+ .la_data0(la_data0),
+ .la_data1(la_data1),
+ .gpio_data0(gpio_data0),
+ .gpio_data1(gpio_data1)
+);
+
+sky130_sram_1kbyte_1rw1r_32x256_8 SRAM0
+ (
+ .clk0 (sram0_clk),
+ .csb0 (sram0_connections[54]),
+ .web0 (sram0_connections[53]),
+ .wmask0 (sram0_connections[52:49]),
+ .addr0 (sram0_connections[48:41]),
+ .din0 (sram0_connections[40:9]),
+ .dout0 (sram0_rw_in),
+ .clk1 (sram0_clk),
+ .csb1 (sram0_connections[8]),
+ .addr1 (sram0_connections[7:0]),
+ .dout1 (sram0_ro_in));
+
+sky130_sram_1kbyte_1rw1r_32x256_8 SRAM1
+ (
+ .clk0 (sram1_clk),
+ .csb0 (sram1_connections[54]),
+ .web0 (sram1_connections[53]),
+ .wmask0 (sram1_connections[52:49]),
+ .addr0 (sram1_connections[48:41]),
+ .din0 (sram1_connections[40:9]),
+ .dout0 (sram1_rw_in),
+ .clk1 (sram1_clk),
+ .csb1 (sram1_connections[8]),
+ .addr1 (sram1_connections[7:0]),
+ .dout1 (sram1_ro_in));
+
+sram_1rw0r0w_32_1024_sky130 SRAM2
+ (
+ .clk0 (sram2_clk),
+ .csb0 (sram2_connections[47]),
+ .web0 (sram2_connections[46]),
+ .wmask0 (sram2_connections[45:42]),
+ .addr0 (sram2_connections[41:32]),
+ .din0 (sram2_connections[31:0]),
+ .dout0 (sram2_rw_in));
+
+sram_1rw0r0w_32_256_sky130 SRAM3
+ (
+ .clk0 (sram3_clk),
+ .csb0 (sram3_connections[45]),
+ .web0 (sram3_connections[44]),
+ .wmask0 (sram3_connections[43:40]),
+ .addr0 (sram3_connections[39:32]),
+ .din0 (sram3_connections[31:0]),
+ .dout0 (sram3_rw_in));
+
+sram_1rw0r0w_32_512_sky130 SRAM4
+ (
+ .clk0 (sram4_clk),
+ .csb0 (sram4_connections[46]),
+ .web0 (sram4_connections[45]),
+ .wmask0 (sram4_connections[44:41]),
+ .addr0 (sram4_connections[40:32]),
+ .din0 (sram4_connections[31:0]),
+ .dout0 (sram4_rw_in));
+
+/*
+sram_1rw0r0w_64_512_sky130 SRAM5
+ (
+ .clk0 (sram5_clk),
+ .csb0 (sram5_connections[82]),
+ .web0 (sram5_connections[81]),
+ .wmask0 (sram5_connections[80:73]),
+ .addr0 (sram5_connections[72:64]),
+ .din0 (sram5_connections[63:0]),
+ .dout0 (sram5_rw_in));
+*/
+
+initial begin
+ $dumpfile("testchip_tb.vcd");
+ $dumpvars(0, test_chip_tb);
+ la_clk = 1;
+ gpio_clk = 0;
+ la_sram_clk = 0;
+ gpio_sram_clk = 0;
+ gpio_scan = 0;
+ gpio_bit = 0;
+ reset = 0;
+
+ //Send bits using logic analyzer
+ in_select = 0;
+ la_in_load = 1;
+ la_sram_load = 0;
+ la_bits = {4'd0, 16'd1, 32'd1, 1'b0, 1'b0, 4'd15, 16'd0, 32'd0, 1'b1, 1'b1, 4'd0};
+
+ #10;
+ la_in_load = 0;
+ la_sram_load = 1;
+ la_sram_clk = 1;
+ #5;
+ la_sram_clk = 0;
+ #5;
+
+ la_in_load = 1;
+ la_sram_load = 0;
+ la_bits = {4'd0, 16'd1, 32'd0, 1'b0, 1'b1, 4'd0, 16'd0, 32'd0, 1'b1, 1'b1, 4'd0};
+
+ #10;
+ la_in_load = 0;
+ la_sram_load = 1;
+ la_sram_clk = 1;
+ #5;
+ la_sram_clk = 0;
+ #5;
+
+ la_sram_clk = 1;
+ #5;
+ la_sram_clk = 0;
+ #10;
+ `assert(la_data0, 32'd1);
+
+ #10;$finish;
+end
+
+always
+ #5 la_clk = !la_clk;
+endmodule
diff --git a/verilog/rtl/sky130_sram_1kbyte_1rw1r_8x1024_8.v b/verilog/rtl/sky130_sram_1kbyte_1rw1r_8x1024_8.v
new file mode 100644
index 0000000..ee2b1d6
--- /dev/null
+++ b/verilog/rtl/sky130_sram_1kbyte_1rw1r_8x1024_8.v
@@ -0,0 +1,108 @@
+// OpenRAM SRAM model
+// Words: 1024
+// Word size: 8
+// Write size: 8
+
+module sky130_sram_1kbyte_1rw1r_8x1024_8(
+`ifdef USE_POWER_PINS
+ vccd1,
+ vssd1,
+`endif
+// Port 0: RW
+ clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+ clk1,csb1,addr1,dout1
+ );
+
+ parameter NUM_WMASKS = 1 ;
+ parameter DATA_WIDTH = 8 ;
+ parameter ADDR_WIDTH = 10 ;
+ parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+ // FIXME: This delay is arbitrary.
+ parameter DELAY = 3 ;
+ parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+ parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+ inout vccd1;
+ inout vssd1;
+`endif
+ input clk0; // clock
+ input csb0; // active low chip select
+ input web0; // active low write control
+ input [NUM_WMASKS-1:0] wmask0; // write mask
+ input [ADDR_WIDTH-1:0] addr0;
+ input [DATA_WIDTH-1:0] din0;
+ output [DATA_WIDTH-1:0] dout0;
+ input clk1; // clock
+ input csb1; // active low chip select
+ input [ADDR_WIDTH-1:0] addr1;
+ output [DATA_WIDTH-1:0] dout1;
+
+ reg csb0_reg;
+ reg web0_reg;
+ reg [NUM_WMASKS-1:0] wmask0_reg;
+ reg [ADDR_WIDTH-1:0] addr0_reg;
+ reg [DATA_WIDTH-1:0] din0_reg;
+ reg [DATA_WIDTH-1:0] dout0;
+
+ // All inputs are registers
+ always @(posedge clk0)
+ begin
+ csb0_reg = csb0;
+ web0_reg = web0;
+ wmask0_reg = wmask0;
+ addr0_reg = addr0;
+ din0_reg = din0;
+ #(T_HOLD) dout0 = 8'bx;
+ if ( !csb0_reg && web0_reg && VERBOSE )
+ $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+ if ( !csb0_reg && !web0_reg && VERBOSE )
+ $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+ end
+
+ reg csb1_reg;
+ reg [ADDR_WIDTH-1:0] addr1_reg;
+ reg [DATA_WIDTH-1:0] dout1;
+
+ // All inputs are registers
+ always @(posedge clk1)
+ begin
+ csb1_reg = csb1;
+ addr1_reg = addr1;
+ if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+ $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+ #(T_HOLD) dout1 = 8'bx;
+ if ( !csb1_reg && VERBOSE )
+ $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+ end
+
+reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
+
+ // Memory Write Block Port 0
+ // Write Operation : When web0 = 0, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_WRITE0
+ if ( !csb0_reg && !web0_reg ) begin
+ if (wmask0_reg[0])
+ mem[addr0_reg][7:0] = din0_reg[7:0];
+ end
+ end
+
+ // Memory Read Block Port 0
+ // Read Operation : When web0 = 1, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_READ0
+ if (!csb0_reg && web0_reg)
+ dout0 <= #(DELAY) mem[addr0_reg];
+ end
+
+ // Memory Read Block Port 1
+ // Read Operation : When web1 = 1, csb1 = 0
+ always @ (negedge clk1)
+ begin : MEM_READ1
+ if (!csb1_reg)
+ dout1 <= #(DELAY) mem[addr1_reg];
+ end
+
+endmodule
diff --git a/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v b/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
new file mode 100644
index 0000000..7da4327
--- /dev/null
+++ b/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
@@ -0,0 +1,114 @@
+// OpenRAM SRAM model
+// Words: 512
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_2kbyte_1rw1r_32x512_8(
+`ifdef USE_POWER_PINS
+ vccd1,
+ vssd1,
+`endif
+// Port 0: RW
+ clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+ clk1,csb1,addr1,dout1
+ );
+
+ parameter NUM_WMASKS = 4 ;
+ parameter DATA_WIDTH = 32 ;
+ parameter ADDR_WIDTH = 9 ;
+ parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+ // FIXME: This delay is arbitrary.
+ parameter DELAY = 3 ;
+ parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+ parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+ inout vccd1;
+ inout vssd1;
+`endif
+ input clk0; // clock
+ input csb0; // active low chip select
+ input web0; // active low write control
+ input [NUM_WMASKS-1:0] wmask0; // write mask
+ input [ADDR_WIDTH-1:0] addr0;
+ input [DATA_WIDTH-1:0] din0;
+ output [DATA_WIDTH-1:0] dout0;
+ input clk1; // clock
+ input csb1; // active low chip select
+ input [ADDR_WIDTH-1:0] addr1;
+ output [DATA_WIDTH-1:0] dout1;
+
+ reg csb0_reg;
+ reg web0_reg;
+ reg [NUM_WMASKS-1:0] wmask0_reg;
+ reg [ADDR_WIDTH-1:0] addr0_reg;
+ reg [DATA_WIDTH-1:0] din0_reg;
+ reg [DATA_WIDTH-1:0] dout0;
+
+ // All inputs are registers
+ always @(posedge clk0)
+ begin
+ csb0_reg = csb0;
+ web0_reg = web0;
+ wmask0_reg = wmask0;
+ addr0_reg = addr0;
+ din0_reg = din0;
+ #(T_HOLD) dout0 = 32'bx;
+ if ( !csb0_reg && web0_reg && VERBOSE )
+ $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+ if ( !csb0_reg && !web0_reg && VERBOSE )
+ $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+ end
+
+ reg csb1_reg;
+ reg [ADDR_WIDTH-1:0] addr1_reg;
+ reg [DATA_WIDTH-1:0] dout1;
+
+ // All inputs are registers
+ always @(posedge clk1)
+ begin
+ csb1_reg = csb1;
+ addr1_reg = addr1;
+ if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+ $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+ #(T_HOLD) dout1 = 32'bx;
+ if ( !csb1_reg && VERBOSE )
+ $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+ end
+
+reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
+
+ // Memory Write Block Port 0
+ // Write Operation : When web0 = 0, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_WRITE0
+ if ( !csb0_reg && !web0_reg ) begin
+ if (wmask0_reg[0])
+ mem[addr0_reg][7:0] = din0_reg[7:0];
+ if (wmask0_reg[1])
+ mem[addr0_reg][15:8] = din0_reg[15:8];
+ if (wmask0_reg[2])
+ mem[addr0_reg][23:16] = din0_reg[23:16];
+ if (wmask0_reg[3])
+ mem[addr0_reg][31:24] = din0_reg[31:24];
+ end
+ end
+
+ // Memory Read Block Port 0
+ // Read Operation : When web0 = 1, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_READ0
+ if (!csb0_reg && web0_reg)
+ dout0 <= #(DELAY) mem[addr0_reg];
+ end
+
+ // Memory Read Block Port 1
+ // Read Operation : When web1 = 1, csb1 = 0
+ always @ (negedge clk1)
+ begin : MEM_READ1
+ if (!csb1_reg)
+ dout1 <= #(DELAY) mem[addr1_reg];
+ end
+
+endmodule
diff --git a/verilog/rtl/sky130_sram_4kbyte_1rw1r_32x1024_8.v b/verilog/rtl/sky130_sram_4kbyte_1rw1r_32x1024_8.v
new file mode 100644
index 0000000..e3d3e4d
--- /dev/null
+++ b/verilog/rtl/sky130_sram_4kbyte_1rw1r_32x1024_8.v
@@ -0,0 +1,114 @@
+// OpenRAM SRAM model
+// Words: 1024
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_4kbyte_1rw1r_32x1024_8(
+`ifdef USE_POWER_PINS
+ vccd1,
+ vssd1,
+`endif
+// Port 0: RW
+ clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+ clk1,csb1,addr1,dout1
+ );
+
+ parameter NUM_WMASKS = 4 ;
+ parameter DATA_WIDTH = 32 ;
+ parameter ADDR_WIDTH = 10 ;
+ parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+ // FIXME: This delay is arbitrary.
+ parameter DELAY = 3 ;
+ parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+ parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+ inout vccd1;
+ inout vssd1;
+`endif
+ input clk0; // clock
+ input csb0; // active low chip select
+ input web0; // active low write control
+ input [NUM_WMASKS-1:0] wmask0; // write mask
+ input [ADDR_WIDTH-1:0] addr0;
+ input [DATA_WIDTH-1:0] din0;
+ output [DATA_WIDTH-1:0] dout0;
+ input clk1; // clock
+ input csb1; // active low chip select
+ input [ADDR_WIDTH-1:0] addr1;
+ output [DATA_WIDTH-1:0] dout1;
+
+ reg csb0_reg;
+ reg web0_reg;
+ reg [NUM_WMASKS-1:0] wmask0_reg;
+ reg [ADDR_WIDTH-1:0] addr0_reg;
+ reg [DATA_WIDTH-1:0] din0_reg;
+ reg [DATA_WIDTH-1:0] dout0;
+
+ // All inputs are registers
+ always @(posedge clk0)
+ begin
+ csb0_reg = csb0;
+ web0_reg = web0;
+ wmask0_reg = wmask0;
+ addr0_reg = addr0;
+ din0_reg = din0;
+ #(T_HOLD) dout0 = 32'bx;
+ if ( !csb0_reg && web0_reg && VERBOSE )
+ $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+ if ( !csb0_reg && !web0_reg && VERBOSE )
+ $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+ end
+
+ reg csb1_reg;
+ reg [ADDR_WIDTH-1:0] addr1_reg;
+ reg [DATA_WIDTH-1:0] dout1;
+
+ // All inputs are registers
+ always @(posedge clk1)
+ begin
+ csb1_reg = csb1;
+ addr1_reg = addr1;
+ if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+ $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+ #(T_HOLD) dout1 = 32'bx;
+ if ( !csb1_reg && VERBOSE )
+ $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+ end
+
+reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
+
+ // Memory Write Block Port 0
+ // Write Operation : When web0 = 0, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_WRITE0
+ if ( !csb0_reg && !web0_reg ) begin
+ if (wmask0_reg[0])
+ mem[addr0_reg][7:0] = din0_reg[7:0];
+ if (wmask0_reg[1])
+ mem[addr0_reg][15:8] = din0_reg[15:8];
+ if (wmask0_reg[2])
+ mem[addr0_reg][23:16] = din0_reg[23:16];
+ if (wmask0_reg[3])
+ mem[addr0_reg][31:24] = din0_reg[31:24];
+ end
+ end
+
+ // Memory Read Block Port 0
+ // Read Operation : When web0 = 1, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_READ0
+ if (!csb0_reg && web0_reg)
+ dout0 <= #(DELAY) mem[addr0_reg];
+ end
+
+ // Memory Read Block Port 1
+ // Read Operation : When web1 = 1, csb1 = 0
+ always @ (negedge clk1)
+ begin : MEM_READ1
+ if (!csb1_reg)
+ dout1 <= #(DELAY) mem[addr1_reg];
+ end
+
+endmodule
diff --git a/verilog/rtl/sky130_sram_8kbyte_1rw1r_32x2048_8.v b/verilog/rtl/sky130_sram_8kbyte_1rw1r_32x2048_8.v
new file mode 100644
index 0000000..2875382
--- /dev/null
+++ b/verilog/rtl/sky130_sram_8kbyte_1rw1r_32x2048_8.v
@@ -0,0 +1,114 @@
+// OpenRAM SRAM model
+// Words: 2048
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_8kbyte_1rw1r_32x2048_8(
+`ifdef USE_POWER_PINS
+ vccd1,
+ vssd1,
+`endif
+// Port 0: RW
+ clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+ clk1,csb1,addr1,dout1
+ );
+
+ parameter NUM_WMASKS = 4 ;
+ parameter DATA_WIDTH = 32 ;
+ parameter ADDR_WIDTH = 11 ;
+ parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+ // FIXME: This delay is arbitrary.
+ parameter DELAY = 3 ;
+ parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+ parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+ inout vccd1;
+ inout vssd1;
+`endif
+ input clk0; // clock
+ input csb0; // active low chip select
+ input web0; // active low write control
+ input [NUM_WMASKS-1:0] wmask0; // write mask
+ input [ADDR_WIDTH-1:0] addr0;
+ input [DATA_WIDTH-1:0] din0;
+ output [DATA_WIDTH-1:0] dout0;
+ input clk1; // clock
+ input csb1; // active low chip select
+ input [ADDR_WIDTH-1:0] addr1;
+ output [DATA_WIDTH-1:0] dout1;
+
+ reg csb0_reg;
+ reg web0_reg;
+ reg [NUM_WMASKS-1:0] wmask0_reg;
+ reg [ADDR_WIDTH-1:0] addr0_reg;
+ reg [DATA_WIDTH-1:0] din0_reg;
+ reg [DATA_WIDTH-1:0] dout0;
+
+ // All inputs are registers
+ always @(posedge clk0)
+ begin
+ csb0_reg = csb0;
+ web0_reg = web0;
+ wmask0_reg = wmask0;
+ addr0_reg = addr0;
+ din0_reg = din0;
+ #(T_HOLD) dout0 = 32'bx;
+ if ( !csb0_reg && web0_reg && VERBOSE )
+ $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+ if ( !csb0_reg && !web0_reg && VERBOSE )
+ $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+ end
+
+ reg csb1_reg;
+ reg [ADDR_WIDTH-1:0] addr1_reg;
+ reg [DATA_WIDTH-1:0] dout1;
+
+ // All inputs are registers
+ always @(posedge clk1)
+ begin
+ csb1_reg = csb1;
+ addr1_reg = addr1;
+ if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+ $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+ #(T_HOLD) dout1 = 32'bx;
+ if ( !csb1_reg && VERBOSE )
+ $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+ end
+
+reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
+
+ // Memory Write Block Port 0
+ // Write Operation : When web0 = 0, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_WRITE0
+ if ( !csb0_reg && !web0_reg ) begin
+ if (wmask0_reg[0])
+ mem[addr0_reg][7:0] = din0_reg[7:0];
+ if (wmask0_reg[1])
+ mem[addr0_reg][15:8] = din0_reg[15:8];
+ if (wmask0_reg[2])
+ mem[addr0_reg][23:16] = din0_reg[23:16];
+ if (wmask0_reg[3])
+ mem[addr0_reg][31:24] = din0_reg[31:24];
+ end
+ end
+
+ // Memory Read Block Port 0
+ // Read Operation : When web0 = 1, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_READ0
+ if (!csb0_reg && web0_reg)
+ dout0 <= #(DELAY) mem[addr0_reg];
+ end
+
+ // Memory Read Block Port 1
+ // Read Operation : When web1 = 1, csb1 = 0
+ always @ (negedge clk1)
+ begin : MEM_READ1
+ if (!csb1_reg)
+ dout1 <= #(DELAY) mem[addr1_reg];
+ end
+
+endmodule
diff --git a/verilog/rtl/testchip/openram_testchip.v b/verilog/rtl/testchip/openram_testchip.v
deleted file mode 100644
index 470468f..0000000
--- a/verilog/rtl/testchip/openram_testchip.v
+++ /dev/null
@@ -1,128 +0,0 @@
-module openram_testchip(
- `ifdef USE_POWER_PINS
- inout vdda1, // User area 1 3.3V supply
- inout vdda2, // User area 2 3.3V supply
- inout vssa1, // User area 1 analog ground
- inout vssa2, // User area 2 analog ground
- inout vccd1, // User area 1 1.8V supply
- inout vccd2, // User area 2 1.8v supply
- inout vssd1, // User area 1 digital ground
- inout vssd2, // User area 2 digital ground
- `endif
- input clock,
- input reset,
- input [85:0] io_logical_analyzer_packet,
- input [55:0] io_gpio_packet,
- input io_in_select,
- input [31:0] io_sram0_rw_in,
- input [31:0] io_sram0_r0_in,
- input [31:0] io_sram1_rw_in,
- input [31:0] io_sram1_ro_in,
- input [31:0] io_sram2_rw_in,
- input [31:0] io_sram3_rw_in,
- input [31:0] io_sram4_rw_in,
- input [63:0] io_sram5_rw_in,
- output [54:0] io_sram0_connections,
- output [54:0] io_sram1_connections,
- output [47:0] io_sram2_connections,
- output [45:0] io_sram3_connections,
- output [46:0] io_sram4_connections,
- output [82:0] io_sram5_connections,
- output [63:0] io_sram_data
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [95:0] _RAND_0;
-`endif // RANDOMIZE_REG_INIT
- reg [85:0] input_; // @[openram_testchip.scala 30:20]
- wire [2:0] chip_select = input_[85:83]; // @[openram_testchip.scala 40:34]
- wire csb0 = input_[54]; // @[openram_testchip.scala 49:21]
- wire web = input_[53]; // @[openram_testchip.scala 50:20]
- wire _T = 3'h0 == chip_select; // @[Conditional.scala 37:30]
- wire _T_1 = 3'h1 == chip_select; // @[Conditional.scala 37:30]
- wire _T_2 = 3'h2 == chip_select; // @[Conditional.scala 37:30]
- wire _T_3 = 3'h3 == chip_select; // @[Conditional.scala 37:30]
- wire _T_4 = 3'h4 == chip_select; // @[Conditional.scala 37:30]
- wire _T_5 = 3'h5 == chip_select; // @[Conditional.scala 37:30]
- wire [82:0] _GEN_0 = _T_5 ? input_[82:0] : 83'h7ffffffffffffffffffff; // @[Conditional.scala 39:67 openram_testchip.scala 74:34 openram_testchip.scala 47:26]
- wire [46:0] _GEN_1 = _T_4 ? input_[46:0] : 47'h7fffffffffff; // @[Conditional.scala 39:67 openram_testchip.scala 70:34 openram_testchip.scala 46:26]
- wire [82:0] _GEN_2 = _T_4 ? 83'h7ffffffffffffffffffff : _GEN_0; // @[Conditional.scala 39:67 openram_testchip.scala 47:26]
- wire [45:0] _GEN_3 = _T_3 ? input_[45:0] : 46'h3fffffffffff; // @[Conditional.scala 39:67 openram_testchip.scala 66:34 openram_testchip.scala 45:26]
- wire [46:0] _GEN_4 = _T_3 ? 47'h7fffffffffff : _GEN_1; // @[Conditional.scala 39:67 openram_testchip.scala 46:26]
- wire [82:0] _GEN_5 = _T_3 ? 83'h7ffffffffffffffffffff : _GEN_2; // @[Conditional.scala 39:67 openram_testchip.scala 47:26]
- wire [47:0] _GEN_6 = _T_2 ? input_[47:0] : 48'hffffffffffff; // @[Conditional.scala 39:67 openram_testchip.scala 62:34 openram_testchip.scala 44:26]
- wire [45:0] _GEN_7 = _T_2 ? 46'h3fffffffffff : _GEN_3; // @[Conditional.scala 39:67 openram_testchip.scala 45:26]
- wire [46:0] _GEN_8 = _T_2 ? 47'h7fffffffffff : _GEN_4; // @[Conditional.scala 39:67 openram_testchip.scala 46:26]
- wire [82:0] _GEN_9 = _T_2 ? 83'h7ffffffffffffffffffff : _GEN_5; // @[Conditional.scala 39:67 openram_testchip.scala 47:26]
- wire [54:0] _GEN_10 = _T_1 ? input_[54:0] : 55'h7fffffffffffff; // @[Conditional.scala 39:67 openram_testchip.scala 58:34 openram_testchip.scala 43:26]
- wire [47:0] _GEN_11 = _T_1 ? 48'hffffffffffff : _GEN_6; // @[Conditional.scala 39:67 openram_testchip.scala 44:26]
- wire [45:0] _GEN_12 = _T_1 ? 46'h3fffffffffff : _GEN_7; // @[Conditional.scala 39:67 openram_testchip.scala 45:26]
- wire [46:0] _GEN_13 = _T_1 ? 47'h7fffffffffff : _GEN_8; // @[Conditional.scala 39:67 openram_testchip.scala 46:26]
- wire [82:0] _GEN_14 = _T_1 ? 83'h7ffffffffffffffffffff : _GEN_9; // @[Conditional.scala 39:67 openram_testchip.scala 47:26]
- wire [31:0] _io_sram_data_T = csb0 ? io_sram0_r0_in : io_sram0_rw_in; // @[openram_testchip.scala 84:36]
- wire [31:0] _io_sram_data_T_1 = csb0 ? io_sram1_ro_in : io_sram1_rw_in; // @[openram_testchip.scala 88:37]
- wire [63:0] _GEN_21 = _T_5 ? io_sram5_rw_in : 64'h0; // @[Conditional.scala 39:67 openram_testchip.scala 104:30 openram_testchip.scala 78:18]
- wire [63:0] _GEN_22 = _T_4 ? {{32'd0}, io_sram4_rw_in} : _GEN_21; // @[Conditional.scala 39:67 openram_testchip.scala 100:30]
- wire [63:0] _GEN_23 = _T_3 ? {{32'd0}, io_sram3_rw_in} : _GEN_22; // @[Conditional.scala 39:67 openram_testchip.scala 96:30]
- wire [63:0] _GEN_24 = _T_2 ? {{32'd0}, io_sram2_rw_in} : _GEN_23; // @[Conditional.scala 39:67 openram_testchip.scala 92:30]
- wire [63:0] _GEN_25 = _T_1 ? {{32'd0}, _io_sram_data_T_1} : _GEN_24; // @[Conditional.scala 39:67 openram_testchip.scala 88:30]
- wire [63:0] _GEN_26 = _T ? {{32'd0}, _io_sram_data_T} : _GEN_25; // @[Conditional.scala 40:58 openram_testchip.scala 84:30]
- assign io_sram0_connections = _T ? input_[54:0] : 55'h7fffffffffffff; // @[Conditional.scala 40:58 openram_testchip.scala 54:34 openram_testchip.scala 42:26]
- assign io_sram1_connections = _T ? 55'h7fffffffffffff : _GEN_10; // @[Conditional.scala 40:58 openram_testchip.scala 43:26]
- assign io_sram2_connections = _T ? 48'hffffffffffff : _GEN_11; // @[Conditional.scala 40:58 openram_testchip.scala 44:26]
- assign io_sram3_connections = _T ? 46'h3fffffffffff : _GEN_12; // @[Conditional.scala 40:58 openram_testchip.scala 45:26]
- assign io_sram4_connections = _T ? 47'h7fffffffffff : _GEN_13; // @[Conditional.scala 40:58 openram_testchip.scala 46:26]
- assign io_sram5_connections = _T ? 83'h7ffffffffffffffffffff : _GEN_14; // @[Conditional.scala 40:58 openram_testchip.scala 47:26]
- assign io_sram_data = web ? _GEN_26 : 64'h0; // @[openram_testchip.scala 80:14 openram_testchip.scala 78:18]
- always @(posedge clock) begin
- if (io_in_select) begin // @[openram_testchip.scala 38:17]
- input_ <= {{30'd0}, io_gpio_packet};
- end else begin
- input_ <= io_logical_analyzer_packet;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {3{`RANDOM}};
- input_ = _RAND_0[85:0];
-`endif // RANDOMIZE_REG_INIT
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
diff --git a/verilog/rtl/testchip/openram_testchip_tb.v b/verilog/rtl/testchip/openram_testchip_tb.v
deleted file mode 100644
index 5b4b3c9..0000000
--- a/verilog/rtl/testchip/openram_testchip_tb.v
+++ /dev/null
@@ -1,103 +0,0 @@
-`define assert(signal, value) \
-if (!(signal === value)) begin \
- $display("ASSERTION FAILED in %m: signal != value"); \
- $finish;\
-end
-
-`timescale 1ns/1ns
-
-//`include "control_logic.v"
-//`include "sky130_sram_1kbyte_1rw1r_32x256_8.v"
-`include "openram_testchip.v"
-
-module test_chip_tb;
-
-reg clk_in;
-reg rst;
-reg [55:0] from_analyzer;
-reg [55:0] from_gpio;
-reg in_select;
-
-wire [31:0] read_data;
-
-openram_testchip test_logic(.clk_in(clk_in),
- .rst(rst),
- .analyzer_packet(from_analyzer),
- .gpio_packet(from_gpio),
- .in_select(in_select),
- .sram_data(read_data)
-);
-
-initial begin
- $dumpfile("test_chip_tb.vcd");
- $dumpvars(0, test_chip_tb);
- clk_in = 1;
- rst = 0;
- //Send packet using logic analyzer
- in_select = 0;
- from_analyzer = 55'd0;
- from_gpio = 55'd0;
- //Write 1 to address 1 in SRAM 0
- from_analyzer = {1'b0, 1'b0, 1'b0, 4'd15, 8'd1, 32'd1, 1'b0, 8'd0};
- #10;
-
- //Disable write enable after write
- from_analyzer = {1'b0, 1'b0, 1'b1, 4'd15, 8'd1, 32'd1, 1'b0, 8'd0};
- #20;
-
- //Read from address 1 in SRAM 0
- from_analyzer = {1'b0, 1'b0, 1'b1, 4'd0, 8'd1, 32'd0, 1'b1, 8'd0};
- #25;
- `assert(read_data, 32'd1);
-
- //Send packet using GPIO pins
- in_select = 1;
- //Write 1 to address 1 in SRAM 0
- from_gpio = {1'b0, 1'b0, 1'b0, 4'd15, 8'd2, 32'd2, 1'b0, 8'd0};
- #10;
-
- //Disable write enable after write
- from_gpio = {1'b0, 1'b0, 1'b1, 4'd15, 8'd2, 32'd2, 1'b0, 8'd0};
- #20;
-
- //Read from address 1 in SRAM 0 using RO Port
- from_gpio = {1'b0, 1'b1, 1'b1, 4'd0, 8'd0, 32'd0, 1'b0, 8'd2};
- #40;
- `assert(read_data, 32'd2);
-
- in_select = 0;
- //Write 1 to address 1 in SRAM 1
- from_analyzer = {1'b1, 1'b0, 1'b0, 4'd15, 8'd1, 32'd1, 1'b0, 8'd0};
- #10
-
- //Disable write enable after write
- from_analyzer = {1'b1, 1'b0, 1'b1, 4'd15, 8'd1, 32'd1, 1'b0, 8'd0};
- #20;
-
- //Read from address 1 in SRAM 1
- from_analyzer = {1'b1, 1'b0, 1'b1, 4'd0, 8'd1, 32'd0, 1'b1, 8'd0};
- #40;
- `assert(read_data, 32'd1);
-
- //Send packet using GPIO pins
- in_select = 1;
- //Write 1 to address 1 in SRAM 1
- from_gpio = {1'b1, 1'b0, 1'b0, 4'd15, 8'd2, 32'd2, 1'b0, 8'd0};
- #10;
-
- //Disable write enable after write
- from_gpio = {1'b1, 1'b0, 1'b1, 4'd15, 8'd2, 32'd2, 1'b0, 8'd0};
- #20;
-
- //Read from address 1 in SRAM 1 using RO Port
- from_gpio = {1'b1, 1'b1, 1'b1, 4'd0, 8'd0, 32'd0, 1'b0, 8'd2};
- #40;
- `assert(read_data, 32'd2);
-
- #30;$finish;
-end
-
-always
- #5 clk_in = !clk_in;
-
-endmodule
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 22d4e46..986b543 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -78,12 +78,12 @@
output [2:0] user_irq
);
-wire [54:0] sram0_connections;
-wire [54:0] sram1_connections;
-wire [47:0] io_sram2_connections;
-wire [45:0] io_sram3_connections;
-wire [46:0] io_sram4_connections;
-wire [82:0] io_sram5_connections;
+wire [55:0] sram0_connections;
+wire [55:0] sram1_connections;
+wire [48:0] io_sram2_connections;
+wire [46:0] io_sram3_connections;
+wire [47:0] io_sram4_connections;
+wire [83:0] io_sram5_connections;
wire [31:0] sram0_rw_out;
@@ -95,121 +95,344 @@
wire [31:0] sram4_rw_out;
wire [63:0] sram5_rw_out;
+
+
+
openram_testchip CONTROL_LOGIC(
- .clock(wb_clk_i),
- .reset(wb_rst_i),
- .io_logical_analyzer_packet(la_data_in[85:0]),
- .io_gpio_packet(la_data_in[85:0]),
- .io_in_select(la_data_in[86]),
- .io_sram0_rw_in(sram0_rw_out),
- .io_sram0_r0_in(sram0_ro_out),
- .io_sram1_rw_in(sram1_rw_out),
- .io_sram1_ro_in(sram1_ro_out),
- .io_sram2_rw_in(sram2_rw_out),
- .io_sram3_rw_in(sram3_rw_out),
- .io_sram4_rw_in(sram4_rw_out),
- .io_sram5_rw_in(sram5_rw_out),
- .io_sram0_connections(sram0_connections),
- .io_sram1_connections(sram1_connections),
- .io_sram2_connections(sram2_connections),
- .io_sram3_connections(sram3_connections),
- .io_sram4_connections(sram4_connections),
- .io_sram5_connections(sram5_connections),
- .io_sram_data(la_data_out[63:0])
+ .reset(wb_rst_i),
+ .in_select(io_in[0]),
+ .gpio_clk(io_in[1]),
+ .gpio_sram_clk(io_in[2]),
+ .gpio_scan(io_in[3]),
+ .gpio_sram_load(io_in[4]),
+ .la_clk(la_data_in[127]),
+ .la_sram_clk(la_data_in[126]),
+ .la_in_load(la_data_in[125]),
+ .la_sram_load(la_data_in[124]),
+ .la_data_in(la_data_in[111:0]),
+ .la_data_out(la_data_out[111:0]),
+ .gpio_out(io_out[0]),
+
+ // Shared control/data to the SRAMs
+ .addr0(addr0),
+ .din0(din0),
+ .web0(web0),
+ .wmask0(wmask0),
+ .addr1(addr1),
+ .web1(web1),
+ .wmask1(wmask1),
+
+ // One CSB for each SRAM
+ .csb0(csb0)
+ .csb1(csb1)
+
+ // Clocks for each SRAM
+ .sram0_clk(sram0_clk),
+ .sram1_clk(sram1_clk),
+ .sram2_clk(sram2_clk),
+ .sram3_clk(sram3_clk),
+ .sram4_clk(sram4_clk),
+ .sram5_clk(sram5_clk),
+ .sram6_clk(sram6_clk),
+ .sram7_clk(sram7_clk),
+ .sram8_clk(sram8_clk),
+ .sram9_clk(sram9_clk),
+ .sram10_clk(sram10_clk),
+ .sram11_clk(sram11_clk),
+ .sram12_clk(sram12_clk),
+ .sram13_clk(sram13_clk),
+ .sram14_clk(sram14_clk),
+ .sram15_clk(sram15_clk),
+
+ // SRAM data outputs to be captured
+ .sram0_dout0(sram0_dout0),
+ .sram0_dout1(sram0_dout1),
+ .sram1_dout0(sram1_dout0),
+ .sram1_dout1(sram1_dout1),
+ .sram2_dout0(sram2_dout0),
+ .sram2_dout1(sram2_dout1),
+ .sram3_dout0(sram3_dout0),
+ .sram3_dout1(sram3_dout1),
+ .sram4_dout0(sram4_dout0),
+ .sram4_dout1(sram4_dout1),
+ .sram5_dout0(sram5_dout0),
+ .sram5_dout1(sram5_dout1),
+ .sram6_dout0(sram6_dout0),
+ .sram6_dout1(sram6_dout1),
+ .sram7_dout0(sram7_dout0),
+ .sram7_dout1(sram7_dout1),
+ .sram8_dout0(sram8_dout0),
+ .sram8_dout1(sram8_dout1),
+ .sram9_dout0(sram9_dout0),
+ .sram9_dout1(sram9_dout1),
+ .sram10_dout0(sram10_dout0),
+ .sram10_dout1(sram10_dout1),
+ .sram11_dout0(sram11_dout0),
+ .sram11_dout1(sram11_dout1),
+ .sram12_dout0(sram12_dout0),
+ .sram12_dout1(sram12_dout1),
+ .sram13_dout0(sram13_dout0),
+ .sram13_dout1(sram13_dout1),
+ .sram14_dout0(sram14_dout0),
+ .sram14_dout1(sram14_dout1),
+ .sram15_dout0(sram15_dout0),
+ .sram15_dout1(sram15_dout1),
+
+
);
-sky130_sram_1kbyte_1rw1r_32x256_8 SRAM0
+ wire [31:0] din0;
+ wire web0;
+ wire [3:0] wmask0;
+ wire [15:0] addr1;
+ wire [31:0] din1;
+ wire web1;
+ wire [3:0] wmask1;
+
+ wire [15:0] csb0;
+ wire [15:0] csb1;
+
+ wire [31:0] sram0_dout0;
+ wire [31:0] sram0_dout1;
+ wire [31:0] sram1_dout0;
+ wire [31:0] sram1_dout1;
+ wire [31:0] sram2_dout0;
+ wire [31:0] sram2_dout1;
+ wire [31:0] sram3_dout0;
+ wire [31:0] sram3_dout1;
+ wire [31:0] sram4_dout0;
+ wire [31:0] sram4_dout1;
+ wire [31:0] sram5_dout0;
+ wire [31:0] sram5_dout1;
+ wire [31:0] sram6_dout0;
+ wire [31:0] sram6_dout1;
+ wire [31:0] sram7_dout0;
+ wire [31:0] sram7_dout1;
+ wire [31:0] sram8_dout0;
+ wire [31:0] sram8_dout1;
+ wire [31:0] sram9_dout0;
+ wire [31:0] sram9_dout1;
+ wire [31:0] sram10_dout0;
+ wire [31:0] sram10_dout1;
+ wire [31:0] sram11_dout0;
+ wire [31:0] sram11_dout1;
+ wire [31:0] sram12_dout0;
+ wire [31:0] sram12_dout1;
+ wire [31:0] sram13_dout0;
+ wire [31:0] sram13_dout1;
+ wire [31:0] sram14_dout0;
+ wire [31:0] sram14_dout1;
+ wire [31:0] sram15_dout0;
+ wire [31:0] sram15_dout1;
+
+
+// Not working yet
+// sky130_sram_1kbyte_1r1w_8x1024_8 SRAM0
+// (
+// `ifdef USE_POWER_PINS
+// .vccd1(vccd1),
+// .vssd1(vssd1),
+// `endif
+// .clk0 (sram0_clk),
+// .csb0 (csb0[0]),
+// .web0 (web0),
+// .wmask0 (wmask0),
+// .addr0 (addr0),
+// .din0 (din0),
+// .dout0 (sram0_dout0[7:0]),
+// .clk1 (sram0_clk),
+// .csb1 (csb1[0]),
+// .addr1 (addr1),
+// .dout1 (sram0_dout1[7:0])
+// );
+// assign sram0_dout0 = 0;
+// assign sram0_dout1[31:8] = 0;
+
+
+sky130_sram_1kbyte_1rw1r_8x1024_8 SRAM1
(
-
`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
- .clk0 (wb_clk_i),
- .csb0 (sram0_connections[54]),
- .web0 (sram0_connections[53]),
- .wmask0 (sram0_connections[52:49]),
- .addr0 (sram0_connections[48:41]),
- .din0 (sram0_connections[40:9]),
- .dout0 (sram0_rw_out),
- .clk1 (wb_clk_i),
- .csb1 (sram0_connections[8]),
- .addr1 (sram0_connections[7:0]),
- .dout1 (sram0_ro_out));
-
-sky130_sram_1kbyte_1rw1r_32x256_8 SRAM1
+ .clk0 (sram1_clk),
+ .csb0 (csb0[1]),
+ .web0 (web0),
+ .wmask0 (wmask0),
+ .addr0 (addr0),
+ .din0 (din0),
+ .dout0 (sram1_dout0[7:0]),
+ .clk1 (sram1_clk),
+ .csb1 (csb1[1]),
+ .addr1 (addr1),
+ .dout1 (sram1_dout1[7:0])
+ );
+ assign sram1_dout0[31:8] = 0;
+ assign sram1_dout1[31:8] = 0;
+
+sky130_sram_1kbyte_1rw1r_32x256_8 SRAM2
(
- `ifdef USE_POWER_PINS
+ `ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
- .clk0 (wb_clk_i),
- .csb0 (sram1_connections[54]),
- .web0 (sram1_connections[53]),
- .wmask0 (sram1_connections[52:49]),
- .addr0 (sram1_connections[48:41]),
- .din0 (sram1_connections[40:9]),
- .dout0 (sram1_rw_out),
- .clk1 (wb_clk_i),
- .csb1 (sram1_connections[8]),
- .addr1 (sram1_connections[7:0]),
- .dout1 (sram1_ro_out));
+ .clk0 (sram2_clk),
+ .csb0 (csb0[2]),
+ .web0 (web0),
+ .wmask0 (wmask0),
+ .addr0 (addr0),
+ .din0 (din0),
+ .dout0 (sram2_dout0),
+ .clk1 (sram2_clk),
+ .csb1 (csb1[2]),
+ .addr1 (addr1),
+ .dout1 (sram2_dout1)
+ );
+
+sky130_sram_2kbyte_1rw1r_32x512_8 SRAM3
+ (p
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ `endif
+ .clk0 (sram3_clk),
+ .csb0 (csb0[3]),
+ .web0 (web0),
+ .wmask0 (wmask0),
+ .addr0 (addr0),
+ .din0 (din0),
+ .dout0 (sram3_dout0),
+ .clk1 (sram3_clk),
+ .csb1 (csb1[3]),
+ .addr1 (addr1),
+ .dout1 (sram3_dout1)
+ );
-sram_1rw0r0w_32_1024_sky130 SRAM2
+sky130_sram_4kbyte_1rw1r_32x1024_8 SRAM4
+ (
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ `endif
+ .clk0 (sram4_clk),
+ .csb0 (csb0[4]),
+ .web0 (web0),
+ .wmask0 (wmask0),
+ .addr0 (addr0),
+ .din0 (din0),
+ .dout0 (sram4_dout0),
+ .clk1 (sram4_clk),
+ .csb1 (csb1[4]),
+ .addr1 (addr1),
+ .dout1 (sram4_dout1)
+ );
+
+sky130_sram_8kbyte_1rw1r_32x2048_8 SRAM5
+ (
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ `endif
+ .clk0 (sram5_clk),
+ .csb0 (csb0[5]),
+ .web0 (web0),
+ .wmask0 (wmask0),
+ .addr0 (addr0),
+ .din0 (din0),
+ .dout0 (sram5_dout0),
+ .clk1 (sram5_clk),
+ .csb1 (csb1[5]),
+ .addr1 (addr1),
+ .dout1 (sram5_dout1)
+ );
+
+// Not working yet
+// sky130_sram_16kbyte_1rw1r_32x4096_8 SRAM6
+// (
+// `ifdef USE_POWER_PINS
+// .vccd1(vccd1),
+// .vssd1(vssd1),
+// `endif
+// .clk0 (sram6_clk),
+// .csb0 (csb0[6]),
+// .web0 (web0),
+// .wmask0 (wmask0),
+// .addr0 (addr0),
+// .din0 (din0),
+// .dout0 (sram6_dout0),
+// .clk1 (sram6_clk),
+// .csb1 (csb1[6]),
+// .addr1 (addr1),
+// .dout1 (sram6_dout1)
+// );
+
+
+
+// Single port memories
+sram_1rw0r0w_32_256_sky130 SRAM8
(
`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
- .clk0 (wb_clk_i),
- .csb0 (sram2_connections[47]),
- .web0 (sram2_connections[46]),
- .wmask0 (sram2_connections[45:42]),
- .addr0 (sram2_connections[41:32]),
- .din0 (sram2_connections[31:0]),
- .dout0 (sram2_rw_out));
+ .clk0 (sram8_clk),
+ .csb0 (csb0[8]),
+ .web0 (web0),
+ .wmask0 (wmask0),
+ .addr0 (addr0),
+ .din0 (din0),
+ .dout0 (sram8_dout0)
+ );
+ assign sram8_dout1 = 0;
-sram_1rw0r0w_32_256_sky130 SRAM3
+sram_1rw0r0w_32_512_sky130 SRAM9
(
`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
- .clk0 (wb_clk_i),
- .csb0 (sram3_connections[45]),
- .web0 (sram3_connections[44]),
- .wmask0 (sram3_connections[43:40]),
- .addr0 (sram3_connections[39:32]),
- .din0 (sram3_connections[31:0]),
- .dout0 (sram3_rw_out));
+ .clk0 (sram9_clk),
+ .csb0 (csb0[9]),
+ .web0 (web0),
+ .wmask0 (wmask0),
+ .addr0 (addr0),
+ .din0 (din0),
+ .dout0 (sram9_dout0)
+ );
+ assign sram9_dout1 = 0;
-sram_1rw0r0w_32_512_sky130 SRAM4
+sram_1rw0r0w_32_1024_sky130 SRAM10
(
`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
- .clk0 (wb_clk_i),
- .csb0 (sram4_connections[46]),
- .web0 (sram4_connections[45]),
- .wmask0 (sram4_connections[44:41]),
- .addr0 (sram4_connections[40:32]),
- .din0 (sram4_connections[31:0]),
- .dout0 (sram4_rw_out));
+ .clk0 (sram10_clk),
+ .csb0 (csb0[10]),
+ .web0 (web0),
+ .wmask0 (wmask0),
+ .addr0 (addr0),
+ .din0 (din0),
+ .dout0 (sram10_dout0)
+ );
+ assign sram10_dout1 = 0;
-sram_1rw0r0w_64_512_sky130 SRAM5
+sram_1rw0r0w_64_512_sky130 SRAM11
(
`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
- .clk0 (wb_clk_i),
- .csb0 (sram5_connections[82]),
- .web0 (sram5_connections[81]),
- .wmask0 (sram5_connections[80:73]),
- .addr0 (sram5_connections[72:64]),
- .din0 (sram5_connections[63:0]),
- .dout0 (sram5_rw_out));
+ .clk0 (sram11_clk),
+ .csb0 (csb0[11]),
+ .web0 (web0),
+ .wmask0 (wmask0),
+ .addr0 (addr0),
+ .din0 (din0),
+ .dout0 (sram11_dout0)
+ );
+ assign sram11_dout1 = 0;
+
endmodule // user_project_wrapper
