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foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
31eb2d306d7238f60f14d4bbf86b2f329e8dd094
commit
31eb2d306d7238f60f14d4bbf86b2f329e8dd094
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log
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[
tgz
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author
AmoghLonkar <alonkar@ucsc.edu>
Tue Jun 15 08:58:12 2021 -0700
committer
AmoghLonkar <alonkar@ucsc.edu>
Tue Jun 15 08:58:12 2021 -0700
tree
a434e88fbd1b0c0f9eb5a88d575937594e5f3ccf
parent
e8af1ae7e97c8effb684c65c0781df3bd711c283
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diff
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Proper address wire connection
verilog/rtl/user_project_wrapper.v
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diff
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1 file changed
tree: a434e88fbd1b0c0f9eb5a88d575937594e5f3ccf
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
single_port/
spi/
verilog/
caravel
.gitignore
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info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.