)]}'
{
  "commit": "31eb2d306d7238f60f14d4bbf86b2f329e8dd094",
  "tree": "a434e88fbd1b0c0f9eb5a88d575937594e5f3ccf",
  "parents": [
    "e8af1ae7e97c8effb684c65c0781df3bd711c283"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Tue Jun 15 08:58:12 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Tue Jun 15 08:58:12 2021 -0700"
  },
  "message": "Proper address wire connection\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ec805909fa90de117b5c2ffc7f0f43bd913a6dc8",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "aa559a25b71e2d06c6a300e6dff81775502134c9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}