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foss-eda-tools/third_party/shuttle/sky130/mpw-002/slot-009/2ff0e708301352793a6067ed209e4b71fa1368ca^!/.
commit
2ff0e708301352793a6067ed209e4b71fa1368ca
[log]
author
mrg <mrg@ucsc.edu>
Thu Jun 17 20:10:54 2021 -0700
committer
mrg <mrg@ucsc.edu>
Thu Jun 17 20:10:54 2021 -0700
tree
39a5bc20135567cd46e68fdd80fea41e07b203a8
parent
328535ddf6f75a5eff359e00df136a97e734e325 [diff]
Code cleanup

diff --git a/verilog/rtl/openram_defines.v b/verilog/rtl/openram_defines.v
index 4c65502..67fc5f0 100644
--- a/verilog/rtl/openram_defines.v
+++ b/verilog/rtl/openram_defines.v

@@ -5,3 +5,19 @@
 `define MAX_CHIPS 16
 `define PORT_SIZE `ADDR_SIZE+`DATA_SIZE+`WMASK_SIZE+2
 `define TOTAL_SIZE `PORT_SIZE+`PORT_SIZE+`SELECT_SIZE
+
+
+
+// packet order:
+
+// 4 chip_select
+// 16 addr0
+// 32 din0
+// 1 csb0
+// 1 web0
+// 4 wmask0
+// 16 addr1
+// 32 din1
+// 1 csb1
+// 1 web1
+// 4 wmask1

diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
index c3622d0..a8cc3d9 100644
--- a/verilog/rtl/openram_testchip.v
+++ b/verilog/rtl/openram_testchip.v

@@ -103,7 +103,7 @@
 
       sram_register <= {sram_register[`TOTAL_SIZE-1:`TOTAL_SIZE-`SELECT_SIZE-`ADDR_SIZE],
 			read_data0,
-			sram_register[`ADDR_SIZE+`DATA_SIZE+2*`WMASK_SIZE+3:`DATA_SIZE+`WMASK_SIZE+2],
+			sram_register[`ADDR_SIZE+`DATA_SIZE+`WMASK_SIZE+`WMASK_SIZE+3:`DATA_SIZE+`WMASK_SIZE+2],
 			read_data1,
 			sram_register[`WMASK_SIZE+1:0]};
    end
@@ -114,7 +114,7 @@
 always @(*) begin
    chip_select = sram_register[`TOTAL_SIZE-1:`TOTAL_SIZE-`SELECT_SIZE];
 
-   addr0 = sram_register[`TOTAL_SIZE-`SELECT_SIZE-1:`TOTAL_SIZE-`SELECT_SIZE-`ADDR_SIZE];
+   addr0 = sram_register[`ADDR_SIZE+`DATA_SIZE+`PORT_SIZE+`WMASK_SIZE+1:`DATA_SIZE+`PORT_SIZE+`WMASK_SIZE+2];
    din0 = sram_register[`DATA_SIZE+`PORT_SIZE+`WMASK_SIZE+1:`PORT_SIZE+`WMASK_SIZE+2];
    csb0_temp = global_csb | sram_register[`PORT_SIZE+`WMASK_SIZE+1];
    web0 = sram_register[`PORT_SIZE+`WMASK_SIZE];

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 9e1fbee..c912cef 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v

@@ -80,6 +80,8 @@
 );
 
 
+   assign la_data_out[127:112] = 0;
+
    // Shared control/data to the SRAMs
    wire [`ADDR_SIZE-1:0] addr0;
    wire [`DATA_SIZE-1:0] din0;
@@ -192,28 +194,28 @@
    wire [`DATA_SIZE-1:0]  sram3_dout1;
    wire [`DATA_SIZE-1:0]  sram4_dout0;
    wire [`DATA_SIZE-1:0]  sram4_dout1;
-   wire [`DATA_SIZE-1:0]  sram5_dout0;
-   wire [`DATA_SIZE-1:0]  sram5_dout1;
-   wire [`DATA_SIZE-1:0]  sram6_dout0;
-   wire [`DATA_SIZE-1:0]  sram6_dout1;
-   wire [`DATA_SIZE-1:0]  sram7_dout0;
-   wire [`DATA_SIZE-1:0]  sram7_dout1;
+   wire [`DATA_SIZE-1:0]  sram5_dout0 = 0;
+   wire [`DATA_SIZE-1:0]  sram5_dout1 = 0;
+   wire [`DATA_SIZE-1:0]  sram6_dout0 = 0;
+   wire [`DATA_SIZE-1:0]  sram6_dout1 = 0;
+   wire [`DATA_SIZE-1:0]  sram7_dout0 = 0;
+   wire [`DATA_SIZE-1:0]  sram7_dout1 = 0;
    wire [`DATA_SIZE-1:0]  sram8_dout0;
-   wire [`DATA_SIZE-1:0]  sram8_dout1;
+   wire [`DATA_SIZE-1:0]  sram8_dout1 = 0;
    wire [`DATA_SIZE-1:0]  sram9_dout0;
-   wire [`DATA_SIZE-1:0]  sram9_dout1;
+   wire [`DATA_SIZE-1:0]  sram9_dout1 = 0;
    wire [`DATA_SIZE-1:0]  sram10_dout0;
-   wire [`DATA_SIZE-1:0]  sram10_dout1;
+   wire [`DATA_SIZE-1:0]  sram10_dout1 = 0;
    wire [`DATA_SIZE-1:0]  sram11_dout0;
-   wire [`DATA_SIZE-1:0]  sram11_dout1;
-   wire [`DATA_SIZE-1:0]  sram12_dout0;
-   wire [`DATA_SIZE-1:0]  sram12_dout1;
-   wire [`DATA_SIZE-1:0]  sram13_dout0;
-   wire [`DATA_SIZE-1:0]  sram13_dout1;
-   wire [`DATA_SIZE-1:0]  sram14_dout0;
-   wire [`DATA_SIZE-1:0]  sram14_dout1;
-   wire [`DATA_SIZE-1:0]  sram15_dout0;
-   wire [`DATA_SIZE-1:0]  sram15_dout1;
+   wire [`DATA_SIZE-1:0]  sram11_dout1 = 0;
+   wire [`DATA_SIZE-1:0]  sram12_dout0 = 0;
+   wire [`DATA_SIZE-1:0]  sram12_dout1 = 0;
+   wire [`DATA_SIZE-1:0]  sram13_dout0 = 0;
+   wire [`DATA_SIZE-1:0]  sram13_dout1 = 0;
+   wire [`DATA_SIZE-1:0]  sram14_dout0 = 0;
+   wire [`DATA_SIZE-1:0]  sram14_dout1 = 0;
+   wire [`DATA_SIZE-1:0]  sram15_dout0 = 0;
+   wire [`DATA_SIZE-1:0]  sram15_dout1 = 0;
 
 sky130_sram_1kbyte_1rw1r_8x1024_8 SRAM0
      (
@@ -410,28 +412,28 @@
    reg [`DATA_SIZE-1:0] sram3_data1;
    reg [`DATA_SIZE-1:0] sram4_data0;
    reg [`DATA_SIZE-1:0] sram4_data1;
-   //reg [`DATA_SIZE-1:0] sram5_data0;
-   //reg [`DATA_SIZE-1:0] sram5_data1;
-   //reg [`DATA_SIZE-1:0] sram6_data0;
-   //reg [`DATA_SIZE-1:0] sram6_data1;
-   //reg [`DATA_SIZE-1:0] sram7_data0;
-   //reg [`DATA_SIZE-1:0] sram7_data1;
+   reg [`DATA_SIZE-1:0] sram5_data0;
+   reg [`DATA_SIZE-1:0] sram5_data1;
+   reg [`DATA_SIZE-1:0] sram6_data0;
+   reg [`DATA_SIZE-1:0] sram6_data1;
+   reg [`DATA_SIZE-1:0] sram7_data0;
+   reg [`DATA_SIZE-1:0] sram7_data1;
    reg [`DATA_SIZE-1:0] sram8_data0;
-   //reg [`DATA_SIZE-1:0] sram8_data1;
+   reg [`DATA_SIZE-1:0] sram8_data1;
    reg [`DATA_SIZE-1:0] sram9_data0;
-   //reg [`DATA_SIZE-1:0] sram9_data1;
+   reg [`DATA_SIZE-1:0] sram9_data1;
    reg [`DATA_SIZE-1:0] sram10_data0;
-   //reg [`DATA_SIZE-1:0] sram10_data1;
+   reg [`DATA_SIZE-1:0] sram10_data1;
    reg [`DATA_SIZE-1:0] sram11_data0;
-   //reg [`DATA_SIZE-1:0] sram11_data1;
-   //reg [`DATA_SIZE-1:0] sram12_data0;
-   //reg [`DATA_SIZE-1:0] sram12_data1;
-   //reg [`DATA_SIZE-1:0] sram13_data0;
-   //reg [`DATA_SIZE-1:0] sram13_data1;
-   //reg [`DATA_SIZE-1:0] sram14_data0;
-   //reg [`DATA_SIZE-1:0] sram14_data1;
-   //reg [`DATA_SIZE-1:0] sram15_data0;
-   //reg [`DATA_SIZE-1:0] sram15_data1;
+   reg [`DATA_SIZE-1:0] sram11_data1;
+   reg [`DATA_SIZE-1:0] sram12_data0;
+   reg [`DATA_SIZE-1:0] sram12_data1;
+   reg [`DATA_SIZE-1:0] sram13_data0;
+   reg [`DATA_SIZE-1:0] sram13_data1;
+   reg [`DATA_SIZE-1:0] sram14_data0;
+   reg [`DATA_SIZE-1:0] sram14_data1;
+   reg [`DATA_SIZE-1:0] sram15_data0;
+   reg [`DATA_SIZE-1:0] sram15_data1;
 
    always @(posedge clk) begin
       if (!resetn) begin
@@ -445,28 +447,28 @@
 	 sram3_data1 <= 0;
 	 sram4_data0 <= 0;
 	 sram4_data1 <= 0;
-	 // sram5_data0 <= 0;
-	 // sram5_data1 <= 0;
-	 // sram6_data0 <= 0;
-	 // sram6_data1 <= 0;
-	 // sram7_data0 <= 0;
-	 // sram7_data1 <= 0;
+	 sram5_data0 <= 0;
+	 sram5_data1 <= 0;
+	 sram6_data0 <= 0;
+	 sram6_data1 <= 0;
+	 sram7_data0 <= 0;
+	 sram7_data1 <= 0;
 	 sram8_data0 <= 0;
-	 //sram8_data1 <= 0;
+	 sram8_data1 <= 0;
 	 sram9_data0 <= 0;
-	 //sram9_data1 <= 0;
+	 sram9_data1 <= 0;
 	 sram10_data0 <= 0;
-	 //sram10_data1 <= 0;
+	 sram10_data1 <= 0;
 	 sram11_data0 <= 0;
-	 //sram11_data1 <= 0;
-	 //sram12_data0 <= 0;
-	 //sram12_data1 <= 0;
-	 //sram13_data0 <= 0;
-	 //sram13_data1 <= 0;
-	 //sram14_data0 <= 0;
-	 //sram14_data1 <= 0;
-	 //sram15_data0 <= 0;
-	 //sram15_data1 <= 0;
+	 sram11_data1 <= 0;
+	 sram12_data0 <= 0;
+	 sram12_data1 <= 0;
+	 sram13_data0 <= 0;
+	 sram13_data1 <= 0;
+	 sram14_data0 <= 0;
+	 sram14_data1 <= 0;
+	 sram15_data0 <= 0;
+	 sram15_data1 <= 0;
       end
       else begin
 	 sram0_data0 <= sram0_dout0;
@@ -479,55 +481,37 @@
 	 sram3_data1 <= sram3_dout1;
 	 sram4_data0 <= sram4_dout0;
 	 sram4_data1 <= sram4_dout1;
-	 // sram5_data0 <= sram5_dout0;
-	 // sram5_data1 <= sram5_dout1;
-	 // sram6_data0 <= sram6_dout0;
-	 // sram6_data1 <= sram6_dout1;
-	 // sram7_data0 <= sram7_dout0;
-	 // sram7_data1 <= sram7_dout1;
+	 sram5_data0 <= sram5_dout0;
+	 sram5_data1 <= sram5_dout1;
+	 sram6_data0 <= sram6_dout0;
+	 sram6_data1 <= sram6_dout1;
+	 sram7_data0 <= sram7_dout0;
+	 sram7_data1 <= sram7_dout1;
 	 sram8_data0 <= sram8_dout0;
-	 // sram8_data1 <= sram8_dout1;
+	 sram8_data1 <= sram8_dout1;
 	 sram9_data0 <= sram9_dout0;
-	 // sram9_data1 <= sram9_dout1;
+	 sram9_data1 <= sram9_dout1;
 	 sram10_data0 <= sram10_dout0;
-	 // sram10_data1 <= sram10_dout1;
+	 sram10_data1 <= sram10_dout1;
 	 sram11_data0 <= sram11_dout0;
-	 // sram11_data1 <= sram11_dout1;
-	 // sram12_data0 <= sram12_dout0;
-	 // sram12_data1 <= sram12_dout1;
-	 // sram13_data0 <= sram13_dout0;
-	 // sram13_data1 <= sram13_dout1;
-	 // sram14_data0 <= sram14_dout0;
-	 // sram14_data1 <= sram14_dout1;
-	 // sram15_data0 <= sram15_dout0;
-	 // sram15_data1 <= sram15_dout1;
+	 sram11_data1 <= sram11_dout1;
+	 sram12_data0 <= sram12_dout0;
+	 sram12_data1 <= sram12_dout1;
+	 sram13_data0 <= sram13_dout0;
+	 sram13_data1 <= sram13_dout1;
+	 sram14_data0 <= sram14_dout0;
+	 sram14_data1 <= sram14_dout1;
+	 sram15_data0 <= sram15_dout0;
+	 sram15_data1 <= sram15_dout1;
       end
    end
 
+   // Single port SRAMs
    wire [`DATA_SIZE-1:0] sram8_dout1 = 0;
    wire [`DATA_SIZE-1:0] sram9_dout1 = 0;
    wire [`DATA_SIZE-1:0] sram10_dout1 = 0;
    wire [`DATA_SIZE-1:0] sram11_dout1 = 0;
 
-   wire [`DATA_SIZE-1:0] sram5_data0 = 0;
-   wire [`DATA_SIZE-1:0] sram5_data1 = 0;
-   wire [`DATA_SIZE-1:0] sram6_data0 = 0;
-   wire [`DATA_SIZE-1:0] sram6_data1 = 0;
-   wire [`DATA_SIZE-1:0] sram7_data0 = 0;
-   wire [`DATA_SIZE-1:0] sram7_data1 = 0;
-   wire [`DATA_SIZE-1:0] sram7_data1 = 0;
-   wire [`DATA_SIZE-1:0] sram8_data1 = 0;
-   wire [`DATA_SIZE-1:0] sram9_data1 = 0;
-   wire [`DATA_SIZE-1:0] sram10_data1 = 0;
-   wire [`DATA_SIZE-1:0] sram11_data1 = 0;
-   wire [`DATA_SIZE-1:0] sram12_data0 = 0;
-   wire [`DATA_SIZE-1:0] sram12_data1 = 0;
-   wire [`DATA_SIZE-1:0] sram13_data0 = 0;
-   wire [`DATA_SIZE-1:0] sram13_data1 = 0;
-   wire [`DATA_SIZE-1:0] sram14_data0 = 0;
-   wire [`DATA_SIZE-1:0] sram14_data1 = 0;
-   wire [`DATA_SIZE-1:0] sram15_data0 = 0;
-   wire [`DATA_SIZE-1:0] sram15_data1 = 0;
 
 endmodule	// user_project_wrapper