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foss-eda-tools/third_party/shuttle/sky130/mpw-002/slot-009/2603fb948e7c06fa91e16ef6d93c7435fbf65546
commit
2603fb948e7c06fa91e16ef6d93c7435fbf65546
[log] [tgz]
author
mrg <mrg@ucsc.edu>
Thu Jun 17 11:24:13 2021 -0700
committer
mrg <mrg@ucsc.edu>
Thu Jun 17 11:24:13 2021 -0700
tree
c4905a252de74fa9dfd7f73cd8fe7772063fb757
parent
d54b7b1f7339a70fdfadfe4408b0141cbc346917 [diff]
Remove old verilog
1 file changed
tree: c4905a252de74fa9dfd7f73cd8fe7772063fb757
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. single_port/
  11. spi/
  12. verilog/
  13. caravel
  14. .gitignore
  15. .gitmodules
  16. info.yaml
  17. LICENSE
  18. Makefile
  19. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.