Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
245e98f0ecd2a5a65c668bbc1b9eefa41face456
commit
245e98f0ecd2a5a65c668bbc1b9eefa41face456
[
log
]
[
tgz
]
author
AmoghLonkar <alonkar@ucsc.edu>
Thu Jun 10 22:40:28 2021 -0700
committer
AmoghLonkar <alonkar@ucsc.edu>
Thu Jun 10 22:40:28 2021 -0700
tree
ad6ef7387639ce399c801a08fc0ae4db409fedb9
parent
a44330c3d71af81a2af97ed289894a8f764cc38f
[
diff
]
Single clock
verilog/rtl/openram_testchip.v
[
diff
]
verilog/rtl/openram_testchip_tb.v
[
diff
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2 files changed
tree: ad6ef7387639ce399c801a08fc0ae4db409fedb9
.github/
chisel/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
single_port/
spi/
verilog/
caravel
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LICENSE
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README.md
README.md
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