commit: 197c62f98cebda9ce717b9ea97d16670bcf0f1a5
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Tue Jun 15 22:12:37 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Tue Jun 15 22:12:37 2021 -0700
tree: 1fa306e31600b6d3ae8347a6ffa56f76d7afa6dc
parent: df3c0153165a1a83ee36fbe789b960a41c4d1572 [diff]

openram_testchip_la_tb.v

Testbench for LA Interface

verilog/rtl/openram_testchip_la_tb.v[Added - diff]

1 file changed

tree: 1fa306e31600b6d3ae8347a6ffa56f76d7afa6dc

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.