Fixed sram clock selection

verilog/rtl/openram_testchip.v

diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
index 1195e63..279ec49 100644
--- a/verilog/rtl/openram_testchip.v
+++ b/verilog/rtl/openram_testchip.v
@@ -82,7 +82,7 @@
 //Selecting clock pin

 always @(*) begin

     clk = in_select ? gpio_clk : la_clk;

-    sram_clk = in_select ? gpio_clk : la_clk;

+    sram_clk = in_select ? gpio_sram_clk : la_sram_clk;

 end

 

 always @ (posedge clk) begin