commit 15b80b21d8a106878bd9c928d91dad671caef23b
author AmoghLonkar <alonkar@ucsc.edu> Sat Jun 12 16:45:56 2021 -0700
committer AmoghLonkar <alonkar@ucsc.edu> Sat Jun 12 16:45:56 2021 -0700
tree 39ef5a1d54bdc50e4f9482615a46603e2ed633bb
parent 66e1cb8f6dfc3b21d28c25adcb991e6cc29213f2

Fixed sram clock selection

verilog/rtl/openram_testchip.v

diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
index 1195e63..279ec49 100644
--- a/verilog/rtl/openram_testchip.v
+++ b/verilog/rtl/openram_testchip.v
@@ -82,7 +82,7 @@
 //Selecting clock pin

 always @(*) begin

     clk = in_select ? gpio_clk : la_clk;

-    sram_clk = in_select ? gpio_clk : la_clk;

+    sram_clk = in_select ? gpio_sram_clk : la_sram_clk;

 end

 

 always @ (posedge clk) begin