Add initial la test
diff --git a/verilog/dv/la_test/la_test.c b/verilog/dv/la_test/la_test.c
index 8ccdb53..fc9d91b 100644
--- a/verilog/dv/la_test/la_test.c
+++ b/verilog/dv/la_test/la_test.c
@@ -25,34 +25,66 @@
- Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
*/
+
+ /* wire la_clk = la_data_in[127]; */
+ /* wire la_reset = la_data_in[126]; */
+ /* wire la_in_load = la_data_in[125]; */
+ /* wire la_sram_load = la_data_in[124]; */
+ /* wire la_global_cs = la_data_in[123]; */
+/* * chip_select (4) */
+/* * addr0 (16) */
+/* * din0 (32) */
+/* * csb0 (1) */
+/* * web0 (1) */
+/* * wmask0 (1) */
+/* * addr1 (16) */
+/* * din1 (32) */
+/* * csb1 (1) */
+/* * web1 (1) */
+/* * wmask1 (4) */
+typedef struct bit_fields {
+
+ unsigned int clk : 1;
+ unsigned int rst : 1;
+ unsigned int in_load : 1;
+ unsigned int sram_load : 1;
+ unsigned int cs : 1;
+
+ // unused bits
+ unsigned int unused : 15;
+
+ // 112 bits
+ unsigned int addr0 : 16;
+ unsigned int din0 : 32;
+ unsigned int csb0 : 1;
+ unsigned int web0 : 1;
+ unsigned int wmask0 : 4;
+
+ unsigned int addr1 : 16;
+ unsigned int din1 : 32;
+ unsigned int csb1 : 1;
+ unsigned int web1 : 1;
+ unsigned int wmask1 : 4;
+} bit_fields_t;
+
+typedef struct word_fields {
+
+ unsigned int word3 : 32;
+ unsigned int word2 : 32;
+ unsigned int word1 : 32;
+ unsigned int word0 : 32;
+} word_fields_t;
+
+union packet {
+ bit_fields_t bif;
+ word_fields_t byf;
+};
+
+
void main()
{
- /*
- IO Control Registers
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
-
- Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
-
-
- Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
-
- */
-
- /* Set up the housekeeping SPI to be connected internally so */
- /* that external pin changes don't affect it. */
-
reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
// connect to housekeeping SPI
-
- // Connect the housekeeping SPI to the SPI master
- // so that the CSB line is not left floating. This allows
- // all of the GPIO pins to be used for user functions.
-
// Configure Pin 22 as user output
// Observe counter value in the testbench
reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
@@ -68,6 +100,37 @@
reg_la3_data = 0x00000000;
+ union packet p;
+ p.bif.rst = 0;
+ reg_la0_data = p.byf.word0;
+ reg_la1_data = p.byf.word1;
+ reg_la2_data = p.byf.word2;
+ reg_la3_data = p.byf.word3;
+
+ p.bif.rst = 1;
+ reg_la0_data = p.byf.word0;
+ reg_la1_data = p.byf.word1;
+ reg_la2_data = p.byf.word2;
+ reg_la3_data = p.byf.word3;
+
+ p.bif.rst = 0;
+ reg_la0_data = p.byf.word0;
+ reg_la1_data = p.byf.word1;
+ reg_la2_data = p.byf.word2;
+ reg_la3_data = p.byf.word3;
+
+ p.bif.addr0 = 0x000000001;
+ p.bif.din0 = 0xDEADBEEF;
+ p.bif.csb0 = 0;
+ p.bif.web0 = 0;
+ p.bif.csb1 = 1;
+ p.bif.web1 = 1;
+ reg_la0_data = p.byf.word0;
+ reg_la1_data = p.byf.word1;
+ reg_la2_data = p.byf.word2;
+ reg_la3_data = p.byf.word3;
+
+
// On success, set pin 22 to 1
reg_mprj_datal = 0xFFFFFFFF;
/* Apply configuration */
diff --git a/verilog/dv/la_test/la_test_tb.v b/verilog/dv/la_test/la_test_tb.v
index 37877a0..a6351c1 100644
--- a/verilog/dv/la_test/la_test_tb.v
+++ b/verilog/dv/la_test/la_test_tb.v
@@ -68,7 +68,9 @@
$dumpfile("la_test.vcd");
$dumpvars(0, la_test_tb);
- #100000 $display("FAILED");
+ // Extend this if needed, but have a safety timeout
+ #10000 $display("FAILED");
+ $finish;
end
