Update macro placement. Remove a dual port mem.

openlane/openram_testchip/config.tcl

diff --git a/openlane/openram_testchip/config.tcl b/openlane/openram_testchip/config.tcl
index e9e966a..ab3d61e 100644
--- a/openlane/openram_testchip/config.tcl
+++ b/openlane/openram_testchip/config.tcl
@@ -20,7 +20,7 @@
 set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
 set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
 
-#set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 
 #set ::env(SYNTH_NO_FLAT) 1
 set ::env(GLB_RT_ADJUSTMENT) 0.20

openlane/user_project_wrapper/macro.cfg

diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 39e0f7c..fde5bc5 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,20 +1,51 @@
 # Assume the area is equally divided
 # Area is roughly 2800 wide and 3400 high
+# Sizes:
 
 # 3400 / 6 = ~600
-#SRAM0 100 200 N
-SRAM1 100 800 N
-SRAM2 100 800 N
-SRAM3 100 1400 N
-SRAM4 100 2000 N
-SRAM5 100 2600 N
+
+# 100 on the bottom and 100 betwen macros
+
+# sky130_sram_1kbyte_1rw1w_8x1024_8
+# 452 x 443
+SRAM0 100 100 N
+
+# sky130_sram_1kbyte_1rw1w_32x256_8
+# 476 x 395
+SRAM1 100 700 N
+
+# sky130_sram_2kbyte_1rw1w_32x512_8
+# 680 x 414
+SRAM2 100 1200 N
+
+# sky130_sram_4kbyte_1rw1w_32x1024_8
+# 690 x 667
+SRAM3 100 1900 N
+
+# sky130_sram_8kbyte_1rw1w_32x2048_8
+# 1094 x 721
+SRAM4 100 2700 N
+
+# sky130_sram_16kbyte_1rw1w_32x4096_8 
 #SRAM6 
 
 # Control is 800 wide with 100 margin
 # so 2000
+
+# sram_1rw0r0w_32_256_sky130
+# 473 x 220
 SRAM11 2000 800 N
-SRAM10 2000 1400
-SRAM9 2000 2000
-SRAM8 2000 2600
+
+# sram_1rw0r0w_32_512_sky130
+# 476 x 320
+SRAM10 2000 1200
+
+# sram_1rw0r0w_32_1024_sky130
+# 801 x 348
+SRAM9 2000 1500
+
+# sram_1rw0r0w_64_512_sky130
+# 823 x 335
+SRAM8 2000 2300
 
 CONTROL_LOGIC 1000 200 N

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 86c92de..6f123dc 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -258,30 +258,28 @@
    // Only io_out[27] is output
    assgin io_oeb = 1'b1 << 21;
 
-// Not working yet
-// sky130_sram_1kbyte_1r1w_8x1024_8 SRAM0
-//      (
-//      `ifdef USE_POWER_PINS
-//       .vccd1(vccd1),
-//       .vssd1(vssd1), 
-//       `endif
-//       .clk0   (sram0_clk),
-//       .csb0   (csb0[0]),
-//       .web0   (web0),
-//       .wmask0 (wmask0),
-//       .addr0  (addr0),
-//       .din0   (din0),
-//       .dout0  (sram0_dout0[7:0]),
-//       .clk1   (sram0_clk),
-//       .csb1   (csb1[0]),
-//       .addr1  (addr1),
-//       .dout1  (sram0_dout1[7:0])
-//       );
-//    assign sram0_dout0 = 0;
-//    assign sram0_dout1[31:8] = 0;
-
-
-sky130_sram_1kbyte_1rw1r_8x1024_8 SRAM1
+sky130_sram_1kbyte_1rw1r_8x1024_8 SRAM0
+     (
+     `ifdef USE_POWER_PINS
+      .vccd1(vccd1),
+      .vssd1(vssd1), 
+      `endif
+      .clk0   (sram0_clk),
+      .csb0   (csb0[0]),
+      .web0   (web0),
+      .wmask0 (wmask0),
+      .addr0  (addr0),
+      .din0   (din0),
+      .dout0  (sram0_dout0[7:0]),
+      .clk1   (sram0_clk),
+      .csb1   (csb1[0]),
+      .addr1  (addr0),
+      .dout1  (sram0_dout1[7:0])
+      );
+   assign sram0_dout0[31:8] = 0;
+   assign sram0_dout1[31:8] = 0;
+   
+sky130_sram_1kbyte_1rw1r_32x256_8 SRAM1
      (
      `ifdef USE_POWER_PINS
       .vccd1(vccd1),
@@ -293,17 +291,15 @@
       .wmask0 (wmask0),
       .addr0  (addr0),
       .din0   (din0),
-      .dout0  (sram1_dout0[7:0]),
+      .dout0  (sram1_dout0),
       .clk1   (sram1_clk),
       .csb1   (csb1[1]),
       .addr1  (addr1),
-      .dout1  (sram1_dout1[7:0])
+      .dout1  (sram1_dout1)
       );
-   assign sram1_dout0[31:8] = 0;
-   assign sram1_dout1[31:8] = 0;
    
-sky130_sram_1kbyte_1rw1r_32x256_8 SRAM2
-     (
+sky130_sram_2kbyte_1rw1r_32x512_8 SRAM2
+     (p
      `ifdef USE_POWER_PINS
       .vccd1(vccd1),
       .vssd1(vssd1), 
@@ -320,9 +316,9 @@
       .addr1  (addr1),
       .dout1  (sram2_dout1)
       );
-   
-sky130_sram_2kbyte_1rw1r_32x512_8 SRAM3
-     (p
+
+sky130_sram_4kbyte_1rw1r_32x1024_8 SRAM3
+     (
      `ifdef USE_POWER_PINS
       .vccd1(vccd1),
       .vssd1(vssd1), 
@@ -339,8 +335,8 @@
       .addr1  (addr1),
       .dout1  (sram3_dout1)
       );
-
-sky130_sram_4kbyte_1rw1r_32x1024_8 SRAM4
+   
+sky130_sram_8kbyte_1rw1r_32x2048_8 SRAM4
      (
      `ifdef USE_POWER_PINS
       .vccd1(vccd1),
@@ -358,25 +354,6 @@
       .addr1  (addr1),
       .dout1  (sram4_dout1)
       );
-   
-sky130_sram_8kbyte_1rw1r_32x2048_8 SRAM5
-     (
-     `ifdef USE_POWER_PINS
-      .vccd1(vccd1),
-      .vssd1(vssd1), 
-      `endif
-      .clk0   (sram5_clk),
-      .csb0   (csb0[5]),
-      .web0   (web0),
-      .wmask0 (wmask0),
-      .addr0  (addr0),
-      .din0   (din0),
-      .dout0  (sram5_dout0),
-      .clk1   (sram5_clk),
-      .csb1   (csb1[5]),
-      .addr1  (addr1),
-      .dout1  (sram5_dout1)
-      );
 
 // Not working yet
 // sky130_sram_16kbyte_1rw1r_32x4096_8 SRAM6