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foss-eda-tools/third_party/shuttle/sky130/mpw-002/slot-007/HEAD
  1. 26e8605 Updating the shuttle_url value in `info.yaml` file. by Tim 'mithro' Ansell · 3 years, 10 months ago main
  2. aee4a29 final gds & signoff results by Jeff DiCorpo · 4 years, 10 months ago
  3. 9006aad final gds oasis by Jeff DiCorpo · 4 years, 10 months ago
  4. ac6e601 final gds & signoff results by Jeff DiCorpo · 4 years, 11 months ago
  5. 4a9dd56 final gds oasis by Jeff DiCorpo · 4 years, 11 months ago
  6. 7e549b5 final gds & signoff results by Jeff DiCorpo · 5 years ago
  7. 2d4558f final gds oasis by Jeff DiCorpo · 5 years ago
  8. f467e63 final gds & signoff results by Jeff DiCorpo · 5 years ago
  9. 5175260 final gds oasis by Jeff DiCorpo · 5 years ago
  10. 1c127a8 tapeout.log by Jeff DiCorpo · 5 years ago
  11. cee0eac final gds & signoff results by Jeff DiCorpo · 5 years ago
  12. 6ae2406 final gds oasis by Jeff DiCorpo · 5 years ago
  13. db33f03 final gds & signoff results by Jeff DiCorpo · 5 years ago
  14. 3e15780 final gds oasis by Jeff DiCorpo · 5 years ago
  15. 2f1dd8b final gds & signoff results by Jeff DiCorpo · 5 years ago
  16. 820ce29 final gds oasis by Jeff DiCorpo · 5 years ago
  17. 4ed0e76 final gds & signoff results by Jeff DiCorpo · 5 years ago
  18. 434b39e final gds oasis by Jeff DiCorpo · 5 years ago
  19. 93bf859 final gds & signoff results by Jeff DiCorpo · 5 years ago
  20. 40a1350 final gds oasis by Jeff DiCorpo · 5 years ago
  21. 4382e33 final gds & signoff results by Jeff DiCorpo · 5 years ago
  22. bbe6ffe final gds oasis by Jeff DiCorpo · 5 years ago
  23. d134e4f Riscv Unalign access fix and sdr ctrl 8 bit address mode fix by dineshannayya · 5 years ago
  24. 26743b2 modelsim compile cleanup by dineshannayya · 5 years ago
  25. 337d9f8 synta core cleanup by dineshannayya · 5 years ago
  26. 2223fbd pdk file are copied /opt/pdk inside the docker by dineshannayya · 5 years ago
  27. 5bc74d2 synthesis with latest yosys with $ netname avoidance fix by dineshannayya · 5 years ago
  28. c6a2a5d antenna fix by dineshannayya · 5 years ago
  29. c88cc9d openlane link pointing to dineshannaya/openlane by dineshannayya · 5 years ago
  30. c3362ee efabless/dv_setup moved as dineshannayya/dvsetup with updating latest iverilog + 64bit riscv gcc compile support, efabless core compile also moved from 32 bit to 64bit by dineshannayya · 5 years ago
  31. c057bac efabless/dv_setup moved as dineshannayya/dvsetup with updating latest iverilog + 64bit riscv gcc compile support, efabless core compile also moved from 32 bit to 64bit by dineshannayya · 5 years ago
  32. 47e853b block diagram updated by dineshannayya · 5 years ago
  33. fbc351b SPDX Non compliant text fix by dineshannayya · 5 years ago
  34. 3ae1a2b usb1 host is integrated by dineshannayya · 5 years ago
  35. 1bfec4f Register Map detail updated by dineshannayya · 5 years ago
  36. 8adb7e4 Register Map updated in Readme by dineshannayya · 5 years ago
  37. 9daed32 README updated with i2c info by dineshannayya · 5 years ago
  38. 4a4e2b8 YiFive Block Diagram Updated, Added I2C Master by dineshannayya · 5 years ago
  39. 4f74e2f i2cm integrated and share same uart io by dineshannayya · 5 years ago
  40. 80d1ad8 spi master with qddr mode support added by dineshannayya · 5 years ago
  41. 9fdcbca syntacore timing fix by dineshannayya · 5 years ago
  42. 77ce327 syntacore rtl changes to improve timing closure from 25Mhz to 50Mhz by dineshannayya · 5 years ago
  43. 8db2585 syntacore timing optimization, timing stage added at scr1_pipe_mrpf by dineshannayya · 5 years ago
  44. 9242ac2 SPI Preftech logic added by dineshannayya · 5 years ago
  45. a8d6590 Power Ring is now 8 + Power Mesh is 2 (vccd1 & vssd1) by dineshannayya · 5 years ago
  46. 93bc315 clk_skew power hook fix by dineshannayya · 5 years ago
  47. 14f70c6 sta clean up, global clock buf and reset buf added by dineshannayya · 5 years ago
  48. 5ac4e7d full chip sta clean-up: cpu,spi,rtc clock generation moved from glbl_cfg to wb_host by dineshannayya · 5 years ago
  49. daa4343 sdram clock connectivity correction at u_skew hookup by dineshannayya · 5 years ago
  50. 4c022a3 spi unused input pin io_in[1:0] removed by dineshannayya · 5 years ago
  51. ae23e25 Timing Closure related clean-up. Hold fix added at spi-master and clock delay adjusted inside the clock_skew module by dineshannayya · 5 years ago
  52. 63db20d Clean GateSim and RTL Sim + Updated SPI Master by dineshannayya · 5 years ago
  53. dcf9534 first version of pre-check clean database by dineshannayya · 5 years ago
  54. a25bcff Clock Skew adjust network added + Inside SDRAM WB Stagging FF added by dineshannayya · 5 years ago
  55. 311a4e0 precheck cleanup by dineshannayya · 5 years ago
  56. c184ad2 License Text Added by dineshannayya · 5 years ago
  57. 76d58fb DRC clean user_project_wrapper by dineshannayya · 5 years ago
  58. a908000 updated database by dineshannayya · 5 years ago
  59. 81d24ed wb_host rtl and openlane setup added by dineshannayya · 5 years ago
  60. feb1877 backand cleanup by dineshannayya · 5 years ago
  61. 9112eeb user project def,lef,gds added by dineshannayya · 5 years ago
  62. ed94965 database update by dineshannayya · 5 years ago
  63. 3f698f9 script update by dineshannayya · 5 years ago
  64. 1431d7b def,gds,lef addition by dineshannayya · 5 years ago
  65. e08e2a5 uart test case integration by dineshannayya · 5 years ago
  66. b547314 uart test case integration by dineshannayya · 5 years ago
  67. 46bd181 uart integrated into SOC by DESKTOP-QFPBD39\dinesha · 5 years ago
  68. 35b181f Merge branch 'master' of https://github.com/dineshannayya/yifive_r0 by DESKTOP-QFPBD39\dinesha · 5 years ago
  69. ea1e6f3 floor planning cleanup by dineshannayya · 5 years ago
  70. a040531 risc core and wishbone domain seperated + Stagging FF added at wishbone interconnect by dineshannayya · 5 years ago
  71. 723ff6c prec-check clean-up .docx and .obd file removes from doc folder by dineshannayya · 5 years ago
  72. 42f8786 readme added by dineshannayya · 5 years ago
  73. 493d018 def,lef,gds,mag,spi,magled added by dineshannayya · 5 years ago
  74. 44e67e1 first user project lvs clean database by dineshannayya · 5 years ago
  75. 54e49ce spi rtl issue fix in clkgen by dineshannayya · 5 years ago
  76. f21e9b6 info update by DESKTOP-QFPBD39\dinesha · 5 years ago
  77. 6330d33 carvel submodel added by DESKTOP-QFPBD39\dinesha · 5 years ago
  78. 0a0119f signoff added by dineshannayya · 5 years ago
  79. b2b810b Design Document added by DESKTOP-QFPBD39\dinesha · 5 years ago
  80. c0f4d4f readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago
  81. c9f1ae3 readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago
  82. 3ee6a19 readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago
  83. fdfa50d readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago
  84. 26c10d3 readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago
  85. c27c399 readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago
  86. feb001d readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago
  87. 19d0960 Read me update with Soc Pin Map by DESKTOP-QFPBD39\dinesha · 5 years ago
  88. a3c31b0 readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago
  89. fded6d7 readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago
  90. 2eebfb2 readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago
  91. 15da101 Readme update by DESKTOP-QFPBD39\dinesha · 5 years ago
  92. 9ca8009 pin order update for sdram & syntacore by dineshannayya · 5 years ago
  93. b051167 Readme update by dineshannayya · 5 years ago
  94. 3767e91 Readme update by dineshannayya · 5 years ago
  95. 9741649 ReadMe update by dineshannayya · 5 years ago
  96. 3adf542 Read Me update by dineshannayya · 5 years ago
  97. aade2f4 ReadMe updated by dineshannayya · 5 years ago
  98. 2e2fad8 sdram added by dinesha · 5 years ago
  99. 21e5ba9 test bench update by dinesha · 5 years ago
  100. d4c716c Simulation clean up and wishbone interconnect added by dinesha · 5 years ago