sdram clock connectivity correction at u_skew hookup
diff --git a/def/user_project_wrapper.def.gz b/def/user_project_wrapper.def.gz
index 69541a8..6fb7524 100644
--- a/def/user_project_wrapper.def.gz
+++ b/def/user_project_wrapper.def.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index fb5fdd7..eb9572e 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index b3ba08b..56101d9 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ
diff --git a/mag/user_project_wrapper.mag.gz b/mag/user_project_wrapper.mag.gz
index 22aa6c7..19750ea 100644
--- a/mag/user_project_wrapper.mag.gz
+++ b/mag/user_project_wrapper.mag.gz
Binary files differ
diff --git a/maglef/user_project_wrapper.mag.gz b/maglef/user_project_wrapper.mag.gz
index 2348a31..22da1af 100644
--- a/maglef/user_project_wrapper.mag.gz
+++ b/maglef/user_project_wrapper.mag.gz
Binary files differ
diff --git a/openlane/user_project_wrapper/base.sdc b/openlane/user_project_wrapper/base.sdc
index ea5f7ca..6aabd5a 100644
--- a/openlane/user_project_wrapper/base.sdc
+++ b/openlane/user_project_wrapper/base.sdc
@@ -16,52 +16,113 @@
set_units -time ns
-set ::env(WB_CLOCK_PERIOD) "10"
-set ::env(WB_CLOCK_PORT) "wb_clk_i"
+set ::env(WBM_CLOCK_PERIOD) "10"
+set ::env(WBM_CLOCK_PORT) "wb_clk_i"
+set ::env(WBM_CLOCK_NAME) "wbm_clk_i"
+
+set ::env(WBS_CLOCK_PERIOD) "10"
+set ::env(WBS_CLOCK_PORT) "u_wb_host*wbs_clk_i"
+set ::env(WBS_CLOCK_NAME) "wbs_clk_i"
set ::env(SDRAM_CLOCK_PERIOD) "20"
-set ::env(SDRAM_CLOCK_PORT) "digital_core.u_glbl_cfg.sdram_clk"
+set ::env(SDRAM_CLOCK_PORT) "u_glbl_cfg*sdram_clk"
+set ::env(SDRAM_CLOCK_NAME) "sdram_clk"
set ::env(PAD_SDRAM_CLOCK_PERIOD) "20"
-set ::env(PAD_SDRAM_CLOCK_PORT) "digital_core.u_sdram_ctrl.sdram_pad_clk"
+set ::env(PAD_SDRAM_CLOCK_PORT) "u_skew_sd_ci*sclk_out"
+set ::env(PAD_SDRAM_CLOCK_NAME) "sdram_pad_clk"
set ::env(CPU_CLOCK_PERIOD) "50"
-set ::env(CPU_CLOCK_PORT) "digital_core.u_glbl_cfg.cpu_clk"
+set ::env(CPU_CLOCK_PORT) "u_glbl_cfg*cpu_clk"
+set ::env(CPU_CLOCK_NAME) "cpu_clk"
set ::env(RTC_CLOCK_PERIOD) "50"
-set ::env(RTC_CLOCK_PORT) "digital_core.u_glbl_cfg.rtc_clk"
+set ::env(RTC_CLOCK_PORT) "u_glbl_cfg*rtc_clk"
+set ::env(RTC_CLOCK_NAME) "rtc_clk"
+
+#Setting clock delay to center of the tap
+set_case_analysis 1 [get_pins -hierarchical u_skew_wi*sel[3]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_wi*sel[2]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_wi*sel[1]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_wi*sel[0]]
+
+set_case_analysis 1 [get_pins -hierarchical u_skew_riscv*sel[3]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_riscv*sel[2]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_riscv*sel[1]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_riscv*sel[0]]
+
+set_case_analysis 1 [get_pins -hierarchical u_skew_uart*sel[3]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_uart*sel[2]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_uart*sel[1]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_uart*sel[0]]
+
+set_case_analysis 1 [get_pins -hierarchical u_skew_spi*sel[3]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_spi*sel[2]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_spi*sel[1]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_spi*sel[0]]
+
+set_case_analysis 1 [get_pins -hierarchical u_skew_glbl*sel[3]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_glbl*sel[2]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_glbl*sel[1]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_glbl*sel[0]]
+
+set_case_analysis 1 [get_pins -hierarchical u_skew_wh*sel[3]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_wh*sel[2]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_wh*sel[1]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_wh*sel[0]]
+
+# Set the interface logic to 0
+set_case_analysis 0 [get_pins -hierarchical u_skew_sd_co*sel[3]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_sd_co*sel[2]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_sd_co*sel[1]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_sd_co*sel[0]]
+
+set_case_analysis 0 [get_pins -hierarchical u_skew_sd_ci*sel[3]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_sd_ci*sel[2]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_sd_ci*sel[1]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_sd_ci*sel[0]]
+
+set_case_analysis 0 [get_pins -hierarchical u_skew_sp_co*sel[3]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_sp_co*sel[2]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_sp_co*sel[1]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_sp_co*sel[0]]
+
######################################
-# WB Clock domain input output
+# WB MASTER Clock domain input output
######################################
-create_clock [get_ports $::env(WB_CLOCK_PORT)] -name $::env(WB_CLOCK_PORT) -period $::env(WB_CLOCK_PERIOD)
-set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
-set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+create_clock [get_ports $::env(WBM_CLOCK_PORT)] -name $::env(WBM_CLOCK_NAME) -period $::env(WBM_CLOCK_PERIOD)
+set wb_input_delay_value [expr $::env(WBM_CLOCK_PERIOD) * 0.6]
+set wb_output_delay_value [expr $::env(WBM_CLOCK_PERIOD) * 0.6]
puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
-set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {wb_rst_i}
+set_input_delay 2.0 -clock [get_clocks $::env(WBM_CLOCK_NAME)] {wb_rst_i}
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_stb_i*]
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_cyc_i*]
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_we_i*]
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_sel_i*]
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_dat_i*]
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_adr_i*]
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_cti_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_stb_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_cyc_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_we_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_sel_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_dat_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_adr_i*]
+set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wb_cti_i*]
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_dat_o*]
-set_output_delay 3.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_ack_o*]
+set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_dat_o*]
+set_output_delay 3.0 -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_ack_o*]
######################################
+# WishBone Slave Port
+#######################################
+create_clock [get_pins -hierarchical $::env(WBS_CLOCK_PORT)] -name $::env(WBS_CLOCK_NAME) -period $::env(WBS_CLOCK_PERIOD)
+######################################
# SDRAM Clock domain input output
######################################
-create_clock [get_pins (SDRAM_CLOCK_PORT)] -name $::env(SDRAM_CLOCK_PORT) -period $::env(SDRAM_CLOCK_PERIOD)
-create_clock [get_pins (PAD_SDRAM_CLOCK_PORT)] -name $::env(PAD_SDRAM_CLOCK_PORT) -period $::env(PAD_SDRAM_CLOCK_PERIOD)
-create_clock [get_pins (CPU_CLOCK_PORT)] -name $::env(CPU_CLOCK_PORT) -period $::env(CPU_CLOCK_PERIOD)
-create_clock [get_pins (RTC_CLOCK_PORT)] -name $::env(RTC_CLOCK_PORT) -period $::env(RTC_CLOCK_PERIOD)
+create_clock [get_pins -hierarchical $::env(SDRAM_CLOCK_PORT)] -name $::env(SDRAM_CLOCK_NAME) -period $::env(SDRAM_CLOCK_PERIOD)
+create_clock [get_pins -hierarchical $::env(PAD_SDRAM_CLOCK_PORT)] -name $::env(PAD_SDRAM_CLOCK_NAME) -period $::env(PAD_SDRAM_CLOCK_PERIOD)
+create_clock [get_pins -hierarchical $::env(CPU_CLOCK_PORT)] -name $::env(CPU_CLOCK_NAME) -period $::env(CPU_CLOCK_PERIOD)
+create_clock [get_pins -hierarchical $::env(RTC_CLOCK_PORT)] -name $::env(RTC_CLOCK_NAME) -period $::env(RTC_CLOCK_PERIOD)
-set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WB_CLOCK_PORT)] -group [get_clocks $::env(SDRAM_CLOCK_PORT)] -group [get_clocks $::env(CPU_CLOCK_PORT)] -group [get_clocks $::env(RTC_CLOCK_PORT)]
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WBM_CLOCK_NAME)] -group [get_clocks $::env(WBS_CLOCK_NAME)] -group [get_clocks $::env(SDRAM_CLOCK_NAME)] -group [get_clocks $::env(CPU_CLOCK_NAME)] -group [get_clocks $::env(RTC_CLOCK_NAME)]
diff --git a/openlane/user_project_wrapper/sta.tcl b/openlane/user_project_wrapper/sta.tcl
new file mode 100644
index 0000000..72967bd
--- /dev/null
+++ b/openlane/user_project_wrapper/sta.tcl
@@ -0,0 +1,81 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
+set ::env(LIB_FASTEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_SLOWEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(DESIGN_NAME) "user_project_wrapper"
+set ::env(BASE_SDC_FILE) "/project/openlane/user_project_wrapper/base.sdc"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+define_corners wc bc
+read_liberty -corner bc $::env(LIB_FASTEST)
+read_liberty -corner wc $::env(LIB_SLOWEST)
+read_verilog /project/verilog/gl/clk_skew_adjust.v
+read_verilog /project/verilog/gl/glbl_cfg.v
+#read_verilog /project/verilog/gl/sdram.v
+read_verilog /project/verilog/gl/spi_master.v
+#read_verilog /project/verilog/gl/syntacore.v
+read_verilog /project/verilog/gl/uart.v
+read_verilog /project/verilog/gl/wb_host.v
+read_verilog /project/verilog/gl/wb_interconnect.v
+read_verilog /project/verilog/gl/user_project_wrapper.v
+link_design $::env(DESIGN_NAME)
+
+read_spef -path u_skew_wi /project/spef/clk_skew_adjust.spef
+read_spef -path u_skew_riscv /project/spef/clk_skew_adjust.spef
+read_spef -path u_skew_uart /project/spef/clk_skew_adjust.spef
+read_spef -path u_skew_spi /project/spef/clk_skew_adjust.spef
+read_spef -path u_skew_sdram /project/spef/clk_skew_adjust.spef
+read_spef -path u_skew_glbl /project/spef/clk_skew_adjust.spef
+read_spef -path u_skew_wh /project/spef/clk_skew_adjust.spef
+read_spef -path u_skew_sd_co /project/spef/clk_skew_adjust.spef
+read_spef -path u_skew_sd_ci /project/spef/clk_skew_adjust.spef
+read_spef -path u_skew_sp_co /project/spef/clk_skew_adjust.spef
+read_spef -path u_glbl_cfg /project/spef/glbl_cfg.spef
+#read_spef -path u_riscv_top /project/spef/scr1_top_wb.spef
+#read_spef -path u_sdram_ctrl /project/spef/sdrc_top.spef
+read_spef -path u_spi_master /project/spef/spim_top.spef
+read_spef -path u_uart_core /project/spef/uart_core.spef
+read_spef -path u_wb_host /project/spef/wb_host.spef
+read_spef -path u_intercon /project/spef/wb_interconnect.spef
+read_spef /project/spef/user_project_wrapper.spef
+
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+check_setup -verbose > unconstraints.rpt
+
+set_operating_conditions -analysis_type single
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+report_power
+report_checks -unique -slack_max -0.0 -group_count 100
+report_checks -unique -slack_min -0.0 -group_count 100
+report_checks -path_delay min_max
+report_checks -group_count 100 -slack_max -0.01 > timing.rpt
+
+report_checks -group_count 100 -slack_min -0.01 >> timing.rpt
+
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index be68387..7d44fb6 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h40m0s,0h5m24s,3.3079078455790785,10.2784,1.6539539227895392,0,569.79,17,0,0,0,0,0,0,0,0,30,-1,-1,1186056,4163,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.29,4.06,0.96,2.29,-1,852,1470,852,1470,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h39m34s,0h4m46s,3.3079078455790785,10.2784,1.6539539227895392,0,569.55,17,0,0,0,0,0,0,0,0,24,-1,-1,1188369,4056,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.3,4.07,0.96,2.29,-1,852,1470,852,1470,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
diff --git a/spi/lvs/user_project_wrapper.spice.gz b/spi/lvs/user_project_wrapper.spice.gz
index 7a75127..eacfd77 100644
--- a/spi/lvs/user_project_wrapper.spice.gz
+++ b/spi/lvs/user_project_wrapper.spice.gz
Binary files differ
diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index 53580b7..6450b59 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -1557,7 +1557,7 @@
\cfg_clk_ctrl1[6] ,
\cfg_clk_ctrl1[5] ,
\cfg_clk_ctrl1[4] }));
- clk_skew_adjust u_skew_sd_ci (.clk_in(sdram_clk),
+ clk_skew_adjust u_skew_sd_ci (.clk_in(io_in[29]),
.clk_out(io_in_29_),
.vccd1(vccd1),
.vssd1(vssd1),
@@ -1565,7 +1565,7 @@
\cfg_clk_ctrl2[6] ,
\cfg_clk_ctrl2[5] ,
\cfg_clk_ctrl2[4] }));
- clk_skew_adjust u_skew_sd_co (.clk_in(io_out_29_),
+ clk_skew_adjust u_skew_sd_co (.clk_in(sdram_clk),
.clk_out(io_out[29]),
.vccd1(vccd1),
.vssd1(vssd1),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 610b812..d5665d0 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -779,7 +779,7 @@
.vccd1 (vccd1 ),// User area 1 1.8V supply
.vssd1 (vssd1 ),// User area 1 digital ground
`endif
- .clk_in (io_out_29_ ),
+ .clk_in (sdram_clk ),
.sel (cfg_cska_sd_co ),
.clk_out (io_out[29] )
);
@@ -791,7 +791,7 @@
.vccd1 (vccd1 ),// User area 1 1.8V supply
.vssd1 (vssd1 ),// User area 1 digital ground
`endif
- .clk_in (sdram_clk ),
+ .clk_in (io_in[29] ),
.sel (cfg_cska_sd_ci ),
.clk_out (io_in_29_ )
);
