| ////////////////////////////////////////////////////////////////////////////// |
| // SPDX-FileCopyrightText: 2021, Dinesh Annayya |
| // |
| // Licensed under the Apache License, Version 2.0 (the "License"); |
| // you may not use this file except in compliance with the License. |
| // You may obtain a copy of the License at |
| // |
| // http://www.apache.org/licenses/LICENSE-2.0 |
| // |
| // Unless required by applicable law or agreed to in writing, software |
| // distributed under the License is distributed on an "AS IS" BASIS, |
| // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| // See the License for the specific language governing permissions and |
| // limitations under the License. |
| // SPDX-License-Identifier: Apache-2.0 |
| // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> |
| // ////////////////////////////////////////////////////////////////////////// |
| ////////////////////////////////////////////////////////////////////// |
| //// //// |
| //// yifive Wishbone define for syntacore //// |
| //// //// |
| //// This file is part of the yifive cores project //// |
| //// https://github.com/dineshannayya/yifive_r0.git //// |
| //// http://www.opencores.org/cores/yifive/ //// |
| //// //// |
| //// Description: //// |
| //// integrated wishbone i/f to Syntacore,scr1 core //// |
| //// //// |
| //// To Do: //// |
| //// nothing //// |
| //// //// |
| //// Author(s): //// |
| //// - Dinesh Annayya, dinesha@opencores.org //// |
| //// //// |
| //// Revision : //// |
| //// v0: June 7, 2021, Dinesh A //// |
| //// wishbone define added //// |
| //// //// |
| ////////////////////////////////////////////////////////////////////// |
| //// //// |
| //// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
| //// //// |
| //// This source file may be used and distributed without //// |
| //// restriction provided that this copyright statement is not //// |
| //// removed from the file and that any derivative work contains //// |
| //// the original copyright notice and the associated disclaimer. //// |
| //// //// |
| //// This source file is free software; you can redistribute it //// |
| //// and/or modify it under the terms of the GNU Lesser General //// |
| //// Public License as published by the Free Software Foundation; //// |
| //// either version 2.1 of the License, or (at your option) any //// |
| //// later version. //// |
| //// //// |
| //// This source is distributed in the hope that it will be //// |
| //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
| //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
| //// PURPOSE. See the GNU Lesser General Public License for more //// |
| //// details. //// |
| //// //// |
| //// You should have received a copy of the GNU Lesser General //// |
| //// Public License along with this source; if not, download it //// |
| //// from http://www.opencores.org/lgpl.shtml //// |
| //// //// |
| ////////////////////////////////////////////////////////////////////// |
| // Orginal owner Details //// |
| ////////////////////////////////////////////////////////////////////// |
| /// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details/// |
| /// @file <scr1_ahb.svh> /// |
| /// @brief WB header file /// |
| ///////////////////////////////////////////////////////////////////// |
| |
| `ifndef SCR1_WB_SVH |
| `define SCR1_WB_SVH |
| |
| `include "scr1_arch_description.svh" |
| |
| parameter SCR1_WB_WIDTH = 32; |
| |
| // Encoding for DATA SIZE |
| parameter logic [2:0] SCR1_DSIZE_8B = 3'b000; |
| parameter logic [2:0] SCR1_DSIZE_16B = 3'b001; |
| parameter logic [2:0] SCR1_DSIZE_32B = 3'b010; |
| |
| `endif // SCR1_WB_SVH |
