Design Document added

docs/source/_static/YiFve_Soc_Design_Document.docx

diff --git a/docs/source/_static/YiFve_Soc_Design_Document.docx b/docs/source/_static/YiFve_Soc_Design_Document.docx
new file mode 100644
index 0000000..0ddf5b2
--- /dev/null
+++ b/docs/source/_static/YiFve_Soc_Design_Document.docx
Binary files differ

verilog/rtl/spi_master/src/spim_ctrl.sv

diff --git a/verilog/rtl/spi_master/src/spim_ctrl.sv b/verilog/rtl/spi_master/src/spim_ctrl.sv
index 95e3dd7..8ce6524 100644
--- a/verilog/rtl/spi_master/src/spim_ctrl.sv
+++ b/verilog/rtl/spi_master/src/spim_ctrl.sv
@@ -50,7 +50,6 @@
     output logic                          eot,
 
     input  logic                    [7:0] spi_clk_div,
-    input  logic                          spi_clk_div_valid,
     output logic                    [8:0] spi_status,
 
 

verilog/rtl/spi_master/src/spim_regs.sv

diff --git a/verilog/rtl/spi_master/src/spim_regs.sv b/verilog/rtl/spi_master/src/spim_regs.sv
index 7e826b6..0128568 100644
--- a/verilog/rtl/spi_master/src/spim_regs.sv
+++ b/verilog/rtl/spi_master/src/spim_regs.sv
@@ -65,7 +65,6 @@
     output logic                         wbd_err_o,  // error
 
     output logic                   [7:0] spi_clk_div,
-    output logic                         spi_clk_div_valid,
     input logic                    [8:0] spi_status,
 
     // Towards SPI TX/RX FSM
@@ -248,7 +247,6 @@
       reg2spi_dummy_wr_len  <=  'h0;
       reg2spi_csreg         <=  'h0;
       reg2spi_req           <=  'h0;
-      spi_clk_div_valid     <= 1'b0;
       spi_clk_div           <=  'h2;
       spi_init_done         <=  'h0;
       spi_init_state        <=  SPI_INIT_IDLE;
@@ -351,7 +349,6 @@
           if ( spim_wb_be[0] == 1 )
           begin
             spi_clk_div <= spim_wb_wdata[7:0];
-            spi_clk_div_valid <= 1'b1;
           end
         REG_SPICMD: begin
           if ( spim_wb_be[0] == 1 )

verilog/rtl/spi_master/src/spim_top.sv

diff --git a/verilog/rtl/spi_master/src/spim_top.sv b/verilog/rtl/spi_master/src/spim_top.sv
index 67d09de..3c322fa 100644
--- a/verilog/rtl/spi_master/src/spim_top.sv
+++ b/verilog/rtl/spi_master/src/spim_top.sv
@@ -83,8 +83,7 @@
 
 
 
-    logic   [7:0] spi_clk_div;
-    logic         spi_clk_div_valid;
+    logic   [5:0] spi_clk_div;
     logic         spi_req;
     logic         spi_ack;
     logic  [31:0] spi_addr;
@@ -144,7 +143,6 @@
         .wbd_err_o                      (wbd_err_o                    ),  // error
 
         .spi_clk_div                    (spi_clk_div                  ),
-        .spi_clk_div_valid              (spi_clk_div_valid            ),
         .spi_status                     (spi_ctrl_status              ),
 
 
@@ -176,7 +174,6 @@
         .eot                            (                             ),
 
         .spi_clk_div                    (spi_clk_div                  ),
-        .spi_clk_div_valid              (spi_clk_div_valid            ),
         .spi_status                     (spi_ctrl_status              ),
 
         .spi_req                        (spi_req                      ),