| commit | 9daed323bcb77ca7761897870e15ad4963778c08 | [log] [tgz] |
|---|---|---|
| author | dineshannayya <dinesh.annayya@gmail.com> | Wed Jul 28 14:53:32 2021 +0530 |
| committer | dineshannayya <dinesh.annayya@gmail.com> | Wed Jul 28 14:53:32 2021 +0530 |
| tree | f9e4b6c23328f760a391b316f31516787c20ed55 | |
| parent | 4a4e2b872289285ab8ec262066183a00a51a0429 [diff] |
README updated with i2c info
diff --git a/README.md b/README.md index ad39806..62cfcb9 100644 --- a/README.md +++ b/README.md
@@ -50,6 +50,8 @@ * industry-grade and silicon-proven Open-Source RISC-V core from syntacore * industry-graded and silicon-proven 8-bit SDRAM controller * Quad SPI Master + * UART with 16Byte FIFO + * I2C Master * Wishbone compatible design * Written in System Verilog * Open-source tool set