Register Map updated in Readme
diff --git a/README.md b/README.md
index 62cfcb9..de3be03 100644
--- a/README.md
+++ b/README.md
@@ -155,6 +155,145 @@
</tr>
</table>
+##### Register Map Wishbone HOST
+
+| Offset | Name | Description |
+| ------ | --------- | ------------- |
+| 0x00 | GLBL_CTRL | [RW] Global Wishbone Access Control Register |
+| 0x04 | BANK_CTRL | [RW] Bank Selection, MSB 8 bit Address |
+| 0x08 | CLK_SKEW_CTRL1| [RW] Clock Skew Control2 |
+| 0x0c | CLK_SKEW_CTRL2 | [RW] Clock Skew Control2 |
+
+##### Register: GLBL_CTRL
+
+| Bits | Name | Description |
+| ---- | ---- | -------------- |
+| 31:24 | Resevered | Unsused |
+| 23:20 | RTC_CLK_CTRL | RTC Clock Div Selection |
+| 19:16 | CPU_CLK_CTRL | CPU Clock Div Selection |
+| 15:12 | SDARM_CLK_CTRL| SDRAM Clock Div Selection |
+| 10:8 | WB_CLK_CTRL | Core Wishbone Clock Div Selection |
+| 7 | UART_I2C_SEL | 0 - UART , 1 - I2C Master IO Selection |
+| 5 | I2C_RST | I2C Reset Control |
+| 4 | UART_RST | UART Reset Control |
+| 3 | SDRAM_RST | SDRAM Reset Control |
+| 2 | SPI_RST | SPI Reset Control |
+| 1 | CPU_RST | CPU Reset Control |
+| 0 | WB_RST | Wishbone Core Reset Control |
+
+##### Register: BANK_CTRL
+
+| Bits | Name | Description |
+| ---- | ---- | -------------- |
+| 31:24 | Resevered | Unsused |
+| 7:0 | BANK_SEL | Holds the upper 8 bit address core Wishbone Address |
+
+##### Register: CLK_SKEW_CTRL1
+
+| Bits | Name | Description |
+| ---- | ---- | -------------- |
+| 31:28 | Resevered | Unsused |
+| 27:24 | CLK_SKEW_WB | WishBone Core Clk Skew Control |
+| 23:20 | CLK_SKEW_GLBL | Glbal Register Clk Skew Control |
+| 19:16 | CLK_SKEW_SDRAM| SDRAM Clk Skew Control |
+| 15:12 | CLK_SKEW_SPI | SPI Clk Skew Control |
+| 11:8 | CLK_SKEW_UART | UART/I2C Clk Skew Control |
+| 7:4 | CLK_SKEW_RISC | RISC Clk Skew Control |
+| 3:0 | CLK_SKEW_WI | Wishbone Clk Skew Control |
+
+##### Register Map SPI MASTER
+
+| Offset | Name | Description |
+| ------ | --------- | ------------- |
+| 0x00 | GLBL_CTRL | [RW] Global SPI Access Control Register |
+| 0x04 | DMEM_CTRL1 | [RW] Direct SPI Memory Access Control Register1 |
+| 0x08 | DMEM_CTRL2 | [RW] Direct SPI Memory Access Control Register2 |
+| 0x0c | IMEM_CTRL1 | [RW] Indirect SPI Memory Access Control Register1 |
+| 0x10 | IMEM_CTRL2 | [RW] Indirect SPI Memory Access Control Register2 |
+| 0x14 | IMEM_ADDR | [RW] Indirect SPI Memory Address |
+| 0x18 | IMEM_WDATA | [W] Indirect SPI Memory Write Data |
+| 0x1c | IMEM_RDATA | [R] Indirect SPI Memory Read Data |
+| 0x20 | SPI_STATUS | [R] SPI Debug Status |
+
+##### Register: GLBL_CTRL
+
+| Bits | Name | Description |
+| ---- | ---- | -------------- |
+| 31:16 | Resevered | Unsused |
+| 15:8 | SPI_CLK_DIV | SPI Clock Div Rato Selection |
+| 7:4 | Reserved | Unused |
+| 3:2 | CS_LATE | CS DE_ASSERTION CONTROL |
+| 1:0 | CS_EARLY | CS ASSERTION CONTROL |
+
+##### Register: DMEM_CTRL1
+
+| Bits | Name | Description |
+| ---- | ---- | -------------- |
+| 31:9 | Resevered | Unsused |
+| 8 | FSM_RST | Direct Mem State Machine Reset |
+| 7:6 | SPI_SWITCH | Phase at which SPI Mode need to switch |
+| 5:4 | SPI_MODE | SPI Mode, 0 - Single, 1 - Dual, 2 - Quad, 3 - QDDR |
+| 3:0 | CS_SELECT | CHIP SELECT |
+
+##### Register: DMEM_CTRL2
+
+| Bits | Name | Description |
+| ---- | ---- | -------------- |
+| 31:24 | DATA_CNT | Total Data Byte Count |
+| 23:22 | DUMMY_CNT | Total Dummy Byte Count |
+| 21:20 | ADDR_CNT | Total Address Byte Count |
+| 19:16 | SPI_SEQ | SPI Access Sequence |
+| 15:8 | MODE_REG | Mode Register Value |
+| 7:0 | CMD_REG | Command Register Value |
+
+##### Register: IMEM_CTRL1
+
+| Bits | Name | Description |
+| ---- | ---- | -------------- |
+| 31:9 | Resevered | Unsused |
+| 8 | FSM_RST | InDirect Mem State Machine Reset |
+| 7:6 | SPI_SWITCH | Phase at which SPI Mode need to switch |
+| 5:4 | SPI_MODE | SPI Mode, 0 - Single, 1 - Dual, 2 - Quad, 3 - QDDR |
+| 3:0 | CS_SELECT | CHIP SELECT |
+
+##### Register: IMEM_CTRL2
+
+| Bits | Name | Description |
+| ---- | ---- | -------------- |
+| 31:24 | DATA_CNT | Total Data Byte Count |
+| 23:22 | DUMMY_CNT | Total Dummy Byte Count |
+| 21:20 | ADDR_CNT | Total Address Byte Count |
+| 19:16 | SPI_SEQ | SPI Access Sequence |
+| 15:8 | MODE_REG | Mode Register Value |
+| 7:0 | CMD_REG | Command Register Value |
+
+##### Register: IMEM_ADDR
+
+| Bits | Name | Description |
+| ---- | ---- | -------------- |
+| 31:0 | ADDR | Indirect Memory Address |
+
+##### Register: IMEM_WDATA
+
+| Bits | Name | Description |
+| ---- | ---- | -------------- |
+| 31:0 | WDATA | Indirect Memory Write Data |
+
+##### Register: IMEM_RDATA
+
+| Bits | Name | Description |
+| ---- | ---- | -------------- |
+| 31:0 | RDATA | Indirect Memory Read Data |
+
+##### Register: SPI_STATUS
+
+| Bits | Name | Description |
+| ---- | ---- | -------------- |
+| 31:0 | DEBUG | SPI Debug Status |
+
+
+
+
# SOC Pin Mapping
Carvel SOC provides 38 GPIO pins for user functionality. YiFive SOC GPIO Pin Mapping as follows
diff --git a/verilog/rtl/spi_master/src/spim_regs.sv b/verilog/rtl/spi_master/src/spim_regs.sv
index 496d75e..0885fe0 100644
--- a/verilog/rtl/spi_master/src/spim_regs.sv
+++ b/verilog/rtl/spi_master/src/spim_regs.sv
@@ -157,14 +157,14 @@
// Register Decoding
// ---------------------------
parameter GLBL_CTRL = 4'b0000;
-parameter MEM_CTRL1 = 4'b0001;
-parameter MEM_CTRL2 = 4'b0010;
-parameter REG_CTRL1 = 4'b0011;
-parameter REG_CTRL2 = 4'b0100;
-parameter REG_SPIADR = 4'b0101;
-parameter REG_SPIWDATA = 4'b0110;
-parameter REG_SPIRDATA = 4'b0111;
-parameter REG_STATUS = 4'b1000;
+parameter DMEM_CTRL1 = 4'b0001;
+parameter DMEM_CTRL2 = 4'b0010;
+parameter IMEM_CTRL1 = 4'b0011;
+parameter IMEM_CTRL2 = 4'b0100;
+parameter IMEM_ADDR = 4'b0101;
+parameter IMEM_WDATA = 4'b0110;
+parameter IMEM_RDATA = 4'b0111;
+parameter SPI_STATUS = 4'b1000;
// Init FSM
parameter SPI_INIT_PWUP = 3'b000;
@@ -289,8 +289,8 @@
// 3. Indirect Memory Read
//----------------------------------------------
//
-assign spim_fifo_rdata_req = spim_reg_req && spim_reg_we == 0 && (spim_reg_addr== REG_SPIRDATA);
-assign spim_fifo_wdata_req = spim_reg_req && spim_reg_we == 1 && (spim_reg_addr== REG_SPIWDATA);
+assign spim_fifo_rdata_req = spim_reg_req && spim_reg_we == 0 && (spim_reg_addr== IMEM_RDATA);
+assign spim_fifo_wdata_req = spim_reg_req && spim_reg_we == 1 && (spim_reg_addr== IMEM_WDATA);
always_ff @(negedge rst_n or posedge mclk) begin
if ( rst_n == 1'b0 ) begin
@@ -302,14 +302,14 @@
// If FIFO Write DATA case, Make sure that there no previous pending
// need to processed
spim_reg_ack <= 1'b1;
- end else if (spim_reg_req && spim_reg_we && (spim_reg_addr != REG_SPIWDATA)) begin // Indirect memory Write
+ end else if (spim_reg_req && spim_reg_we && (spim_reg_addr != IMEM_WDATA)) begin // Indirect memory Write
spim_reg_ack <= 1'b1;
end else if (spim_fifo_rdata_req && (spim_m1_rrdy == 1)) begin // Indirect mem Read
// If FIFO Read DATA case, Make sure that there Data is read from
// External SPI Memory
spim_reg_ack <= 1'b1;
spim_reg_rdata <= reg_rdata;
- end else if (spim_reg_req && spim_reg_we == 0 && (spim_reg_addr != REG_SPIRDATA)) begin // Normal Read
+ end else if (spim_reg_req && spim_reg_we == 0 && (spim_reg_addr != IMEM_RDATA)) begin // Normal Read
// Read other than FIFO Read Data case
spim_reg_ack <= 1'b1;
spim_reg_rdata <= reg_rdata;
@@ -477,7 +477,7 @@
spi_clk_div <= spim_reg_wdata[15:8];
end
end
- MEM_CTRL1: begin // This register control Direct Memory Access Type
+ DMEM_CTRL1: begin // This register control Direct Memory Access Type
if ( spim_reg_be[0] == 1 ) begin
cfg_m0_cs_reg <= spim_reg_wdata[3:0]; // Chip Select for Memory Interface
cfg_m0_spi_mode <= spim_reg_wdata[5:4]; // SPI Mode, 0 - Normal, 1- Double, 2 - Qard, 3 - QDDR
@@ -487,7 +487,7 @@
cfg_m0_fsm_reset <= spim_reg_wdata[8];
end
end
- MEM_CTRL2: begin // This register control Direct Memory Access Type
+ DMEM_CTRL2: begin // This register control Direct Memory Access Type
if ( spim_reg_be[0] == 1 ) begin
cfg_m0_cmd_reg <= spim_reg_wdata[7:0];
end
@@ -503,7 +503,7 @@
cfg_m0_data_cnt[7:0] <= spim_reg_wdata[31:24];
end
end
- REG_CTRL1: begin
+ IMEM_CTRL1: begin
if ( spim_reg_be[0] == 1 ) begin
cfg_m1_cs_reg <= spim_reg_wdata[3:0]; // Chip Select for Memory Interface
cfg_m1_spi_mode <= spim_reg_wdata[5:4]; // SPI Mode, 0 - Normal, 1- Double, 2 - Qard
@@ -513,7 +513,7 @@
cfg_m1_fsm_reset <= spim_reg_wdata[8];
end
end
- REG_CTRL2: begin // This register control Direct Memory Access Type
+ IMEM_CTRL2: begin // This register control Direct Memory Access Type
if ( spim_reg_be[0] == 1 ) begin
cfg_m1_cmd_reg <= spim_reg_wdata[7:0];
end
@@ -529,7 +529,7 @@
cfg_m1_data_cnt[7:0] <= spim_reg_wdata[31:24];
end
end
- REG_SPIADR: begin
+ IMEM_ADDR: begin
for (byte_index = 0; byte_index < 4; byte_index = byte_index+1 )
if ( spim_reg_be[byte_index] == 1 )
cfg_m1_addr[byte_index*8 +: 8] <= spim_reg_wdata[(byte_index*8) +: 8];
@@ -548,14 +548,14 @@
if(spim_reg_req) begin
case(spim_reg_addr)
GLBL_CTRL: reg_rdata[31:0] = {16'h0,spi_clk_div,4'h0,cfg_cs_late,cfg_cs_early};
- MEM_CTRL1: reg_rdata[31:0] = {23'h0,cfg_m0_fsm_reset,cfg_m0_spi_switch,cfg_m0_spi_mode,cfg_m0_cs_reg};
- MEM_CTRL2: reg_rdata[31:0] = {cfg_m0_data_cnt,cfg_m0_dummy_cnt,cfg_m0_addr_cnt,cfg_m0_spi_seq,cfg_m0_mode_reg,cfg_m0_cmd_reg};
- REG_CTRL1: reg_rdata[31:0] = {23'h0, cfg_m1_fsm_reset,cfg_m1_spi_switch,cfg_m1_spi_mode,cfg_m1_cs_reg};
- REG_CTRL2: reg_rdata[31:0] = {cfg_m1_data_cnt,cfg_m1_dummy_cnt,cfg_m1_addr_cnt,cfg_m1_spi_seq,cfg_m1_mode_reg,cfg_m1_cmd_reg};
- REG_SPIADR: reg_rdata[31:0] = cfg_m1_addr;
- REG_SPIWDATA: reg_rdata[31:0] = cfg_m1_wdata;
- REG_SPIRDATA: reg_rdata[31:0] = cfg_m1_rdata;
- REG_STATUS: reg_rdata[31:0] = spi_debug;
+ DMEM_CTRL1: reg_rdata[31:0] = {23'h0,cfg_m0_fsm_reset,cfg_m0_spi_switch,cfg_m0_spi_mode,cfg_m0_cs_reg};
+ DMEM_CTRL2: reg_rdata[31:0] = {cfg_m0_data_cnt,cfg_m0_dummy_cnt,cfg_m0_addr_cnt,cfg_m0_spi_seq,cfg_m0_mode_reg,cfg_m0_cmd_reg};
+ IMEM_CTRL1: reg_rdata[31:0] = {23'h0, cfg_m1_fsm_reset,cfg_m1_spi_switch,cfg_m1_spi_mode,cfg_m1_cs_reg};
+ IMEM_CTRL2: reg_rdata[31:0] = {cfg_m1_data_cnt,cfg_m1_dummy_cnt,cfg_m1_addr_cnt,cfg_m1_spi_seq,cfg_m1_mode_reg,cfg_m1_cmd_reg};
+ IMEM_ADDR: reg_rdata[31:0] = cfg_m1_addr;
+ IMEM_WDATA: reg_rdata[31:0] = cfg_m1_wdata;
+ IMEM_RDATA: reg_rdata[31:0] = cfg_m1_rdata;
+ SPI_STATUS: reg_rdata[31:0] = spi_debug;
endcase
end
end
